3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * SPDX-License-Identifier: GPL-2.0+
13 #include <linux/compiler.h>
15 DECLARE_GLOBAL_DATA_PTR;
17 #if !defined(CONFIG_8xx_CONS_NONE) /* No Console at all */
19 #if defined(CONFIG_8xx_CONS_SMC1) /* Console on SMC1 */
21 #define PROFF_SMC PROFF_SMC1
22 #define CPM_CR_CH_SMC CPM_CR_CH_SMC1
24 #elif defined(CONFIG_8xx_CONS_SMC2) /* Console on SMC2 */
26 #define PROFF_SMC PROFF_SMC2
27 #define CPM_CR_CH_SMC CPM_CR_CH_SMC2
29 #endif /* CONFIG_8xx_CONS_SMCx */
31 #if defined(CONFIG_8xx_CONS_SCC1) /* Console on SCC1 */
33 #define PROFF_SCC PROFF_SCC1
34 #define CPM_CR_CH_SCC CPM_CR_CH_SCC1
36 #elif defined(CONFIG_8xx_CONS_SCC2) /* Console on SCC2 */
38 #define PROFF_SCC PROFF_SCC2
39 #define CPM_CR_CH_SCC CPM_CR_CH_SCC2
41 #elif defined(CONFIG_8xx_CONS_SCC3) /* Console on SCC3 */
43 #define PROFF_SCC PROFF_SCC3
44 #define CPM_CR_CH_SCC CPM_CR_CH_SCC3
46 #elif defined(CONFIG_8xx_CONS_SCC4) /* Console on SCC4 */
48 #define PROFF_SCC PROFF_SCC4
49 #define CPM_CR_CH_SCC CPM_CR_CH_SCC4
51 #endif /* CONFIG_8xx_CONS_SCCx */
53 #if !defined(CONFIG_SYS_SMC_RXBUFLEN)
54 #define CONFIG_SYS_SMC_RXBUFLEN 1
55 #define CONFIG_SYS_MAXIDLE 0
57 #if !defined(CONFIG_SYS_MAXIDLE)
58 #error "you must define CONFIG_SYS_MAXIDLE"
62 typedef volatile struct serialbuffer {
63 cbd_t rxbd; /* Rx BD */
64 cbd_t txbd; /* Tx BD */
65 uint rxindex; /* index for next character to read */
66 volatile uchar rxbuf[CONFIG_SYS_SMC_RXBUFLEN];/* rx buffers */
67 volatile uchar txbuf; /* tx buffers */
70 static void serial_setdivisor(volatile cpm8xx_t *cp)
72 int divisor=(gd->cpu_clk + 8*gd->baudrate)/16/gd->baudrate;
74 if(divisor/16>0x1000) {
75 /* bad divisor, assume 50MHz clock and 9600 baud */
76 divisor=(50*1000*1000 + 8*9600)/16/9600;
79 #ifdef CONFIG_SYS_BRGCLK_PRESCALE
80 divisor /= CONFIG_SYS_BRGCLK_PRESCALE;
84 cp->cp_brgc1=((divisor-1)<<1) | CPM_BRG_EN;
86 cp->cp_brgc1=((divisor/16-1)<<1) | CPM_BRG_EN | CPM_BRG_DIV16;
90 #if (defined (CONFIG_8xx_CONS_SMC1) || defined (CONFIG_8xx_CONS_SMC2))
93 * Minimal serial functions needed to use one of the SMC ports
94 * as serial console interface.
97 static void smc_setbrg (void)
99 volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
100 volatile cpm8xx_t *cp = &(im->im_cpm);
102 /* Set up the baud rate generator.
103 * See 8xx_io/commproc.c for details.
108 cp->cp_simode = 0x00000000;
110 serial_setdivisor(cp);
113 static int smc_init (void)
115 volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
117 volatile smc_uart_t *up;
118 volatile cpm8xx_t *cp = &(im->im_cpm);
119 #if (!defined(CONFIG_8xx_CONS_SMC1)) && (defined(CONFIG_MPC823) || defined(CONFIG_MPC850))
120 volatile iop8xx_t *ip = (iop8xx_t *)&(im->im_ioport);
123 volatile serialbuffer_t *rtx;
125 /* initialize pointers to SMC */
127 sp = (smc_t *) &(cp->cp_smc[SMC_INDEX]);
128 up = (smc_uart_t *) &cp->cp_dparam[PROFF_SMC];
129 #ifdef CONFIG_SYS_SMC_UCODE_PATCH
130 up = (smc_uart_t *) &cp->cp_dpmem[up->smc_rpbase];
132 /* Disable relocation */
136 /* Disable transmitter/receiver. */
137 sp->smc_smcmr &= ~(SMCMR_REN | SMCMR_TEN);
140 im->im_siu_conf.sc_sdcr = 1;
142 /* clear error conditions */
143 #ifdef CONFIG_SYS_SDSR
144 im->im_sdma.sdma_sdsr = CONFIG_SYS_SDSR;
146 im->im_sdma.sdma_sdsr = 0x83;
149 /* clear SDMA interrupt mask */
150 #ifdef CONFIG_SYS_SDMR
151 im->im_sdma.sdma_sdmr = CONFIG_SYS_SDMR;
153 im->im_sdma.sdma_sdmr = 0x00;
156 #if defined(CONFIG_8xx_CONS_SMC1)
157 /* Use Port B for SMC1 instead of other functions. */
158 cp->cp_pbpar |= 0x000000c0;
159 cp->cp_pbdir &= ~0x000000c0;
160 cp->cp_pbodr &= ~0x000000c0;
161 #else /* CONFIG_8xx_CONS_SMC2 */
162 # if defined(CONFIG_MPC823) || defined(CONFIG_MPC850)
163 /* Use Port A for SMC2 instead of other functions. */
164 ip->iop_papar |= 0x00c0;
165 ip->iop_padir &= ~0x00c0;
166 ip->iop_paodr &= ~0x00c0;
167 # else /* must be a 860 then */
168 /* Use Port B for SMC2 instead of other functions.
170 cp->cp_pbpar |= 0x00000c00;
171 cp->cp_pbdir &= ~0x00000c00;
172 cp->cp_pbodr &= ~0x00000c00;
176 /* Set the physical address of the host memory buffers in
177 * the buffer descriptors.
179 dpaddr = CPM_SERIAL_BASE;
181 rtx = (serialbuffer_t *)&cp->cp_dpmem[dpaddr];
182 /* Allocate space for two buffer descriptors in the DP ram.
183 * For now, this address seems OK, but it may have to
184 * change with newer versions of the firmware.
185 * damm: allocating space after the two buffers for rx/tx data
188 rtx->rxbd.cbd_bufaddr = (uint) &rtx->rxbuf;
189 rtx->rxbd.cbd_sc = 0;
191 rtx->txbd.cbd_bufaddr = (uint) &rtx->txbuf;
192 rtx->txbd.cbd_sc = 0;
194 /* Set up the uart parameters in the parameter ram. */
195 up->smc_rbase = dpaddr;
196 up->smc_tbase = dpaddr+sizeof(cbd_t);
197 up->smc_rfcr = SMC_EB;
198 up->smc_tfcr = SMC_EB;
199 #if defined (CONFIG_SYS_SMC_UCODE_PATCH)
200 up->smc_rbptr = up->smc_rbase;
201 up->smc_tbptr = up->smc_tbase;
206 /* Set UART mode, 8 bit, no parity, one stop.
207 * Enable receive and transmit.
209 sp->smc_smcmr = smcr_mk_clen(9) | SMCMR_SM_UART;
211 /* Mask all interrupts and remove anything pending.
216 #ifdef CONFIG_SYS_SPC1920_SMC1_CLK4
217 /* clock source is PLD */
219 /* set freq to 19200 Baud */
220 *((volatile uchar *) CONFIG_SYS_SPC1920_PLD_BASE+6) = 0x3;
221 /* configure clk4 as input */
222 im->im_ioport.iop_pdpar |= 0x800;
223 im->im_ioport.iop_pddir &= ~0x800;
225 cp->cp_simode = ((cp->cp_simode & ~0xf000) | 0x7000);
227 /* Set up the baud rate generator */
231 /* Make the first buffer the only buffer. */
232 rtx->txbd.cbd_sc |= BD_SC_WRAP;
233 rtx->rxbd.cbd_sc |= BD_SC_EMPTY | BD_SC_WRAP;
235 /* single/multi character receive. */
236 up->smc_mrblr = CONFIG_SYS_SMC_RXBUFLEN;
237 up->smc_maxidl = CONFIG_SYS_MAXIDLE;
240 /* Initialize Tx/Rx parameters. */
241 while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */
244 cp->cp_cpcr = mk_cr_cmd(CPM_CR_CH_SMC, CPM_CR_INIT_TRX) | CPM_CR_FLG;
246 while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */
249 /* Enable transmitter/receiver. */
250 sp->smc_smcmr |= SMCMR_REN | SMCMR_TEN;
256 smc_putc(const char c)
258 volatile smc_uart_t *up;
259 volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
260 volatile cpm8xx_t *cpmp = &(im->im_cpm);
261 volatile serialbuffer_t *rtx;
266 up = (smc_uart_t *)&cpmp->cp_dparam[PROFF_SMC];
267 #ifdef CONFIG_SYS_SMC_UCODE_PATCH
268 up = (smc_uart_t *) &cpmp->cp_dpmem[up->smc_rpbase];
271 rtx = (serialbuffer_t *)&cpmp->cp_dpmem[up->smc_rbase];
273 /* Wait for last character to go. */
275 rtx->txbd.cbd_datlen = 1;
276 rtx->txbd.cbd_sc |= BD_SC_READY;
279 while (rtx->txbd.cbd_sc & BD_SC_READY) {
286 smc_puts (const char *s)
296 volatile smc_uart_t *up;
297 volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
298 volatile cpm8xx_t *cpmp = &(im->im_cpm);
299 volatile serialbuffer_t *rtx;
302 up = (smc_uart_t *)&cpmp->cp_dparam[PROFF_SMC];
303 #ifdef CONFIG_SYS_SMC_UCODE_PATCH
304 up = (smc_uart_t *) &cpmp->cp_dpmem[up->smc_rpbase];
306 rtx = (serialbuffer_t *)&cpmp->cp_dpmem[up->smc_rbase];
308 /* Wait for character to show up. */
309 while (rtx->rxbd.cbd_sc & BD_SC_EMPTY)
312 /* the characters are read one by one,
313 * use the rxindex to know the next char to deliver
315 c = *(unsigned char *) (rtx->rxbd.cbd_bufaddr+rtx->rxindex);
318 /* check if all char are readout, then make prepare for next receive */
319 if (rtx->rxindex >= rtx->rxbd.cbd_datlen) {
321 rtx->rxbd.cbd_sc |= BD_SC_EMPTY;
329 volatile smc_uart_t *up;
330 volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
331 volatile cpm8xx_t *cpmp = &(im->im_cpm);
332 volatile serialbuffer_t *rtx;
334 up = (smc_uart_t *)&cpmp->cp_dparam[PROFF_SMC];
335 #ifdef CONFIG_SYS_SMC_UCODE_PATCH
336 up = (smc_uart_t *) &cpmp->cp_dpmem[up->smc_rpbase];
339 rtx = (serialbuffer_t *)&cpmp->cp_dpmem[up->smc_rbase];
341 return !(rtx->rxbd.cbd_sc & BD_SC_EMPTY);
344 struct serial_device serial_smc_device =
346 .name = "serial_smc",
349 .setbrg = smc_setbrg,
356 #endif /* CONFIG_8xx_CONS_SMC1 || CONFIG_8xx_CONS_SMC2 */
358 #if defined(CONFIG_8xx_CONS_SCC1) || defined(CONFIG_8xx_CONS_SCC2) || \
359 defined(CONFIG_8xx_CONS_SCC3) || defined(CONFIG_8xx_CONS_SCC4)
364 volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
365 volatile cpm8xx_t *cp = &(im->im_cpm);
367 /* Set up the baud rate generator.
368 * See 8xx_io/commproc.c for details.
373 cp->cp_sicr &= ~(0x000000FF << (8 * SCC_INDEX));
375 serial_setdivisor(cp);
378 static int scc_init (void)
380 volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
382 volatile scc_uart_t *up;
383 volatile cbd_t *tbdf, *rbdf;
384 volatile cpm8xx_t *cp = &(im->im_cpm);
386 #if (SCC_INDEX != 2) || !defined(CONFIG_MPC850)
387 volatile iop8xx_t *ip = (iop8xx_t *)&(im->im_ioport);
390 /* initialize pointers to SCC */
392 sp = (scc_t *) &(cp->cp_scc[SCC_INDEX]);
393 up = (scc_uart_t *) &cp->cp_dparam[PROFF_SCC];
395 /* Disable transmitter/receiver. */
396 sp->scc_gsmrl &= ~(SCC_GSMRL_ENR | SCC_GSMRL_ENT);
398 #if (SCC_INDEX == 2) && defined(CONFIG_MPC850)
400 * The MPC850 has SCC3 on Port B
402 cp->cp_pbpar |= 0x06;
403 cp->cp_pbdir &= ~0x06;
404 cp->cp_pbodr &= ~0x06;
406 #elif (SCC_INDEX < 2)
408 * Standard configuration for SCC's is on Part A
410 ip->iop_papar |= ((3 << (2 * SCC_INDEX)));
411 ip->iop_padir &= ~((3 << (2 * SCC_INDEX)));
412 ip->iop_paodr &= ~((3 << (2 * SCC_INDEX)));
415 /* Allocate space for two buffer descriptors in the DP ram. */
416 dpaddr = dpram_alloc_align(sizeof(cbd_t)*2 + 2, 8);
419 im->im_siu_conf.sc_sdcr = 0x0001;
421 /* Set the physical address of the host memory buffers in
422 * the buffer descriptors.
425 rbdf = (cbd_t *)&cp->cp_dpmem[dpaddr];
426 rbdf->cbd_bufaddr = (uint) (rbdf+2);
429 tbdf->cbd_bufaddr = ((uint) (rbdf+2)) + 1;
432 /* Set up the baud rate generator. */
435 /* Set up the uart parameters in the parameter ram. */
436 up->scc_genscc.scc_rbase = dpaddr;
437 up->scc_genscc.scc_tbase = dpaddr+sizeof(cbd_t);
439 /* Initialize Tx/Rx parameters. */
440 while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */
442 cp->cp_cpcr = mk_cr_cmd(CPM_CR_CH_SCC, CPM_CR_INIT_TRX) | CPM_CR_FLG;
444 while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */
447 up->scc_genscc.scc_rfcr = SCC_EB | 0x05;
448 up->scc_genscc.scc_tfcr = SCC_EB | 0x05;
450 up->scc_genscc.scc_mrblr = 1; /* Single character receive */
451 up->scc_maxidl = 0; /* disable max idle */
452 up->scc_brkcr = 1; /* send one break character on stop TX */
460 up->scc_char1 = 0x8000;
461 up->scc_char2 = 0x8000;
462 up->scc_char3 = 0x8000;
463 up->scc_char4 = 0x8000;
464 up->scc_char5 = 0x8000;
465 up->scc_char6 = 0x8000;
466 up->scc_char7 = 0x8000;
467 up->scc_char8 = 0x8000;
468 up->scc_rccm = 0xc0ff;
470 /* Set low latency / small fifo. */
471 sp->scc_gsmrh = SCC_GSMRH_RFW;
473 /* Set SCC(x) clock mode to 16x
474 * See 8xx_io/commproc.c for details.
479 /* Set UART mode, clock divider 16 on Tx and Rx */
480 sp->scc_gsmrl &= ~0xF;
482 (SCC_GSMRL_MODE_UART | SCC_GSMRL_TDCR_16 | SCC_GSMRL_RDCR_16);
485 sp->scc_psmr |= SCU_PSMR_CL;
487 /* Mask all interrupts and remove anything pending. */
489 sp->scc_scce = 0xffff;
490 sp->scc_dsr = 0x7e7e;
491 sp->scc_psmr = 0x3000;
493 /* Make the first buffer the only buffer. */
494 tbdf->cbd_sc |= BD_SC_WRAP;
495 rbdf->cbd_sc |= BD_SC_EMPTY | BD_SC_WRAP;
497 /* Enable transmitter/receiver. */
498 sp->scc_gsmrl |= (SCC_GSMRL_ENR | SCC_GSMRL_ENT);
504 scc_putc(const char c)
506 volatile cbd_t *tbdf;
508 volatile scc_uart_t *up;
509 volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
510 volatile cpm8xx_t *cpmp = &(im->im_cpm);
515 up = (scc_uart_t *)&cpmp->cp_dparam[PROFF_SCC];
517 tbdf = (cbd_t *)&cpmp->cp_dpmem[up->scc_genscc.scc_tbase];
519 /* Wait for last character to go. */
521 buf = (char *)tbdf->cbd_bufaddr;
524 tbdf->cbd_datlen = 1;
525 tbdf->cbd_sc |= BD_SC_READY;
528 while (tbdf->cbd_sc & BD_SC_READY) {
535 scc_puts (const char *s)
545 volatile cbd_t *rbdf;
546 volatile unsigned char *buf;
547 volatile scc_uart_t *up;
548 volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
549 volatile cpm8xx_t *cpmp = &(im->im_cpm);
552 up = (scc_uart_t *)&cpmp->cp_dparam[PROFF_SCC];
554 rbdf = (cbd_t *)&cpmp->cp_dpmem[up->scc_genscc.scc_rbase];
556 /* Wait for character to show up. */
557 buf = (unsigned char *)rbdf->cbd_bufaddr;
559 while (rbdf->cbd_sc & BD_SC_EMPTY)
563 rbdf->cbd_sc |= BD_SC_EMPTY;
571 volatile cbd_t *rbdf;
572 volatile scc_uart_t *up;
573 volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
574 volatile cpm8xx_t *cpmp = &(im->im_cpm);
576 up = (scc_uart_t *)&cpmp->cp_dparam[PROFF_SCC];
578 rbdf = (cbd_t *)&cpmp->cp_dpmem[up->scc_genscc.scc_rbase];
580 return(!(rbdf->cbd_sc & BD_SC_EMPTY));
583 struct serial_device serial_scc_device =
585 .name = "serial_scc",
588 .setbrg = scc_setbrg,
595 #endif /* CONFIG_8xx_CONS_SCCx */
597 __weak struct serial_device *default_serial_console(void)
599 #if defined(CONFIG_8xx_CONS_SMC1) || defined(CONFIG_8xx_CONS_SMC2)
600 return &serial_smc_device;
602 return &serial_scc_device;
606 void mpc8xx_serial_initialize(void)
608 #if defined(CONFIG_8xx_CONS_SMC1) || defined(CONFIG_8xx_CONS_SMC2)
609 serial_register(&serial_smc_device);
611 #if defined(CONFIG_8xx_CONS_SCC1) || defined(CONFIG_8xx_CONS_SCC2) || \
612 defined(CONFIG_8xx_CONS_SCC3) || defined(CONFIG_8xx_CONS_SCC4)
613 serial_register(&serial_scc_device);
617 #if defined(CONFIG_CMD_KGDB)
620 kgdb_serial_init(void)
624 if (strcmp(default_serial_console()->name, "serial_smc") == 0)
626 #if defined(CONFIG_8xx_CONS_SMC1)
628 #elif defined(CONFIG_8xx_CONS_SMC2)
632 else if (strcmp(default_serial_console()->name, "serial_scc") == 0)
634 #if defined(CONFIG_8xx_CONS_SCC1)
636 #elif defined(CONFIG_8xx_CONS_SCC2)
638 #elif defined(CONFIG_8xx_CONS_SCC3)
640 #elif defined(CONFIG_8xx_CONS_SCC4)
647 serial_printf("[on %s%d] ", default_serial_console()->name, i);
658 putDebugStr (const char *str)
666 return serial_getc();
670 kgdb_interruptible (int yes)
676 #endif /* CONFIG_8xx_CONS_NONE */