2 * Copyright 2008-2012 Freescale Semiconductor, Inc.
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * Version 2 as published by the Free Software Foundation.
10 * Generic driver for Freescale DDR/DDR2/DDR3 memory controller.
11 * Based on code from spd_sdram.c
12 * Author: James Yang [at freescale.com]
17 #include <asm/fsl_ddr_sdram.h>
18 #include <asm/fsl_law.h>
22 void fsl_ddr_set_lawbar(
23 const common_timing_params_t *memctl_common_params,
24 unsigned int memctl_interleaved,
25 unsigned int ctrl_num);
26 void fsl_ddr_set_intl3r(const unsigned int granule_size);
28 /* processor specific function */
29 extern void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
30 unsigned int ctrl_num);
32 #if defined(SPD_EEPROM_ADDRESS) || \
33 defined(SPD_EEPROM_ADDRESS1) || defined(SPD_EEPROM_ADDRESS2) || \
34 defined(SPD_EEPROM_ADDRESS3) || defined(SPD_EEPROM_ADDRESS4)
35 #if (CONFIG_NUM_DDR_CONTROLLERS == 1) && (CONFIG_DIMM_SLOTS_PER_CTLR == 1)
36 u8 spd_i2c_addr[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR] = {
37 [0][0] = SPD_EEPROM_ADDRESS,
39 #elif (CONFIG_NUM_DDR_CONTROLLERS == 1) && (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
40 u8 spd_i2c_addr[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR] = {
41 [0][0] = SPD_EEPROM_ADDRESS1, /* controller 1 */
42 [0][1] = SPD_EEPROM_ADDRESS2, /* controller 1 */
44 #elif (CONFIG_NUM_DDR_CONTROLLERS == 2) && (CONFIG_DIMM_SLOTS_PER_CTLR == 1)
45 u8 spd_i2c_addr[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR] = {
46 [0][0] = SPD_EEPROM_ADDRESS1, /* controller 1 */
47 [1][0] = SPD_EEPROM_ADDRESS2, /* controller 2 */
49 #elif (CONFIG_NUM_DDR_CONTROLLERS == 2) && (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
50 u8 spd_i2c_addr[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR] = {
51 [0][0] = SPD_EEPROM_ADDRESS1, /* controller 1 */
52 [0][1] = SPD_EEPROM_ADDRESS2, /* controller 1 */
53 [1][0] = SPD_EEPROM_ADDRESS3, /* controller 2 */
54 [1][1] = SPD_EEPROM_ADDRESS4, /* controller 2 */
56 #elif (CONFIG_NUM_DDR_CONTROLLERS == 3) && (CONFIG_DIMM_SLOTS_PER_CTLR == 1)
57 u8 spd_i2c_addr[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR] = {
58 [0][0] = SPD_EEPROM_ADDRESS1, /* controller 1 */
59 [1][0] = SPD_EEPROM_ADDRESS2, /* controller 2 */
60 [2][0] = SPD_EEPROM_ADDRESS3, /* controller 3 */
62 #elif (CONFIG_NUM_DDR_CONTROLLERS == 3) && (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
63 u8 spd_i2c_addr[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR] = {
64 [0][0] = SPD_EEPROM_ADDRESS1, /* controller 1 */
65 [0][1] = SPD_EEPROM_ADDRESS2, /* controller 1 */
66 [1][0] = SPD_EEPROM_ADDRESS3, /* controller 2 */
67 [1][1] = SPD_EEPROM_ADDRESS4, /* controller 2 */
68 [2][0] = SPD_EEPROM_ADDRESS5, /* controller 3 */
69 [2][1] = SPD_EEPROM_ADDRESS6, /* controller 3 */
74 static void __get_spd(generic_spd_eeprom_t *spd, u8 i2c_address)
76 int ret = i2c_read(i2c_address, 0, 1, (uchar *)spd,
77 sizeof(generic_spd_eeprom_t));
80 printf("DDR: failed to read SPD from address %u\n", i2c_address);
81 memset(spd, 0, sizeof(generic_spd_eeprom_t));
85 __attribute__((weak, alias("__get_spd")))
86 void get_spd(generic_spd_eeprom_t *spd, u8 i2c_address);
88 void fsl_ddr_get_spd(generic_spd_eeprom_t *ctrl_dimms_spd,
89 unsigned int ctrl_num)
92 unsigned int i2c_address = 0;
94 if (ctrl_num >= CONFIG_NUM_DDR_CONTROLLERS) {
95 printf("%s unexpected ctrl_num = %u\n", __FUNCTION__, ctrl_num);
99 for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) {
100 i2c_address = spd_i2c_addr[ctrl_num][i];
101 get_spd(&(ctrl_dimms_spd[i]), i2c_address);
105 void fsl_ddr_get_spd(generic_spd_eeprom_t *ctrl_dimms_spd,
106 unsigned int ctrl_num)
109 #endif /* SPD_EEPROM_ADDRESSx */
113 * - Same number of CONFIG_DIMM_SLOTS_PER_CTLR on each controller
114 * - Same memory data bus width on all controllers
118 * The memory controller and associated documentation use confusing
119 * terminology when referring to the orgranization of DRAM.
121 * Here is a terminology translation table:
123 * memory controller/documention |industry |this code |signals
124 * -------------------------------|-----------|-----------|-----------------
125 * physical bank/bank |rank |rank |chip select (CS)
126 * logical bank/sub-bank |bank |bank |bank address (BA)
127 * page/row |row |page |row address
128 * ??? |column |column |column address
130 * The naming confusion is further exacerbated by the descriptions of the
131 * memory controller interleaving feature, where accesses are interleaved
132 * _BETWEEN_ two seperate memory controllers. This is configured only in
133 * CS0_CONFIG[INTLV_CTL] of each memory controller.
135 * memory controller documentation | number of chip selects
136 * | per memory controller supported
137 * --------------------------------|-----------------------------------------
138 * cache line interleaving | 1 (CS0 only)
139 * page interleaving | 1 (CS0 only)
140 * bank interleaving | 1 (CS0 only)
141 * superbank interleraving | depends on bank (chip select)
142 * | interleraving [rank interleaving]
143 * | mode used on every memory controller
145 * Even further confusing is the existence of the interleaving feature
146 * _WITHIN_ each memory controller. The feature is referred to in
147 * documentation as chip select interleaving or bank interleaving,
148 * although it is configured in the DDR_SDRAM_CFG field.
150 * Name of field | documentation name | this code
151 * -----------------------------|-----------------------|------------------
152 * DDR_SDRAM_CFG[BA_INTLV_CTL] | Bank (chip select) | rank interleaving
156 const char *step_string_tbl[] = {
158 "STEP_COMPUTE_DIMM_PARMS",
159 "STEP_COMPUTE_COMMON_PARMS",
161 "STEP_ASSIGN_ADDRESSES",
167 const char * step_to_string(unsigned int step) {
169 unsigned int s = __ilog2(step);
171 if ((1 << s) != step)
172 return step_string_tbl[7];
174 return step_string_tbl[s];
177 unsigned long long step_assign_addresses(fsl_ddr_info_t *pinfo,
178 unsigned int dbw_cap_adj[])
181 unsigned long long total_mem, current_mem_base, total_ctlr_mem;
182 unsigned long long rank_density, ctlr_density = 0;
185 * If a reduced data width is requested, but the SPD
186 * specifies a physically wider device, adjust the
187 * computed dimm capacities accordingly before
188 * assigning addresses.
190 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
191 unsigned int found = 0;
193 switch (pinfo->memctl_opts[i].data_bus_width) {
196 for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
198 if (!pinfo->dimm_params[i][j].n_ranks)
200 dw = pinfo->dimm_params[i][j].primary_sdram_width;
201 if ((dw == 72 || dw == 64)) {
204 } else if ((dw == 40 || dw == 32)) {
213 for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
215 dw = pinfo->dimm_params[i][j].data_width;
216 if (pinfo->dimm_params[i][j].n_ranks
217 && (dw == 72 || dw == 64)) {
219 * FIXME: can't really do it
220 * like this because this just
221 * further reduces the memory
237 printf("unexpected data bus width "
238 "specified controller %u\n", i);
241 debug("dbw_cap_adj[%d]=%d\n", i, dbw_cap_adj[i]);
244 current_mem_base = 0ull;
246 if (pinfo->memctl_opts[0].memctl_interleaving) {
247 rank_density = pinfo->dimm_params[0][0].rank_density >>
249 switch (pinfo->memctl_opts[0].ba_intlv_ctl &
250 FSL_DDR_CS0_CS1_CS2_CS3) {
251 case FSL_DDR_CS0_CS1_CS2_CS3:
252 ctlr_density = 4 * rank_density;
254 case FSL_DDR_CS0_CS1:
255 case FSL_DDR_CS0_CS1_AND_CS2_CS3:
256 ctlr_density = 2 * rank_density;
258 case FSL_DDR_CS2_CS3:
260 ctlr_density = rank_density;
263 debug("rank density is 0x%llx, ctlr density is 0x%llx\n",
264 rank_density, ctlr_density);
265 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
266 if (pinfo->memctl_opts[i].memctl_interleaving) {
267 switch (pinfo->memctl_opts[i].memctl_interleaving_mode) {
268 case FSL_DDR_CACHE_LINE_INTERLEAVING:
269 case FSL_DDR_PAGE_INTERLEAVING:
270 case FSL_DDR_BANK_INTERLEAVING:
271 case FSL_DDR_SUPERBANK_INTERLEAVING:
272 total_ctlr_mem = 2 * ctlr_density;
274 case FSL_DDR_3WAY_1KB_INTERLEAVING:
275 case FSL_DDR_3WAY_4KB_INTERLEAVING:
276 case FSL_DDR_3WAY_8KB_INTERLEAVING:
277 total_ctlr_mem = 3 * ctlr_density;
279 case FSL_DDR_4WAY_1KB_INTERLEAVING:
280 case FSL_DDR_4WAY_4KB_INTERLEAVING:
281 case FSL_DDR_4WAY_8KB_INTERLEAVING:
282 total_ctlr_mem = 4 * ctlr_density;
285 panic("Unknown interleaving mode");
287 pinfo->common_timing_params[i].base_address =
289 pinfo->common_timing_params[i].total_mem =
291 total_mem = current_mem_base + total_ctlr_mem;
292 debug("ctrl %d base 0x%llx\n", i, current_mem_base);
293 debug("ctrl %d total 0x%llx\n", i, total_ctlr_mem);
295 /* when 3rd controller not interleaved */
296 current_mem_base = total_mem;
298 pinfo->common_timing_params[i].base_address =
300 for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
301 unsigned long long cap =
302 pinfo->dimm_params[i][j].capacity >> dbw_cap_adj[i];
303 pinfo->dimm_params[i][j].base_address =
305 debug("ctrl %d dimm %d base 0x%llx\n", i, j, current_mem_base);
306 current_mem_base += cap;
307 total_ctlr_mem += cap;
309 debug("ctrl %d total 0x%llx\n", i, total_ctlr_mem);
310 pinfo->common_timing_params[i].total_mem =
312 total_mem += total_ctlr_mem;
317 * Simple linear assignment if memory
318 * controllers are not interleaved.
320 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
322 pinfo->common_timing_params[i].base_address =
324 for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
325 /* Compute DIMM base addresses. */
326 unsigned long long cap =
327 pinfo->dimm_params[i][j].capacity >> dbw_cap_adj[i];
328 pinfo->dimm_params[i][j].base_address =
330 debug("ctrl %d dimm %d base 0x%llx\n", i, j, current_mem_base);
331 current_mem_base += cap;
332 total_ctlr_mem += cap;
334 debug("ctrl %d total 0x%llx\n", i, total_ctlr_mem);
335 pinfo->common_timing_params[i].total_mem =
337 total_mem += total_ctlr_mem;
340 debug("Total mem by %s is 0x%llx\n", __func__, total_mem);
346 fsl_ddr_compute(fsl_ddr_info_t *pinfo, unsigned int start_step,
347 unsigned int size_only)
350 unsigned long long total_mem = 0;
352 fsl_ddr_cfg_regs_t *ddr_reg = pinfo->fsl_ddr_config_reg;
353 common_timing_params_t *timing_params = pinfo->common_timing_params;
355 /* data bus width capacity adjust shift amount */
356 unsigned int dbw_capacity_adjust[CONFIG_NUM_DDR_CONTROLLERS];
358 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
359 dbw_capacity_adjust[i] = 0;
362 debug("starting at step %u (%s)\n",
363 start_step, step_to_string(start_step));
365 switch (start_step) {
367 #if defined(CONFIG_DDR_SPD) || defined(CONFIG_SPD_EEPROM)
368 /* STEP 1: Gather all DIMM SPD data */
369 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
370 fsl_ddr_get_spd(pinfo->spd_installed_dimms[i], i);
373 case STEP_COMPUTE_DIMM_PARMS:
374 /* STEP 2: Compute DIMM parameters from SPD data */
376 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
377 for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
379 generic_spd_eeprom_t *spd =
380 &(pinfo->spd_installed_dimms[i][j]);
381 dimm_params_t *pdimm =
382 &(pinfo->dimm_params[i][j]);
384 retval = compute_dimm_parameters(spd, pdimm, i);
385 #ifdef CONFIG_SYS_DDR_RAW_TIMING
386 if (!i && !j && retval) {
387 printf("SPD error on controller %d! "
388 "Trying fallback to raw timing "
390 fsl_ddr_get_dimm_params(pdimm, i, j);
394 printf("Error: compute_dimm_parameters"
395 " non-zero returned FATAL value "
396 "for memctl=%u dimm=%u\n", i, j);
401 debug("Warning: compute_dimm_parameters"
402 " non-zero return value for memctl=%u "
408 #elif defined(CONFIG_SYS_DDR_RAW_TIMING)
409 case STEP_COMPUTE_DIMM_PARMS:
410 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
411 for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
412 dimm_params_t *pdimm =
413 &(pinfo->dimm_params[i][j]);
414 fsl_ddr_get_dimm_params(pdimm, i, j);
417 debug("Filling dimm parameters from board specific file\n");
419 case STEP_COMPUTE_COMMON_PARMS:
421 * STEP 3: Compute a common set of timing parameters
422 * suitable for all of the DIMMs on each memory controller
424 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
425 debug("Computing lowest common DIMM"
426 " parameters for memctl=%u\n", i);
427 compute_lowest_common_dimm_parameters(
428 pinfo->dimm_params[i],
430 CONFIG_DIMM_SLOTS_PER_CTLR);
433 case STEP_GATHER_OPTS:
434 /* STEP 4: Gather configuration requirements from user */
435 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
436 debug("Reloading memory controller "
437 "configuration options for memctl=%u\n", i);
439 * This "reloads" the memory controller options
440 * to defaults. If the user "edits" an option,
441 * next_step points to the step after this,
442 * which is currently STEP_ASSIGN_ADDRESSES.
444 populate_memctl_options(
445 timing_params[i].all_DIMMs_registered,
446 &pinfo->memctl_opts[i],
447 pinfo->dimm_params[i], i);
449 case STEP_ASSIGN_ADDRESSES:
450 /* STEP 5: Assign addresses to chip selects */
451 check_interleaving_options(pinfo);
452 total_mem = step_assign_addresses(pinfo, dbw_capacity_adjust);
454 case STEP_COMPUTE_REGS:
455 /* STEP 6: compute controller register values */
456 debug("FSL Memory ctrl register computation\n");
457 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
458 if (timing_params[i].ndimms_present == 0) {
459 memset(&ddr_reg[i], 0,
460 sizeof(fsl_ddr_cfg_regs_t));
464 compute_fsl_memctl_config_regs(
465 &pinfo->memctl_opts[i],
466 &ddr_reg[i], &timing_params[i],
467 pinfo->dimm_params[i],
468 dbw_capacity_adjust[i],
478 * Compute the amount of memory available just by
479 * looking for the highest valid CSn_BNDS value.
480 * This allows us to also experiment with using
481 * only CS0 when using dual-rank DIMMs.
483 unsigned int max_end = 0;
485 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
486 for (j = 0; j < CONFIG_CHIP_SELECTS_PER_CTRL; j++) {
487 fsl_ddr_cfg_regs_t *reg = &ddr_reg[i];
488 if (reg->cs[j].config & 0x80000000) {
490 end = reg->cs[j].bnds & 0xFFF;
498 total_mem = 1 + (((unsigned long long)max_end << 24ULL)
506 * fsl_ddr_sdram() -- this is the main function to be called by
507 * initdram() in the board file.
509 * It returns amount of memory configured in bytes.
511 phys_size_t fsl_ddr_sdram(void)
514 unsigned int law_memctl = LAW_TRGT_IF_DDR_1;
515 unsigned long long total_memory;
518 /* Reset info structure. */
519 memset(&info, 0, sizeof(fsl_ddr_info_t));
521 /* Compute it once normally. */
522 #ifdef CONFIG_FSL_DDR_INTERACTIVE
523 if (getenv("ddr_interactive"))
524 total_memory = fsl_ddr_interactive(&info);
527 total_memory = fsl_ddr_compute(&info, STEP_GET_SPD, 0);
529 /* Program configuration registers. */
530 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
531 debug("Programming controller %u\n", i);
532 if (info.common_timing_params[i].ndimms_present == 0) {
533 debug("No dimms present on controller %u; "
534 "skipping programming\n", i);
538 fsl_ddr_set_memctl_regs(&(info.fsl_ddr_config_reg[i]), i);
542 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
543 if (info.memctl_opts[i].memctl_interleaving) {
544 switch (info.memctl_opts[i].memctl_interleaving_mode) {
545 case FSL_DDR_CACHE_LINE_INTERLEAVING:
546 case FSL_DDR_PAGE_INTERLEAVING:
547 case FSL_DDR_BANK_INTERLEAVING:
548 case FSL_DDR_SUPERBANK_INTERLEAVING:
550 law_memctl = LAW_TRGT_IF_DDR_INTRLV;
551 fsl_ddr_set_lawbar(&info.common_timing_params[i],
554 law_memctl = LAW_TRGT_IF_DDR_INTLV_34;
555 fsl_ddr_set_lawbar(&info.common_timing_params[i],
559 case FSL_DDR_3WAY_1KB_INTERLEAVING:
560 case FSL_DDR_3WAY_4KB_INTERLEAVING:
561 case FSL_DDR_3WAY_8KB_INTERLEAVING:
562 law_memctl = LAW_TRGT_IF_DDR_INTLV_123;
564 fsl_ddr_set_intl3r(info.memctl_opts[i].memctl_interleaving_mode);
565 fsl_ddr_set_lawbar(&info.common_timing_params[i],
569 case FSL_DDR_4WAY_1KB_INTERLEAVING:
570 case FSL_DDR_4WAY_4KB_INTERLEAVING:
571 case FSL_DDR_4WAY_8KB_INTERLEAVING:
572 law_memctl = LAW_TRGT_IF_DDR_INTLV_1234;
574 fsl_ddr_set_lawbar(&info.common_timing_params[i],
576 /* place holder for future 4-way interleaving */
584 law_memctl = LAW_TRGT_IF_DDR_1;
587 law_memctl = LAW_TRGT_IF_DDR_2;
590 law_memctl = LAW_TRGT_IF_DDR_3;
593 law_memctl = LAW_TRGT_IF_DDR_4;
598 fsl_ddr_set_lawbar(&info.common_timing_params[i],
603 debug("total_memory by %s = %llu\n", __func__, total_memory);
605 #if !defined(CONFIG_PHYS_64BIT)
606 /* Check for 4G or more. Bad. */
607 if (total_memory >= (1ull << 32)) {
608 printf("Detected %lld MB of memory\n", total_memory >> 20);
609 printf(" This U-Boot only supports < 4G of DDR\n");
610 printf(" You could rebuild it with CONFIG_PHYS_64BIT\n");
611 printf(" "); /* re-align to match init_func_ram print */
612 total_memory = CONFIG_MAX_MEM_MAPPED;
620 * fsl_ddr_sdram_size() - This function only returns the size of the total
621 * memory without setting ddr control registers.
624 fsl_ddr_sdram_size(void)
627 unsigned long long total_memory = 0;
629 memset(&info, 0 , sizeof(fsl_ddr_info_t));
631 /* Compute it once normally. */
632 total_memory = fsl_ddr_compute(&info, STEP_GET_SPD, 1);