git.sur5r.net Git - u-boot/blob - arch/powerpc/cpu/mpc8xxx/ddr/options.c

   1 /*
   2  * Copyright 2008, 2010 Freescale Semiconductor, Inc.
   3  *
   4  * This program is free software; you can redistribute it and/or modify it
   5  * under the terms of the GNU General Public License as published by the Free
   6  * Software Foundation; either version 2 of the License, or (at your option)
   7  * any later version.
   8  */
   9
  10 #include <common.h>
  11 #include <hwconfig.h>
  12 #include <asm/fsl_ddr_sdram.h>
  13
  14 #include "ddr.h"
  15
  16 /* Board-specific functions defined in each board's ddr.c */
  17 extern void fsl_ddr_board_options(memctl_options_t *popts,
  18                 dimm_params_t *pdimm,
  19                 unsigned int ctrl_num);
  20
  21 unsigned int populate_memctl_options(int all_DIMMs_registered,
  22                         memctl_options_t *popts,
  23                         dimm_params_t *pdimm,
  24                         unsigned int ctrl_num)
  25 {
  26         unsigned int i;
  27
  28         /* Chip select options. */
  29
  30         /* Pick chip-select local options. */
  31         for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
  32                 /* If not DDR2, odt_rd_cfg and odt_wr_cfg need to be 0. */
  33
  34                 /* only for single CS? */
  35                 popts->cs_local_opts[i].odt_rd_cfg = 0;
  36
  37                 popts->cs_local_opts[i].odt_wr_cfg = 1;
  38                 popts->cs_local_opts[i].auto_precharge = 0;
  39         }
  40
  41         /* Pick interleaving mode. */
  42
  43         /*
  44          * 0 = no interleaving
  45          * 1 = interleaving between 2 controllers
  46          */
  47         popts->memctl_interleaving = 0;
  48
  49         /*
  50          * 0 = cacheline
  51          * 1 = page
  52          * 2 = (logical) bank
  53          * 3 = superbank (only if CS interleaving is enabled)
  54          */
  55         popts->memctl_interleaving_mode = 0;
  56
  57         /*
  58          * 0: cacheline: bit 30 of the 36-bit physical addr selects the memctl
  59          * 1: page:      bit to the left of the column bits selects the memctl
  60          * 2: bank:      bit to the left of the bank bits selects the memctl
  61          * 3: superbank: bit to the left of the chip select selects the memctl
  62          *
  63          * NOTE: ba_intlv (rank interleaving) is independent of memory
  64          * controller interleaving; it is only within a memory controller.
  65          * Must use superbank interleaving if rank interleaving is used and
  66          * memory controller interleaving is enabled.
  67          */
  68
  69         /*
  70          * 0 = no
  71          * 0x40 = CS0,CS1
  72          * 0x20 = CS2,CS3
  73          * 0x60 = CS0,CS1 + CS2,CS3
  74          * 0x04 = CS0,CS1,CS2,CS3
  75          */
  76         popts->ba_intlv_ctl = 0;
  77
  78         /* Memory Organization Parameters */
  79         popts->registered_dimm_en = all_DIMMs_registered;
  80
  81         /* Operational Mode Paramters */
  82
  83         /* Pick ECC modes */
  84 #ifdef CONFIG_DDR_ECC
  85         popts->ECC_mode = 1;              /* 0 = disabled, 1 = enabled */
  86 #else
  87         popts->ECC_mode = 0;              /* 0 = disabled, 1 = enabled */
  88 #endif
  89         popts->ECC_init_using_memctl = 1; /* 0 = use DMA, 1 = use memctl */
  90
  91         /*
  92          * Choose DQS config
  93          * 0 for DDR1
  94          * 1 for DDR2
  95          */
  96 #if defined(CONFIG_FSL_DDR1)
  97         popts->DQS_config = 0;
  98 #elif defined(CONFIG_FSL_DDR2) || defined(CONFIG_FSL_DDR3)
  99         popts->DQS_config = 1;
 100 #endif
 101
 102         /* Choose self-refresh during sleep. */
 103         popts->self_refresh_in_sleep = 1;
 104
 105         /* Choose dynamic power management mode. */
 106         popts->dynamic_power = 0;
 107
 108         /* 0 = 64-bit, 1 = 32-bit, 2 = 16-bit */
 109         popts->data_bus_width = 0;
 110
 111         /* Choose burst length. */
 112 #if defined(CONFIG_FSL_DDR3)
 113 #if defined(CONFIG_E500MC)
 114         popts->OTF_burst_chop_en = 0;   /* on-the-fly burst chop disable */
 115         popts->burst_length = DDR_BL8;  /* Fixed 8-beat burst len */
 116 #else
 117         popts->OTF_burst_chop_en = 1;   /* on-the-fly burst chop */
 118         popts->burst_length = DDR_OTF;  /* on-the-fly BC4 and BL8 */
 119 #endif
 120 #else
 121         popts->burst_length = DDR_BL4;  /* has to be 4 for DDR2 */
 122 #endif
 123
 124         /* Choose ddr controller address mirror mode */
 125 #if defined(CONFIG_FSL_DDR3)
 126         popts->mirrored_dimm = pdimm[0].mirrored_dimm;
 127 #endif
 128
 129         /* Global Timing Parameters. */
 130         debug("mclk_ps = %u ps\n", get_memory_clk_period_ps());
 131
 132         /* Pick a caslat override. */
 133         popts->cas_latency_override = 0;
 134         popts->cas_latency_override_value = 3;
 135         if (popts->cas_latency_override) {
 136                 debug("using caslat override value = %u\n",
 137                        popts->cas_latency_override_value);
 138         }
 139
 140         /* Decide whether to use the computed derated latency */
 141         popts->use_derated_caslat = 0;
 142
 143         /* Choose an additive latency. */
 144         popts->additive_latency_override = 0;
 145         popts->additive_latency_override_value = 3;
 146         if (popts->additive_latency_override) {
 147                 debug("using additive latency override value = %u\n",
 148                        popts->additive_latency_override_value);
 149         }
 150
 151         /*
 152          * 2T_EN setting
 153          *
 154          * Factors to consider for 2T_EN:
 155          *      - number of DIMMs installed
 156          *      - number of components, number of active ranks
 157          *      - how much time you want to spend playing around
 158          */
 159         popts->twoT_en = 0;
 160         popts->threeT_en = 0;
 161
 162         /*
 163          * BSTTOPRE precharge interval
 164          *
 165          * Set this to 0 for global auto precharge
 166          *
 167          * FIXME: Should this be configured in picoseconds?
 168          * Why it should be in ps:  better understanding of this
 169          * relative to actual DRAM timing parameters such as tRAS.
 170          * e.g. tRAS(min) = 40 ns
 171          */
 172         popts->bstopre = 0x100;
 173
 174         /* Minimum CKE pulse width -- tCKE(MIN) */
 175         popts->tCKE_clock_pulse_width_ps
 176                 = mclk_to_picos(FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR);
 177
 178         /*
 179          * Window for four activates -- tFAW
 180          *
 181          * FIXME: UM: applies only to DDR2/DDR3 with eight logical banks only
 182          * FIXME: varies depending upon number of column addresses or data
 183          * FIXME: width, was considering looking at pdimm->primary_sdram_width
 184          */
 185 #if defined(CONFIG_FSL_DDR1)
 186         popts->tFAW_window_four_activates_ps = mclk_to_picos(1);
 187
 188 #elif defined(CONFIG_FSL_DDR2)
 189         /*
 190          * x4/x8;  some datasheets have 35000
 191          * x16 wide columns only?  Use 50000?
 192          */
 193         popts->tFAW_window_four_activates_ps = 37500;
 194
 195 #elif defined(CONFIG_FSL_DDR3)
 196         popts->tFAW_window_four_activates_ps = pdimm[0].tFAW_ps;
 197 #endif
 198         popts->zq_en = 0;
 199         popts->wrlvl_en = 0;
 200 #if defined(CONFIG_FSL_DDR3)
 201         /*
 202          * due to ddr3 dimm is fly-by topology
 203          * we suggest to enable write leveling to
 204          * meet the tQDSS under different loading.
 205          */
 206         popts->wrlvl_en = 1;
 207         popts->wrlvl_override = 0;
 208 #endif
 209
 210         /*
 211          * Check interleaving configuration from environment.
 212          * Please refer to doc/README.fsl-ddr for the detail.
 213          *
 214          * If memory controller interleaving is enabled, then the data
 215          * bus widths must be programmed identically for the 2 memory
 216          * controllers.
 217          *
 218          * XXX: Attempt to set both controllers to the same chip select
 219          * interleaving mode. It will do a best effort to get the
 220          * requested ranks interleaved together such that the result
 221          * should be a subset of the requested configuration.
 222          */
 223 #if (CONFIG_NUM_DDR_CONTROLLERS > 1)
 224         if (hwconfig_sub("fsl_ddr", "ctlr_intlv")) {
 225                 if (pdimm[0].n_ranks == 0) {
 226                         printf("There is no rank on CS0. Because only rank on "
 227                                 "CS0 and ranks chip-select interleaved with CS0"
 228                                 " are controller interleaved, force non memory "
 229                                 "controller interleaving\n");
 230                         popts->memctl_interleaving = 0;
 231                 } else {
 232                         popts->memctl_interleaving = 1;
 233                         /* test null first. if CONFIG_HWCONFIG is not defined
 234                          * hwconfig_arg_cmp returns non-zero */
 235                         if (hwconfig_subarg_cmp("fsl_ddr", "ctlr_intlv", "null")) {
 236                                 popts->memctl_interleaving = 0;
 237                                 debug("memory controller interleaving disabled.\n");
 238                         } else if (hwconfig_subarg_cmp("fsl_ddr", "ctlr_intlv", "cacheline"))
 239                                 popts->memctl_interleaving_mode =
 240                                         FSL_DDR_CACHE_LINE_INTERLEAVING;
 241                         else if (hwconfig_subarg_cmp("fsl_ddr", "ctlr_intlv", "page"))
 242                                 popts->memctl_interleaving_mode =
 243                                         FSL_DDR_PAGE_INTERLEAVING;
 244                         else if (hwconfig_subarg_cmp("fsl_ddr", "ctlr_intlv", "bank"))
 245                                 popts->memctl_interleaving_mode =
 246                                         FSL_DDR_BANK_INTERLEAVING;
 247                         else if (hwconfig_subarg_cmp("fsl_ddr", "ctlr_intlv", "superbank"))
 248                                 popts->memctl_interleaving_mode =
 249                                         FSL_DDR_SUPERBANK_INTERLEAVING;
 250                         else {
 251                                 popts->memctl_interleaving = 0;
 252                                 printf("hwconfig has unrecognized parameter for ctlr_intlv.\n");
 253                         }
 254                 }
 255         }
 256 #endif
 257
 258         if ((hwconfig_sub("fsl_ddr", "bank_intlv")) &&
 259                 (CONFIG_CHIP_SELECTS_PER_CTRL > 1)) {
 260                 /* test null first. if CONFIG_HWCONFIG is not defined,
 261                  * hwconfig_arg_cmp returns non-zero */
 262                 if (hwconfig_subarg_cmp("fsl_ddr", "bank_intlv", "null"))
 263                         printf("bank interleaving disabled.\n");
 264                 else if (hwconfig_subarg_cmp("fsl_ddr", "bank_intlv", "cs0_cs1"))
 265                         popts->ba_intlv_ctl = FSL_DDR_CS0_CS1;
 266                 else if (hwconfig_subarg_cmp("fsl_ddr", "bank_intlv", "cs2_cs3"))
 267                         popts->ba_intlv_ctl = FSL_DDR_CS2_CS3;
 268                 else if (hwconfig_subarg_cmp("fsl_ddr", "bank_intlv", "cs0_cs1_and_cs2_cs3"))
 269                         popts->ba_intlv_ctl = FSL_DDR_CS0_CS1_AND_CS2_CS3;
 270                 else if (hwconfig_subarg_cmp("fsl_ddr", "bank_intlv", "cs0_cs1_cs2_cs3"))
 271                         popts->ba_intlv_ctl = FSL_DDR_CS0_CS1_CS2_CS3;
 272                 else
 273                         printf("hwconfig has unrecognized parameter for ba_intlv_ctl.\n");
 274
 275                 switch (popts->ba_intlv_ctl & FSL_DDR_CS0_CS1_CS2_CS3) {
 276                 case FSL_DDR_CS0_CS1_CS2_CS3:
 277                 case FSL_DDR_CS0_CS1:
 278                         if (pdimm[0].n_ranks != 2) {
 279                                 popts->ba_intlv_ctl = 0;
 280                                 printf("Not enough bank(chip-select) for "
 281                                         "CS0+CS1, force non-interleaving!\n");
 282                         }
 283                         break;
 284                 case FSL_DDR_CS2_CS3:
 285                         if (pdimm[1].n_ranks !=2){
 286                                 popts->ba_intlv_ctl = 0;
 287                                 printf("Not enough bank(CS) for CS2+CS3, "
 288                                         "force non-interleaving!\n");
 289                         }
 290                         break;
 291                 case FSL_DDR_CS0_CS1_AND_CS2_CS3:
 292                         if ((pdimm[0].n_ranks != 2)||(pdimm[1].n_ranks != 2)) {
 293                                 popts->ba_intlv_ctl = 0;
 294                                 printf("Not enough bank(CS) for CS0+CS1 or "
 295                                         "CS2+CS3, force non-interleaving!\n");
 296                         }
 297                         break;
 298                 default:
 299                         popts->ba_intlv_ctl = 0;
 300                         break;
 301                 }
 302         }
 303
 304         fsl_ddr_board_options(popts, pdimm, ctrl_num);
 305
 306         return 0;
 307 }