2 * Copyright 2009-2010 Freescale Semiconductor, Inc.
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 #include <asm/fsl_law.h>
31 /* The cfg field is a bit mask in which each bit represents the value of
32 * cfg_IO_ports[] signal and the bit is set if the interface would be
33 * enabled based on the value of cfg_IO_ports[] signal
35 * On MPC86xx/PQ3 based systems:
36 * we extract cfg_IO_ports from GUTS register PORDEVSR
38 * cfg_IO_ports only exist on systems w/PCIe (we set cfg 0 for systems
42 #if defined(CONFIG_MPC8540) || defined(CONFIG_MPC8560)
43 static struct pci_info pci_config_info[] =
49 #elif defined(CONFIG_MPC8541) || defined(CONFIG_MPC8555)
50 static struct pci_info pci_config_info[] =
56 #elif defined(CONFIG_MPC8536)
57 static struct pci_info pci_config_info[] =
60 #elif defined(CONFIG_MPC8544)
61 static struct pci_info pci_config_info[] =
66 [LAW_TRGT_IF_PCIE_1] = {
67 .cfg = (1 << 2) | (1 << 3) | (1 << 4) | (1 << 5) |
70 [LAW_TRGT_IF_PCIE_2] = {
71 .cfg = (1 << 4) | (1 << 5) | (1 << 6) | (1 << 7),
73 [LAW_TRGT_IF_PCIE_3] = {
74 .cfg = (1 << 6) | (1 << 7),
77 #elif defined(CONFIG_MPC8548)
78 static struct pci_info pci_config_info[] =
80 [LAW_TRGT_IF_PCI_1] = {
83 [LAW_TRGT_IF_PCI_2] = {
86 /* PCI_2 is always host and we dont use iosel to determine enable/disable */
87 [LAW_TRGT_IF_PCIE_1] = {
88 .cfg = (1 << 3) | (1 << 4) | (1 << 7),
91 #elif defined(CONFIG_MPC8568)
92 static struct pci_info pci_config_info[] =
97 [LAW_TRGT_IF_PCIE_1] = {
98 .cfg = (1 << 3) | (1 << 4) | (1 << 7),
101 #elif defined(CONFIG_MPC8569)
102 static struct pci_info pci_config_info[] =
104 [LAW_TRGT_IF_PCIE_1] = {
105 .cfg = (1 << 0) | (1 << 4) | (1 << 5) | (1 << 6) | (1 << 7) |
106 (1 << 8) | (1 << 0xc) | (1 << 0xf),
109 #elif defined(CONFIG_MPC8572)
110 static struct pci_info pci_config_info[] =
112 [LAW_TRGT_IF_PCIE_1] = {
113 .cfg = (1 << 2) | (1 << 3) | (1 << 7) |
114 (1 << 0xb) | (1 << 0xc) | (1 << 0xf),
116 [LAW_TRGT_IF_PCIE_2] = {
117 .cfg = (1 << 3) | (1 << 7),
119 [LAW_TRGT_IF_PCIE_3] = {
123 #elif defined(CONFIG_MPC8610)
124 static struct pci_info pci_config_info[] =
126 [LAW_TRGT_IF_PCI_1] = {
129 [LAW_TRGT_IF_PCIE_1] = {
130 .cfg = (1 << 1) | (1 << 4),
132 [LAW_TRGT_IF_PCIE_2] = {
133 .cfg = (1 << 0) | (1 << 4),
136 #elif defined(CONFIG_MPC8641)
137 static struct pci_info pci_config_info[] =
139 [LAW_TRGT_IF_PCIE_1] = {
140 .cfg = (1 << 2) | (1 << 3) | (1 << 5) | (1 << 6) |
141 (1 << 7) | (1 << 0xe) | (1 << 0xf),
144 #elif defined(CONFIG_P1011) || defined(CONFIG_P1020) || \
145 defined(CONFIG_P1012) || defined(CONFIG_P1021)
146 static struct pci_info pci_config_info[] =
148 [LAW_TRGT_IF_PCIE_1] = {
149 .cfg = (1 << 0) | (1 << 6) | (1 << 0xe) | (1 << 0xf),
151 [LAW_TRGT_IF_PCIE_2] = {
155 #elif defined(CONFIG_P1013) || defined(CONFIG_P1022)
156 static struct pci_info pci_config_info[] =
158 [LAW_TRGT_IF_PCIE_1] = {
159 .cfg = (1 << 6) | (1 << 7) | (1 << 9) | (1 << 0xa) |
160 (1 << 0xb) | (1 << 0xd) | (1 << 0xe) |
161 (1 << 0xf) | (1 << 0x15) | (1 << 0x16) |
162 (1 << 0x17) | (1 << 0x18) | (1 << 0x19) |
163 (1 << 0x1a) | (1 << 0x1b) | (1 << 0x1c) |
164 (1 << 0x1d) | (1 << 0x1e) | (1 << 0x1f),
166 [LAW_TRGT_IF_PCIE_2] = {
167 .cfg = (1 << 1) | (1 << 6) | (1 << 7) | (1 << 9) |
168 (1 << 0xd) | (1 << 0x15) | (1 << 0x16) | (1 << 0x17) |
169 (1 << 0x18) | (1 << 0x19) | (1 << 0x1a) | (1 << 0x1b),
171 [LAW_TRGT_IF_PCIE_3] = {
172 .cfg = (1 << 0) | (1 << 1) | (1 << 6) | (1 << 7) | (1 << 9) |
173 (1 << 0xa) | (1 << 0xb) | (1 << 0xd) | (1 << 0x15) |
174 (1 << 0x16) | (1 << 0x17) | (1 << 0x18) | (1 << 0x1c),
177 #elif defined(CONFIG_P2010) || defined(CONFIG_P2020)
178 static struct pci_info pci_config_info[] =
180 [LAW_TRGT_IF_PCIE_1] = {
181 .cfg = (1 << 0) | (1 << 2) | (1 << 4) | (1 << 6) |
182 (1 << 0xd) | (1 << 0xe) | (1 << 0xf),
184 [LAW_TRGT_IF_PCIE_2] = {
185 .cfg = (1 << 2) | (1 << 0xe),
187 [LAW_TRGT_IF_PCIE_3] = {
188 .cfg = (1 << 2) | (1 << 4),
191 #elif defined(CONFIG_FSL_CORENET)
193 #error Need to define pci_config_info for processor
196 #ifndef CONFIG_FSL_CORENET
197 int is_fsl_pci_cfg(enum law_trgt_if trgt, u32 io_sel)
199 return ((1 << io_sel) & pci_config_info[trgt].cfg);