2 * Copyright 2011-2012 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
7 #ifndef _ASM_MPC85xx_CONFIG_H_
8 #define _ASM_MPC85xx_CONFIG_H_
10 /* SoC specific defines for Freescale MPC85xx (PQ3) and QorIQ processors */
12 #ifdef CONFIG_SYS_CCSRBAR_DEFAULT
13 #error "Do not define CONFIG_SYS_CCSRBAR_DEFAULT in the board header file."
17 * This macro should be removed when we no longer care about backwards
18 * compatibility with older operating systems.
20 #define CONFIG_PPC_SPINTABLE_COMPATIBLE
22 #define FSL_DDR_VER_4_7 47
23 #define FSL_DDR_VER_5_0 50
25 /* Number of TLB CAM entries we have on FSL Book-E chips */
26 #if defined(CONFIG_E500MC)
27 #define CONFIG_SYS_NUM_TLBCAMS 64
28 #elif defined(CONFIG_E500)
29 #define CONFIG_SYS_NUM_TLBCAMS 16
32 #if defined(CONFIG_MPC8536)
33 #define CONFIG_MAX_CPUS 1
34 #define CONFIG_SYS_FSL_NUM_LAWS 12
35 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 1
36 #define CONFIG_SYS_FSL_SEC_COMPAT 2
37 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
38 #define CONFIG_SYS_FSL_ERRATUM_A005125
40 #elif defined(CONFIG_MPC8540)
41 #define CONFIG_MAX_CPUS 1
42 #define CONFIG_SYS_FSL_NUM_LAWS 8
43 #define CONFIG_SYS_FSL_DDRC_GEN1
44 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
46 #elif defined(CONFIG_MPC8541)
47 #define CONFIG_MAX_CPUS 1
48 #define CONFIG_SYS_FSL_NUM_LAWS 8
49 #define CONFIG_SYS_FSL_DDRC_GEN1
50 #define CONFIG_SYS_FSL_SEC_COMPAT 2
51 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
53 #elif defined(CONFIG_MPC8544)
54 #define CONFIG_MAX_CPUS 1
55 #define CONFIG_SYS_FSL_NUM_LAWS 10
56 #define CONFIG_SYS_FSL_DDRC_GEN2
57 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 0
58 #define CONFIG_SYS_FSL_SEC_COMPAT 2
59 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
60 #define CONFIG_SYS_FSL_ERRATUM_A005125
62 #elif defined(CONFIG_MPC8548)
63 #define CONFIG_MAX_CPUS 1
64 #define CONFIG_SYS_FSL_NUM_LAWS 10
65 #define CONFIG_SYS_FSL_DDRC_GEN2
66 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 0
67 #define CONFIG_SYS_FSL_SEC_COMPAT 2
68 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
69 #define CONFIG_SYS_FSL_ERRATUM_NMG_DDR120
70 #define CONFIG_SYS_FSL_ERRATUM_NMG_LBC103
71 #define CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129
72 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1
73 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
74 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
75 #define CONFIG_SYS_FSL_RMU
76 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
77 #define CONFIG_SYS_FSL_ERRATUM_A005125
78 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
79 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x00
81 #elif defined(CONFIG_MPC8555)
82 #define CONFIG_MAX_CPUS 1
83 #define CONFIG_SYS_FSL_NUM_LAWS 8
84 #define CONFIG_SYS_FSL_DDRC_GEN1
85 #define CONFIG_SYS_FSL_SEC_COMPAT 2
86 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
88 #elif defined(CONFIG_MPC8560)
89 #define CONFIG_MAX_CPUS 1
90 #define CONFIG_SYS_FSL_NUM_LAWS 8
91 #define CONFIG_SYS_FSL_DDRC_GEN1
92 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
94 #elif defined(CONFIG_MPC8568)
95 #define CONFIG_MAX_CPUS 1
96 #define CONFIG_SYS_FSL_NUM_LAWS 10
97 #define CONFIG_SYS_FSL_DDRC_GEN2
98 #define CONFIG_SYS_FSL_SEC_COMPAT 2
99 #define QE_MURAM_SIZE 0x10000UL
100 #define MAX_QE_RISC 2
101 #define QE_NUM_OF_SNUM 28
102 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
103 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1
104 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
105 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
106 #define CONFIG_SYS_FSL_RMU
107 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
109 #elif defined(CONFIG_MPC8569)
110 #define CONFIG_MAX_CPUS 1
111 #define CONFIG_SYS_FSL_NUM_LAWS 10
112 #define CONFIG_SYS_FSL_SEC_COMPAT 2
113 #define QE_MURAM_SIZE 0x20000UL
114 #define MAX_QE_RISC 4
115 #define QE_NUM_OF_SNUM 46
116 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
117 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1
118 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
119 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
120 #define CONFIG_SYS_FSL_RMU
121 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
122 #define CONFIG_SYS_FSL_ERRATUM_A005125
124 #elif defined(CONFIG_MPC8572)
125 #define CONFIG_MAX_CPUS 2
126 #define CONFIG_SYS_FSL_NUM_LAWS 12
127 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
128 #define CONFIG_SYS_FSL_SEC_COMPAT 2
129 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
130 #define CONFIG_SYS_FSL_ERRATUM_DDR_115
131 #define CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134
132 #define CONFIG_SYS_FSL_ERRATUM_A005125
134 #elif defined(CONFIG_P1010)
135 #define CONFIG_MAX_CPUS 1
136 #define CONFIG_FSL_SDHC_V2_3
137 #define CONFIG_SYS_FSL_NUM_LAWS 12
138 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 3
139 #define CONFIG_TSECV2
140 #define CONFIG_SYS_FSL_SEC_COMPAT 4
141 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
142 #define CONFIG_NUM_DDR_CONTROLLERS 1
143 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
144 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 4
145 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
146 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
147 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
148 #define CONFIG_SYS_FSL_ERRATUM_IFC_A002769
149 #define CONFIG_SYS_FSL_ERRATUM_P1010_A003549
150 #define CONFIG_SYS_FSL_ERRATUM_SEC_A003571
151 #define CONFIG_SYS_FSL_ERRATUM_IFC_A003399
152 #define CONFIG_SYS_FSL_ERRATUM_A005125
153 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
154 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x10
156 /* P1011 is single core version of P1020 */
157 #elif defined(CONFIG_P1011)
158 #define CONFIG_MAX_CPUS 1
159 #define CONFIG_SYS_FSL_NUM_LAWS 12
160 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
161 #define CONFIG_TSECV2
162 #define CONFIG_FSL_PCIE_DISABLE_ASPM
163 #define CONFIG_SYS_FSL_SEC_COMPAT 2
164 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
165 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
166 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
167 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
168 #define CONFIG_SYS_FSL_ERRATUM_A005125
170 /* P1012 is single core version of P1021 */
171 #elif defined(CONFIG_P1012)
172 #define CONFIG_MAX_CPUS 1
173 #define CONFIG_SYS_FSL_NUM_LAWS 12
174 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
175 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
176 #define CONFIG_TSECV2
177 #define CONFIG_FSL_PCIE_DISABLE_ASPM
178 #define CONFIG_SYS_FSL_SEC_COMPAT 2
179 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
180 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
181 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
182 #define QE_MURAM_SIZE 0x6000UL
183 #define MAX_QE_RISC 1
184 #define QE_NUM_OF_SNUM 28
185 #define CONFIG_SYS_FSL_ERRATUM_A005125
187 /* P1013 is single core version of P1022 */
188 #elif defined(CONFIG_P1013)
189 #define CONFIG_MAX_CPUS 1
190 #define CONFIG_SYS_FSL_NUM_LAWS 12
191 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
192 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
193 #define CONFIG_TSECV2
194 #define CONFIG_SYS_FSL_SEC_COMPAT 2
195 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
196 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
197 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
198 #define CONFIG_FSL_SATA_ERRATUM_A001
199 #define CONFIG_SYS_FSL_ERRATUM_A005125
201 #elif defined(CONFIG_P1014)
202 #define CONFIG_MAX_CPUS 1
203 #define CONFIG_FSL_SDHC_V2_3
204 #define CONFIG_SYS_FSL_NUM_LAWS 12
205 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 3
206 #define CONFIG_TSECV2
207 #define CONFIG_SYS_FSL_SEC_COMPAT 4
208 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
209 #define CONFIG_NUM_DDR_CONTROLLERS 1
210 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
211 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
212 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
213 #define CONFIG_SYS_FSL_ERRATUM_IFC_A002769
214 #define CONFIG_SYS_FSL_ERRATUM_P1010_A003549
215 #define CONFIG_SYS_FSL_ERRATUM_IFC_A003399
217 /* P1017 is single core version of P1023 */
218 #elif defined(CONFIG_P1017)
219 #define CONFIG_MAX_CPUS 1
220 #define CONFIG_SYS_FSL_NUM_LAWS 12
221 #define CONFIG_SYS_FSL_SEC_COMPAT 4
222 #define CONFIG_SYS_NUM_FMAN 1
223 #define CONFIG_SYS_NUM_FM1_DTSEC 2
224 #define CONFIG_NUM_DDR_CONTROLLERS 1
225 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
226 #define CONFIG_SYS_QMAN_NUM_PORTALS 3
227 #define CONFIG_SYS_BMAN_NUM_PORTALS 3
228 #define CONFIG_SYS_FM_MURAM_SIZE 0x10000
229 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
230 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff600000
231 #define CONFIG_SYS_FSL_ERRATUM_A005125
233 #elif defined(CONFIG_P1020)
234 #define CONFIG_MAX_CPUS 2
235 #define CONFIG_SYS_FSL_NUM_LAWS 12
236 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
237 #define CONFIG_TSECV2
238 #define CONFIG_FSL_PCIE_DISABLE_ASPM
239 #define CONFIG_SYS_FSL_SEC_COMPAT 2
240 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
241 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
242 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
243 #define CONFIG_SYS_FSL_ERRATUM_A005125
244 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
246 #elif defined(CONFIG_P1021)
247 #define CONFIG_MAX_CPUS 2
248 #define CONFIG_SYS_FSL_NUM_LAWS 12
249 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
250 #define CONFIG_TSECV2
251 #define CONFIG_FSL_PCIE_DISABLE_ASPM
252 #define CONFIG_SYS_FSL_SEC_COMPAT 2
253 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
254 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
255 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
256 #define QE_MURAM_SIZE 0x6000UL
257 #define MAX_QE_RISC 1
258 #define QE_NUM_OF_SNUM 28
259 #define CONFIG_SYS_FSL_ERRATUM_A005125
260 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
262 #elif defined(CONFIG_P1022)
263 #define CONFIG_MAX_CPUS 2
264 #define CONFIG_SYS_FSL_NUM_LAWS 12
265 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
266 #define CONFIG_TSECV2
267 #define CONFIG_SYS_FSL_SEC_COMPAT 2
268 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
269 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
270 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
271 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
272 #define CONFIG_FSL_SATA_ERRATUM_A001
273 #define CONFIG_SYS_FSL_ERRATUM_A005125
275 #elif defined(CONFIG_P1023)
276 #define CONFIG_MAX_CPUS 2
277 #define CONFIG_SYS_FSL_NUM_LAWS 12
278 #define CONFIG_SYS_FSL_SEC_COMPAT 4
279 #define CONFIG_SYS_NUM_FMAN 1
280 #define CONFIG_SYS_NUM_FM1_DTSEC 2
281 #define CONFIG_NUM_DDR_CONTROLLERS 1
282 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
283 #define CONFIG_SYS_QMAN_NUM_PORTALS 3
284 #define CONFIG_SYS_BMAN_NUM_PORTALS 3
285 #define CONFIG_SYS_FM_MURAM_SIZE 0x10000
286 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
287 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff600000
288 #define CONFIG_SYS_FSL_ERRATUM_A005125
289 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
290 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x11
292 /* P1024 is lower end variant of P1020 */
293 #elif defined(CONFIG_P1024)
294 #define CONFIG_MAX_CPUS 2
295 #define CONFIG_SYS_FSL_NUM_LAWS 12
296 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
297 #define CONFIG_TSECV2
298 #define CONFIG_FSL_PCIE_DISABLE_ASPM
299 #define CONFIG_SYS_FSL_SEC_COMPAT 2
300 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
301 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
302 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
303 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
304 #define CONFIG_SYS_FSL_ERRATUM_A005125
306 /* P1025 is lower end variant of P1021 */
307 #elif defined(CONFIG_P1025)
308 #define CONFIG_MAX_CPUS 2
309 #define CONFIG_SYS_FSL_NUM_LAWS 12
310 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
311 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
312 #define CONFIG_TSECV2
313 #define CONFIG_FSL_PCIE_DISABLE_ASPM
314 #define CONFIG_SYS_FSL_SEC_COMPAT 2
315 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
316 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
317 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
318 #define QE_MURAM_SIZE 0x6000UL
319 #define MAX_QE_RISC 1
320 #define QE_NUM_OF_SNUM 28
321 #define CONFIG_SYS_FSL_ERRATUM_A005125
323 /* P2010 is single core version of P2020 */
324 #elif defined(CONFIG_P2010)
325 #define CONFIG_MAX_CPUS 1
326 #define CONFIG_SYS_FSL_NUM_LAWS 12
327 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
328 #define CONFIG_SYS_FSL_SEC_COMPAT 2
329 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
330 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
331 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
332 #define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001
333 #define CONFIG_SYS_FSL_ERRATUM_A005125
335 #elif defined(CONFIG_P2020)
336 #define CONFIG_MAX_CPUS 2
337 #define CONFIG_SYS_FSL_NUM_LAWS 12
338 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
339 #define CONFIG_SYS_FSL_SEC_COMPAT 2
340 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
341 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
342 #define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001
343 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
344 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
345 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
346 #define CONFIG_SYS_FSL_RMU
347 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
348 #define CONFIG_SYS_FSL_ERRATUM_A005125
349 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
350 #elif defined(CONFIG_PPC_P2041) /* also supports P2040 */
351 #define CONFIG_SYS_FSL_QORIQ_CHASSIS1
352 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
353 #define CONFIG_MAX_CPUS 4
354 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2
355 #define CONFIG_SYS_FSL_NUM_LAWS 32
356 #define CONFIG_SYS_FSL_SEC_COMPAT 4
357 #define CONFIG_SYS_NUM_FMAN 1
358 #define CONFIG_SYS_NUM_FM1_DTSEC 5
359 #define CONFIG_SYS_NUM_FM1_10GEC 1
360 #define CONFIG_NUM_DDR_CONTROLLERS 1
361 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
362 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000
363 #define CONFIG_SYS_FSL_TBCLK_DIV 32
364 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
365 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
366 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
367 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE
368 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
369 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
370 #define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011
371 #define CONFIG_SYS_FSL_ERRATUM_USB14
372 #define CONFIG_SYS_FSL_ERRATUM_CPU_A003999
373 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003
374 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
375 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
376 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
377 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
378 #define CONFIG_SYS_FSL_ERRATUM_A004510
379 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10
380 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2 0x11
381 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
382 #define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
383 #define CONFIG_SYS_FSL_ERRATUM_A004849
384 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
385 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x11
387 #elif defined(CONFIG_PPC_P3041)
388 #define CONFIG_SYS_FSL_QORIQ_CHASSIS1
389 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
390 #define CONFIG_MAX_CPUS 4
391 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2
392 #define CONFIG_SYS_FSL_NUM_LAWS 32
393 #define CONFIG_SYS_FSL_SEC_COMPAT 4
394 #define CONFIG_SYS_NUM_FMAN 1
395 #define CONFIG_SYS_NUM_FM1_DTSEC 5
396 #define CONFIG_SYS_NUM_FM1_10GEC 1
397 #define CONFIG_NUM_DDR_CONTROLLERS 1
398 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000
399 #define CONFIG_SYS_FSL_TBCLK_DIV 32
400 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
401 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
402 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
403 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE
404 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
405 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
406 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
407 #define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011
408 #define CONFIG_SYS_FSL_ERRATUM_USB14
409 #define CONFIG_SYS_FSL_ERRATUM_CPU_A003999
410 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003
411 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
412 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
413 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
414 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
415 #define CONFIG_SYS_FSL_ERRATUM_A004510
416 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10
417 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2 0x11
418 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
419 #define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
420 #define CONFIG_SYS_FSL_ERRATUM_A004849
421 #define CONFIG_SYS_FSL_ERRATUM_A005812
422 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
423 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x20
425 #elif defined(CONFIG_PPC_P4080) /* also supports P4040 */
426 #define CONFIG_SYS_FSL_QORIQ_CHASSIS1
427 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
428 #define CONFIG_MAX_CPUS 8
429 #define CONFIG_SYS_FSL_NUM_CC_PLLS 4
430 #define CONFIG_SYS_FSL_NUM_LAWS 32
431 #define CONFIG_SYS_FSL_SEC_COMPAT 4
432 #define CONFIG_SYS_NUM_FMAN 2
433 #define CONFIG_SYS_NUM_FM1_DTSEC 4
434 #define CONFIG_SYS_NUM_FM2_DTSEC 4
435 #define CONFIG_SYS_NUM_FM1_10GEC 1
436 #define CONFIG_SYS_NUM_FM2_10GEC 1
437 #define CONFIG_NUM_DDR_CONTROLLERS 2
438 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
439 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000
440 #define CONFIG_SYS_FSL_TBCLK_DIV 16
441 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,p4080-pcie"
442 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
443 #define CONFIG_SYS_FSL_ERRATUM_CPC_A002
444 #define CONFIG_SYS_FSL_ERRATUM_CPC_A003
445 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003
446 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
447 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
448 #define CONFIG_SYS_FSL_ERRATUM_ESDHC135
449 #define CONFIG_SYS_FSL_ERRATUM_ESDHC13
450 #define CONFIG_SYS_P4080_ERRATUM_CPU22
451 #define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011
452 #define CONFIG_SYS_P4080_ERRATUM_SERDES8
453 #define CONFIG_SYS_P4080_ERRATUM_SERDES9
454 #define CONFIG_SYS_P4080_ERRATUM_SERDES_A001
455 #define CONFIG_SYS_P4080_ERRATUM_SERDES_A005
456 #define CONFIG_SYS_FSL_ERRATUM_CPU_A003999
457 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
458 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
459 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
460 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
461 #define CONFIG_SYS_FSL_RMU
462 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
463 #define CONFIG_SYS_FSL_ERRATUM_A004510
464 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x20
465 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xff000000
466 #define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
467 #define CONFIG_SYS_FSL_ERRATUM_A004849
468 #define CONFIG_SYS_FSL_ERRATUM_A004580
469 #define CONFIG_SYS_P4080_ERRATUM_PCIE_A003
470 #define CONFIG_SYS_FSL_ERRATUM_A005812
471 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
472 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x20
474 #elif defined(CONFIG_PPC_P5020) /* also supports P5010 */
475 #define CONFIG_SYS_PPC64 /* 64-bit core */
476 #define CONFIG_SYS_FSL_QORIQ_CHASSIS1
477 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
478 #define CONFIG_MAX_CPUS 2
479 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2
480 #define CONFIG_SYS_FSL_NUM_LAWS 32
481 #define CONFIG_SYS_FSL_SEC_COMPAT 4
482 #define CONFIG_SYS_NUM_FMAN 1
483 #define CONFIG_SYS_NUM_FM1_DTSEC 5
484 #define CONFIG_SYS_NUM_FM1_10GEC 1
485 #define CONFIG_NUM_DDR_CONTROLLERS 2
486 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
487 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000
488 #define CONFIG_SYS_FSL_TBCLK_DIV 32
489 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
490 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
491 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
492 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE
493 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
494 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
495 #define CONFIG_SYS_FSL_ERRATUM_USB14
496 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003
497 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
498 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
499 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
500 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
501 #define CONFIG_SYS_FSL_ERRATUM_A004510
502 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10
503 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xc0000000
504 #define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
505 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
506 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x20
508 #elif defined(CONFIG_PPC_P5040)
509 #define CONFIG_SYS_PPC64
510 #define CONFIG_SYS_FSL_QORIQ_CHASSIS1
511 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
512 #define CONFIG_MAX_CPUS 4
513 #define CONFIG_SYS_FSL_NUM_CC_PLLS 3
514 #define CONFIG_SYS_FSL_NUM_LAWS 32
515 #define CONFIG_SYS_FSL_SEC_COMPAT 4
516 #define CONFIG_SYS_NUM_FMAN 2
517 #define CONFIG_SYS_NUM_FM1_DTSEC 5
518 #define CONFIG_SYS_NUM_FM1_10GEC 1
519 #define CONFIG_SYS_NUM_FM2_DTSEC 5
520 #define CONFIG_SYS_NUM_FM2_10GEC 1
521 #define CONFIG_NUM_DDR_CONTROLLERS 2
522 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
523 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000
524 #define CONFIG_SYS_FSL_TBCLK_DIV 16
525 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4"
526 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
527 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
528 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE
529 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
530 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
531 #define CONFIG_SYS_FSL_ERRATUM_USB14
532 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003
533 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
534 #define CONFIG_SYS_FSL_ERRATUM_A004699
535 #define CONFIG_SYS_FSL_ERRATUM_A004510
536 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10
537 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
538 #define CONFIG_SYS_FSL_ERRATUM_A005812
540 #elif defined(CONFIG_BSC9131)
541 #define CONFIG_MAX_CPUS 1
542 #define CONFIG_FSL_SDHC_V2_3
543 #define CONFIG_SYS_FSL_NUM_LAWS 12
544 #define CONFIG_TSECV2
545 #define CONFIG_SYS_FSL_SEC_COMPAT 4
546 #define CONFIG_NUM_DDR_CONTROLLERS 1
547 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
548 #define CONFIG_SYS_FSL_DSP_M2_RAM_ADDR 0xb0000000
549 #define CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT 0xff600000
550 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 3
551 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
552 #define CONFIG_NAND_FSL_IFC
553 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
554 #define CONFIG_SYS_FSL_ERRATUM_A005125
556 #elif defined(CONFIG_BSC9132)
557 #define CONFIG_MAX_CPUS 2
558 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 3
559 #define CONFIG_FSL_SDHC_V2_3
560 #define CONFIG_SYS_FSL_NUM_LAWS 12
561 #define CONFIG_TSECV2
562 #define CONFIG_SYS_FSL_SEC_COMPAT 4
563 #define CONFIG_NUM_DDR_CONTROLLERS 2
564 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
565 #define CONFIG_SYS_FSL_DSP_DDR_ADDR 0x40000000
566 #define CONFIG_SYS_FSL_DSP_M2_RAM_ADDR 0xb0000000
567 #define CONFIG_SYS_FSL_DSP_M3_RAM_ADDR 0xc0000000
568 #define CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT 0xff600000
569 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 3
570 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
571 #define CONFIG_NAND_FSL_IFC
572 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
573 #define CONFIG_SYS_FSL_ESDHC_P1010_BROKEN_SDCLK
574 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
575 #define CONFIG_SYS_FSL_ERRATUM_A005125
576 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
577 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x11
579 #elif defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160)
581 #define CONFIG_SYS_PPC64 /* 64-bit core */
582 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
583 #define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */
584 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4
585 #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */
586 #ifdef CONFIG_PPC_T4240
587 #define CONFIG_MAX_CPUS 12
588 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 4 }
589 #define CONFIG_SYS_NUM_FM1_DTSEC 8
590 #define CONFIG_SYS_NUM_FM1_10GEC 2
591 #define CONFIG_SYS_NUM_FM2_DTSEC 8
592 #define CONFIG_SYS_NUM_FM2_10GEC 2
593 #define CONFIG_NUM_DDR_CONTROLLERS 3
595 #define CONFIG_MAX_CPUS 8
596 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1 }
597 #define CONFIG_SYS_NUM_FM1_DTSEC 7
598 #define CONFIG_SYS_NUM_FM1_10GEC 1
599 #define CONFIG_SYS_NUM_FM2_DTSEC 7
600 #define CONFIG_SYS_NUM_FM2_10GEC 1
601 #define CONFIG_NUM_DDR_CONTROLLERS 2
603 #define CONFIG_SYS_FSL_NUM_CC_PLLS 5
604 #define CONFIG_SYS_FSL_NUM_LAWS 32
605 #define CONFIG_SYS_FSL_SRDS_1
606 #define CONFIG_SYS_FSL_SRDS_2
607 #define CONFIG_SYS_FSL_SRDS_3
608 #define CONFIG_SYS_FSL_SRDS_4
609 #define CONFIG_SYS_FSL_SEC_COMPAT 4
610 #define CONFIG_SYS_NUM_FMAN 2
611 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
612 #define CONFIG_SYS_PME_CLK 0
613 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7
614 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
615 #define CONFIG_SYS_FMAN_V3
616 #define CONFIG_SYS_FM1_CLK 3
617 #define CONFIG_SYS_FM2_CLK 3
618 #define CONFIG_SYS_FM_MURAM_SIZE 0x60000
619 #define CONFIG_SYS_FSL_TBCLK_DIV 16
620 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v3.0"
621 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
622 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
623 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
624 #define CONFIG_SYS_FSL_SRIO_LIODN
625 #define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
626 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
627 #define CONFIG_SYS_FSL_ERRATUM_A004468
628 #define CONFIG_SYS_FSL_ERRATUM_A_004934
629 #define CONFIG_SYS_FSL_ERRATUM_A005871
630 #define CONFIG_SYS_FSL_ERRATUM_A006379
631 #define CONFIG_SYS_FSL_ERRATUM_A006593
632 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
633 #define CONFIG_SYS_FSL_PCI_VER_3_X
635 #elif defined(CONFIG_PPC_B4860) || defined(CONFIG_PPC_B4420)
637 #define CONFIG_SYS_PPC64 /* 64-bit core */
638 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
639 #define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */
640 #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */
641 #define CONFIG_SYS_FSL_NUM_LAWS 32
642 #define CONFIG_SYS_FSL_SRDS_1
643 #define CONFIG_SYS_FSL_SRDS_2
644 #define CONFIG_SYS_FSL_SEC_COMPAT 4
645 #define CONFIG_SYS_NUM_FMAN 1
646 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
647 #define CONFIG_SYS_FM1_CLK 0
648 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7
649 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 4
650 #define CONFIG_SYS_FMAN_V3
651 #define CONFIG_SYS_FM_MURAM_SIZE 0x60000
652 #define CONFIG_SYS_FSL_TBCLK_DIV 16
653 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4"
654 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
655 #define CONFIG_SYS_FSL_ERRATUM_A_004934
656 #define CONFIG_SYS_FSL_ERRATUM_A005871
657 #define CONFIG_SYS_FSL_ERRATUM_A006379
658 #define CONFIG_SYS_FSL_ERRATUM_A006593
659 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
661 #ifdef CONFIG_PPC_B4860
662 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4
663 #define CONFIG_MAX_CPUS 4
664 #define CONFIG_SYS_FSL_NUM_CC_PLLS 4
665 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4, 4, 4 }
666 #define CONFIG_SYS_NUM_FM1_DTSEC 6
667 #define CONFIG_SYS_NUM_FM1_10GEC 2
668 #define CONFIG_NUM_DDR_CONTROLLERS 2
669 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
670 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
671 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
672 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
673 #define CONFIG_SYS_FSL_SRIO_LIODN
675 #define CONFIG_MAX_CPUS 2
676 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 2
677 #define CONFIG_SYS_FSL_NUM_CC_PLLS 4
678 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4 }
679 #define CONFIG_SYS_NUM_FM1_DTSEC 4
680 #define CONFIG_SYS_NUM_FM1_10GEC 0
681 #define CONFIG_NUM_DDR_CONTROLLERS 1
684 #elif defined(CONFIG_PPC_T1040) || defined(CONFIG_PPC_T1042) ||\
685 defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022)
687 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
688 #define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */
689 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 1
690 #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */
691 #if defined(CONFIG_PPC_T1040) || defined(CONFIG_PPC_T1042)
692 #define CONFIG_MAX_CPUS 4
693 #elif defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022)
694 #define CONFIG_MAX_CPUS 2
696 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2
697 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 1, 1 }
698 #define CONFIG_SYS_SDHC_CLOCK 0
699 #define CONFIG_SYS_FSL_NUM_LAWS 16
700 #define CONFIG_SYS_FSL_SRDS_1
701 #define CONFIG_SYS_FSL_SEC_COMPAT 5
702 #define CONFIG_SYS_NUM_FMAN 1
703 #define CONFIG_SYS_NUM_FM1_DTSEC 5
704 #define CONFIG_NUM_DDR_CONTROLLERS 1
705 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
706 #define CONFIG_PME_PLAT_CLK_DIV 2
707 #define CONFIG_SYS_PME_CLK CONFIG_PME_PLAT_CLK_DIV
708 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_5_0
709 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
710 #define CONFIG_SYS_FMAN_V3
711 #define CONFIG_FM_PLAT_CLK_DIV 1
712 #define CONFIG_SYS_FM1_CLK CONFIG_FM_PLAT_CLK_DIV
713 #define CONFIG_SYS_FM_MURAM_SIZE 0x30000
714 #define CONFIG_SYS_FSL_TBCLK_DIV 32
715 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4"
716 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
717 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE
718 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
719 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
721 #elif defined(CONFIG_PPC_T2080) || defined(CONFIG_PPC_T2081)
723 #define CONFIG_SYS_PPC64 /* 64-bit core */
724 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
725 #define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */
726 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4
727 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2
728 #define CONFIG_SYS_FSL_QMAN_V3
729 #define CONFIG_MAX_CPUS 4
730 #define CONFIG_SYS_FSL_NUM_LAWS 32
731 #define CONFIG_SYS_FSL_SEC_COMPAT 4
732 #define CONFIG_SYS_NUM_FMAN 1
733 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4, 4, 4 }
734 #define CONFIG_SYS_FSL_SRDS_1
735 #define CONFIG_SYS_FSL_PCI_VER_3_X
736 #if defined(CONFIG_PPC_T2080)
737 #define CONFIG_SYS_NUM_FM1_DTSEC 8
738 #define CONFIG_SYS_NUM_FM1_10GEC 4
739 #define CONFIG_SYS_FSL_SRDS_2
740 #define CONFIG_SYS_FSL_SRIO_LIODN
741 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
742 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
743 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
744 #elif defined(CONFIG_PPC_T2081)
745 #define CONFIG_SYS_NUM_FM1_DTSEC 6
746 #define CONFIG_SYS_NUM_FM1_10GEC 2
748 #define CONFIG_SYS_FSL_NUM_USB_CTRLS 2
749 #define CONFIG_NUM_DDR_CONTROLLERS 1
750 #define CONFIG_PME_PLAT_CLK_DIV 1
751 #define CONFIG_SYS_PME_CLK CONFIG_PME_PLAT_CLK_DIV
752 #define CONFIG_SYS_FM1_CLK 0
753 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7
754 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
755 #define CONFIG_SYS_FMAN_V3
756 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000
757 #define CONFIG_SYS_FSL_TBCLK_DIV 16
758 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v3.0"
759 #define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
760 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
761 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
762 #define CONFIG_SYS_FSL_SFP_VER_3_0
763 #define CONFIG_SYS_FSL_ISBC_VER 2
765 #elif defined(CONFIG_PPC_C29X)
766 #define CONFIG_MAX_CPUS 1
767 #define CONFIG_FSL_SDHC_V2_3
768 #define CONFIG_SYS_FSL_NUM_LAWS 12
769 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 3
770 #define CONFIG_TSECV2_1
771 #define CONFIG_SYS_FSL_SEC_COMPAT 6
772 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
773 #define CONFIG_NUM_DDR_CONTROLLERS 1
774 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
775 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
776 #define CONFIG_SYS_FSL_ERRATUM_A005125
779 #error Processor type not defined for this platform
782 #ifndef CONFIG_SYS_CCSRBAR_DEFAULT
783 #error "CONFIG_SYS_CCSRBAR_DEFAULT is not defined for this platform."
787 #define CONFIG_SYS_FSL_THREADS_PER_CORE 2
789 #define CONFIG_SYS_FSL_THREADS_PER_CORE 1
792 #if !defined(CONFIG_SYS_FSL_DDRC_GEN1) && \
793 !defined(CONFIG_SYS_FSL_DDRC_GEN2) && \
794 !defined(CONFIG_SYS_FSL_DDRC_GEN3)
795 #define CONFIG_SYS_FSL_DDRC_GEN3
798 #endif /* _ASM_MPC85xx_CONFIG_H_ */