2 * Copyright 2011-2012 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
7 #ifndef _ASM_MPC85xx_CONFIG_H_
8 #define _ASM_MPC85xx_CONFIG_H_
10 /* SoC specific defines for Freescale MPC85xx (PQ3) and QorIQ processors */
12 #ifdef CONFIG_SYS_CCSRBAR_DEFAULT
13 #error "Do not define CONFIG_SYS_CCSRBAR_DEFAULT in the board header file."
17 * This macro should be removed when we no longer care about backwards
18 * compatibility with older operating systems.
20 #define CONFIG_PPC_SPINTABLE_COMPATIBLE
22 #include <fsl_ddrc_version.h>
23 #define CONFIG_SYS_FSL_DDR_BE
26 #define CONFIG_SYS_FSL_IFC_BE
28 /* Number of TLB CAM entries we have on FSL Book-E chips */
29 #if defined(CONFIG_E500MC)
30 #define CONFIG_SYS_NUM_TLBCAMS 64
31 #elif defined(CONFIG_E500)
32 #define CONFIG_SYS_NUM_TLBCAMS 16
35 #if defined(CONFIG_MPC8536)
36 #define CONFIG_MAX_CPUS 1
37 #define CONFIG_SYS_FSL_NUM_LAWS 12
38 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 1
39 #define CONFIG_SYS_FSL_SEC_COMPAT 2
40 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
41 #define CONFIG_SYS_FSL_ERRATUM_A005125
43 #elif defined(CONFIG_MPC8540)
44 #define CONFIG_MAX_CPUS 1
45 #define CONFIG_SYS_FSL_NUM_LAWS 8
46 #define CONFIG_SYS_FSL_DDRC_GEN1
47 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
49 #elif defined(CONFIG_MPC8541)
50 #define CONFIG_MAX_CPUS 1
51 #define CONFIG_SYS_FSL_NUM_LAWS 8
52 #define CONFIG_SYS_FSL_DDRC_GEN1
53 #define CONFIG_SYS_FSL_SEC_COMPAT 2
54 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
56 #elif defined(CONFIG_MPC8544)
57 #define CONFIG_MAX_CPUS 1
58 #define CONFIG_SYS_FSL_NUM_LAWS 10
59 #define CONFIG_SYS_FSL_DDRC_GEN2
60 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 0
61 #define CONFIG_SYS_FSL_SEC_COMPAT 2
62 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
63 #define CONFIG_SYS_FSL_ERRATUM_A005125
65 #elif defined(CONFIG_MPC8548)
66 #define CONFIG_MAX_CPUS 1
67 #define CONFIG_SYS_FSL_NUM_LAWS 10
68 #define CONFIG_SYS_FSL_DDRC_GEN2
69 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 0
70 #define CONFIG_SYS_FSL_SEC_COMPAT 2
71 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
72 #define CONFIG_SYS_FSL_ERRATUM_NMG_DDR120
73 #define CONFIG_SYS_FSL_ERRATUM_NMG_LBC103
74 #define CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129
75 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1
76 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
77 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
78 #define CONFIG_SYS_FSL_RMU
79 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
80 #define CONFIG_SYS_FSL_ERRATUM_A005125
81 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
82 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x00
84 #elif defined(CONFIG_MPC8555)
85 #define CONFIG_MAX_CPUS 1
86 #define CONFIG_SYS_FSL_NUM_LAWS 8
87 #define CONFIG_SYS_FSL_DDRC_GEN1
88 #define CONFIG_SYS_FSL_SEC_COMPAT 2
89 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
91 #elif defined(CONFIG_MPC8560)
92 #define CONFIG_MAX_CPUS 1
93 #define CONFIG_SYS_FSL_NUM_LAWS 8
94 #define CONFIG_SYS_FSL_DDRC_GEN1
95 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
97 #elif defined(CONFIG_MPC8568)
98 #define CONFIG_MAX_CPUS 1
99 #define CONFIG_SYS_FSL_NUM_LAWS 10
100 #define CONFIG_SYS_FSL_DDRC_GEN2
101 #define CONFIG_SYS_FSL_SEC_COMPAT 2
102 #define QE_MURAM_SIZE 0x10000UL
103 #define MAX_QE_RISC 2
104 #define QE_NUM_OF_SNUM 28
105 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
106 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1
107 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
108 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
109 #define CONFIG_SYS_FSL_RMU
110 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
112 #elif defined(CONFIG_MPC8569)
113 #define CONFIG_MAX_CPUS 1
114 #define CONFIG_SYS_FSL_NUM_LAWS 10
115 #define CONFIG_SYS_FSL_SEC_COMPAT 2
116 #define QE_MURAM_SIZE 0x20000UL
117 #define MAX_QE_RISC 4
118 #define QE_NUM_OF_SNUM 46
119 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
120 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1
121 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
122 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
123 #define CONFIG_SYS_FSL_RMU
124 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
125 #define CONFIG_SYS_FSL_ERRATUM_A005125
127 #elif defined(CONFIG_MPC8572)
128 #define CONFIG_MAX_CPUS 2
129 #define CONFIG_SYS_FSL_NUM_LAWS 12
130 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
131 #define CONFIG_SYS_FSL_SEC_COMPAT 2
132 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
133 #define CONFIG_SYS_FSL_ERRATUM_DDR_115
134 #define CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134
135 #define CONFIG_SYS_FSL_ERRATUM_A005125
137 #elif defined(CONFIG_P1010)
138 #define CONFIG_MAX_CPUS 1
139 #define CONFIG_FSL_SDHC_V2_3
140 #define CONFIG_SYS_FSL_NUM_LAWS 12
141 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 3
142 #define CONFIG_TSECV2
143 #define CONFIG_SYS_FSL_SEC_COMPAT 4
144 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
145 #define CONFIG_NUM_DDR_CONTROLLERS 1
146 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
147 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 4
148 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
149 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
150 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
151 #define CONFIG_SYS_FSL_ERRATUM_IFC_A002769
152 #define CONFIG_SYS_FSL_ERRATUM_P1010_A003549
153 #define CONFIG_SYS_FSL_ERRATUM_SEC_A003571
154 #define CONFIG_SYS_FSL_ERRATUM_IFC_A003399
155 #define CONFIG_SYS_FSL_ERRATUM_A005125
156 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
157 #define CONFIG_SYS_FSL_ERRATUM_A007075
158 #define CONFIG_SYS_FSL_ERRATUM_A006261
159 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x10
160 #define CONFIG_ESDHC_HC_BLK_ADDR
162 /* P1011 is single core version of P1020 */
163 #elif defined(CONFIG_P1011)
164 #define CONFIG_MAX_CPUS 1
165 #define CONFIG_SYS_FSL_NUM_LAWS 12
166 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
167 #define CONFIG_TSECV2
168 #define CONFIG_FSL_PCIE_DISABLE_ASPM
169 #define CONFIG_SYS_FSL_SEC_COMPAT 2
170 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
171 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
172 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
173 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
174 #define CONFIG_SYS_FSL_ERRATUM_A005125
176 /* P1012 is single core version of P1021 */
177 #elif defined(CONFIG_P1012)
178 #define CONFIG_MAX_CPUS 1
179 #define CONFIG_SYS_FSL_NUM_LAWS 12
180 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
181 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
182 #define CONFIG_TSECV2
183 #define CONFIG_FSL_PCIE_DISABLE_ASPM
184 #define CONFIG_SYS_FSL_SEC_COMPAT 2
185 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
186 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
187 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
188 #define QE_MURAM_SIZE 0x6000UL
189 #define MAX_QE_RISC 1
190 #define QE_NUM_OF_SNUM 28
191 #define CONFIG_SYS_FSL_ERRATUM_A005125
193 /* P1013 is single core version of P1022 */
194 #elif defined(CONFIG_P1013)
195 #define CONFIG_MAX_CPUS 1
196 #define CONFIG_SYS_FSL_NUM_LAWS 12
197 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
198 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
199 #define CONFIG_TSECV2
200 #define CONFIG_SYS_FSL_SEC_COMPAT 2
201 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
202 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
203 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
204 #define CONFIG_FSL_SATA_ERRATUM_A001
205 #define CONFIG_SYS_FSL_ERRATUM_A005125
207 #elif defined(CONFIG_P1014)
208 #define CONFIG_MAX_CPUS 1
209 #define CONFIG_FSL_SDHC_V2_3
210 #define CONFIG_SYS_FSL_NUM_LAWS 12
211 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 3
212 #define CONFIG_TSECV2
213 #define CONFIG_SYS_FSL_SEC_COMPAT 4
214 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
215 #define CONFIG_NUM_DDR_CONTROLLERS 1
216 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
217 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
218 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
219 #define CONFIG_SYS_FSL_ERRATUM_IFC_A002769
220 #define CONFIG_SYS_FSL_ERRATUM_P1010_A003549
221 #define CONFIG_SYS_FSL_ERRATUM_IFC_A003399
223 /* P1017 is single core version of P1023 */
224 #elif defined(CONFIG_P1017)
225 #define CONFIG_MAX_CPUS 1
226 #define CONFIG_SYS_FSL_NUM_LAWS 12
227 #define CONFIG_SYS_FSL_SEC_COMPAT 4
228 #define CONFIG_SYS_NUM_FMAN 1
229 #define CONFIG_SYS_NUM_FM1_DTSEC 2
230 #define CONFIG_NUM_DDR_CONTROLLERS 1
231 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
232 #define CONFIG_SYS_QMAN_NUM_PORTALS 3
233 #define CONFIG_SYS_BMAN_NUM_PORTALS 3
234 #define CONFIG_SYS_FM_MURAM_SIZE 0x10000
235 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
236 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff600000
237 #define CONFIG_SYS_FSL_ERRATUM_A005125
239 #elif defined(CONFIG_P1020)
240 #define CONFIG_MAX_CPUS 2
241 #define CONFIG_SYS_FSL_NUM_LAWS 12
242 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
243 #define CONFIG_TSECV2
244 #define CONFIG_FSL_PCIE_DISABLE_ASPM
245 #define CONFIG_SYS_FSL_SEC_COMPAT 2
246 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
247 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
248 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
249 #define CONFIG_SYS_FSL_ERRATUM_A005125
250 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
252 #elif defined(CONFIG_P1021)
253 #define CONFIG_MAX_CPUS 2
254 #define CONFIG_SYS_FSL_NUM_LAWS 12
255 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
256 #define CONFIG_TSECV2
257 #define CONFIG_FSL_PCIE_DISABLE_ASPM
258 #define CONFIG_SYS_FSL_SEC_COMPAT 2
259 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
260 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
261 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
262 #define QE_MURAM_SIZE 0x6000UL
263 #define MAX_QE_RISC 1
264 #define QE_NUM_OF_SNUM 28
265 #define CONFIG_SYS_FSL_ERRATUM_A005125
266 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
268 #elif defined(CONFIG_P1022)
269 #define CONFIG_MAX_CPUS 2
270 #define CONFIG_SYS_FSL_NUM_LAWS 12
271 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
272 #define CONFIG_TSECV2
273 #define CONFIG_SYS_FSL_SEC_COMPAT 2
274 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
275 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
276 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
277 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
278 #define CONFIG_FSL_SATA_ERRATUM_A001
279 #define CONFIG_SYS_FSL_ERRATUM_A005125
281 #elif defined(CONFIG_P1023)
282 #define CONFIG_MAX_CPUS 2
283 #define CONFIG_SYS_FSL_NUM_LAWS 12
284 #define CONFIG_SYS_FSL_SEC_COMPAT 4
285 #define CONFIG_SYS_NUM_FMAN 1
286 #define CONFIG_SYS_NUM_FM1_DTSEC 2
287 #define CONFIG_NUM_DDR_CONTROLLERS 1
288 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
289 #define CONFIG_SYS_QMAN_NUM_PORTALS 3
290 #define CONFIG_SYS_BMAN_NUM_PORTALS 3
291 #define CONFIG_SYS_FM_MURAM_SIZE 0x10000
292 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
293 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff600000
294 #define CONFIG_SYS_FSL_ERRATUM_A005125
295 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
296 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x11
298 /* P1024 is lower end variant of P1020 */
299 #elif defined(CONFIG_P1024)
300 #define CONFIG_MAX_CPUS 2
301 #define CONFIG_SYS_FSL_NUM_LAWS 12
302 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
303 #define CONFIG_TSECV2
304 #define CONFIG_FSL_PCIE_DISABLE_ASPM
305 #define CONFIG_SYS_FSL_SEC_COMPAT 2
306 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
307 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
308 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
309 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
310 #define CONFIG_SYS_FSL_ERRATUM_A005125
312 /* P1025 is lower end variant of P1021 */
313 #elif defined(CONFIG_P1025)
314 #define CONFIG_MAX_CPUS 2
315 #define CONFIG_SYS_FSL_NUM_LAWS 12
316 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
317 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
318 #define CONFIG_TSECV2
319 #define CONFIG_FSL_PCIE_DISABLE_ASPM
320 #define CONFIG_SYS_FSL_SEC_COMPAT 2
321 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
322 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
323 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
324 #define QE_MURAM_SIZE 0x6000UL
325 #define MAX_QE_RISC 1
326 #define QE_NUM_OF_SNUM 28
327 #define CONFIG_SYS_FSL_ERRATUM_A005125
329 /* P2010 is single core version of P2020 */
330 #elif defined(CONFIG_P2010)
331 #define CONFIG_MAX_CPUS 1
332 #define CONFIG_SYS_FSL_NUM_LAWS 12
333 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
334 #define CONFIG_SYS_FSL_SEC_COMPAT 2
335 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
336 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
337 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
338 #define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001
339 #define CONFIG_SYS_FSL_ERRATUM_A005125
341 #elif defined(CONFIG_P2020)
342 #define CONFIG_MAX_CPUS 2
343 #define CONFIG_SYS_FSL_NUM_LAWS 12
344 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
345 #define CONFIG_SYS_FSL_SEC_COMPAT 2
346 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
347 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
348 #define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001
349 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
350 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
351 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
352 #define CONFIG_SYS_FSL_RMU
353 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
354 #define CONFIG_SYS_FSL_ERRATUM_A005125
355 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
356 #elif defined(CONFIG_PPC_P2041) /* also supports P2040 */
357 #define CONFIG_SYS_FSL_QORIQ_CHASSIS1
358 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
359 #define CONFIG_MAX_CPUS 4
360 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2
361 #define CONFIG_SYS_FSL_NUM_LAWS 32
362 #define CONFIG_SYS_FSL_SEC_COMPAT 4
363 #define CONFIG_SYS_NUM_FMAN 1
364 #define CONFIG_SYS_NUM_FM1_DTSEC 5
365 #define CONFIG_SYS_NUM_FM1_10GEC 1
366 #define CONFIG_NUM_DDR_CONTROLLERS 1
367 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
368 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000
369 #define CONFIG_SYS_FSL_TBCLK_DIV 32
370 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
371 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
372 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
373 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE
374 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
375 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
376 #define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011
377 #define CONFIG_SYS_FSL_ERRATUM_USB14
378 #define CONFIG_SYS_FSL_ERRATUM_CPU_A003999
379 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003
380 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
381 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
382 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
383 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
384 #define CONFIG_SYS_FSL_ERRATUM_A004510
385 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10
386 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2 0x11
387 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
388 #define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
389 #define CONFIG_SYS_FSL_ERRATUM_A004849
390 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
391 #define CONFIG_SYS_FSL_ERRATUM_A006261
392 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x11
394 #elif defined(CONFIG_PPC_P3041)
395 #define CONFIG_SYS_FSL_QORIQ_CHASSIS1
396 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
397 #define CONFIG_MAX_CPUS 4
398 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2
399 #define CONFIG_SYS_FSL_NUM_LAWS 32
400 #define CONFIG_SYS_FSL_SEC_COMPAT 4
401 #define CONFIG_SYS_NUM_FMAN 1
402 #define CONFIG_SYS_NUM_FM1_DTSEC 5
403 #define CONFIG_SYS_NUM_FM1_10GEC 1
404 #define CONFIG_NUM_DDR_CONTROLLERS 1
405 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_5
406 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000
407 #define CONFIG_SYS_FSL_TBCLK_DIV 32
408 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
409 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
410 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
411 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE
412 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
413 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
414 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
415 #define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011
416 #define CONFIG_SYS_FSL_ERRATUM_USB14
417 #define CONFIG_SYS_FSL_ERRATUM_CPU_A003999
418 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003
419 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
420 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
421 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
422 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
423 #define CONFIG_SYS_FSL_ERRATUM_A004510
424 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10
425 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2 0x11
426 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
427 #define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
428 #define CONFIG_SYS_FSL_ERRATUM_A004849
429 #define CONFIG_SYS_FSL_ERRATUM_A005812
430 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
431 #define CONFIG_SYS_FSL_ERRATUM_A006261
432 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x20
434 #elif defined(CONFIG_PPC_P4080) /* also supports P4040 */
435 #define CONFIG_SYS_FSL_QORIQ_CHASSIS1
436 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
437 #define CONFIG_MAX_CPUS 8
438 #define CONFIG_SYS_FSL_NUM_CC_PLLS 4
439 #define CONFIG_SYS_FSL_NUM_LAWS 32
440 #define CONFIG_SYS_FSL_SEC_COMPAT 4
441 #define CONFIG_SYS_NUM_FMAN 2
442 #define CONFIG_SYS_NUM_FM1_DTSEC 4
443 #define CONFIG_SYS_NUM_FM2_DTSEC 4
444 #define CONFIG_SYS_NUM_FM1_10GEC 1
445 #define CONFIG_SYS_NUM_FM2_10GEC 1
446 #define CONFIG_NUM_DDR_CONTROLLERS 2
447 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_4
448 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
449 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000
450 #define CONFIG_SYS_FSL_TBCLK_DIV 16
451 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,p4080-pcie"
452 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
453 #define CONFIG_SYS_FSL_ERRATUM_CPC_A002
454 #define CONFIG_SYS_FSL_ERRATUM_CPC_A003
455 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003
456 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
457 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
458 #define CONFIG_SYS_FSL_ERRATUM_ESDHC135
459 #define CONFIG_SYS_FSL_ERRATUM_ESDHC13
460 #define CONFIG_SYS_P4080_ERRATUM_CPU22
461 #define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011
462 #define CONFIG_SYS_P4080_ERRATUM_SERDES8
463 #define CONFIG_SYS_P4080_ERRATUM_SERDES9
464 #define CONFIG_SYS_P4080_ERRATUM_SERDES_A001
465 #define CONFIG_SYS_P4080_ERRATUM_SERDES_A005
466 #define CONFIG_SYS_FSL_ERRATUM_CPU_A003999
467 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
468 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
469 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
470 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
471 #define CONFIG_SYS_FSL_RMU
472 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
473 #define CONFIG_SYS_FSL_ERRATUM_A004510
474 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x20
475 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xff000000
476 #define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
477 #define CONFIG_SYS_FSL_ERRATUM_A004849
478 #define CONFIG_SYS_FSL_ERRATUM_A004580
479 #define CONFIG_SYS_P4080_ERRATUM_PCIE_A003
480 #define CONFIG_SYS_FSL_ERRATUM_A005812
481 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
482 #define CONFIG_SYS_FSL_ERRATUM_A007075
483 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x20
485 #elif defined(CONFIG_PPC_P5020) /* also supports P5010 */
486 #define CONFIG_SYS_PPC64 /* 64-bit core */
487 #define CONFIG_SYS_FSL_QORIQ_CHASSIS1
488 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
489 #define CONFIG_MAX_CPUS 2
490 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2
491 #define CONFIG_SYS_FSL_NUM_LAWS 32
492 #define CONFIG_SYS_FSL_SEC_COMPAT 4
493 #define CONFIG_SYS_NUM_FMAN 1
494 #define CONFIG_SYS_NUM_FM1_DTSEC 5
495 #define CONFIG_SYS_NUM_FM1_10GEC 1
496 #define CONFIG_NUM_DDR_CONTROLLERS 2
497 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_4
498 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
499 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000
500 #define CONFIG_SYS_FSL_TBCLK_DIV 32
501 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
502 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
503 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
504 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE
505 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
506 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
507 #define CONFIG_SYS_FSL_ERRATUM_USB14
508 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003
509 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
510 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
511 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
512 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
513 #define CONFIG_SYS_FSL_ERRATUM_A004510
514 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10
515 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xc0000000
516 #define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
517 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
518 #define CONFIG_SYS_FSL_ERRATUM_A006261
519 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x20
521 #elif defined(CONFIG_PPC_P5040)
522 #define CONFIG_SYS_PPC64
523 #define CONFIG_SYS_FSL_QORIQ_CHASSIS1
524 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
525 #define CONFIG_MAX_CPUS 4
526 #define CONFIG_SYS_FSL_NUM_CC_PLLS 3
527 #define CONFIG_SYS_FSL_NUM_LAWS 32
528 #define CONFIG_SYS_FSL_SEC_COMPAT 4
529 #define CONFIG_SYS_NUM_FMAN 2
530 #define CONFIG_SYS_NUM_FM1_DTSEC 5
531 #define CONFIG_SYS_NUM_FM1_10GEC 1
532 #define CONFIG_SYS_NUM_FM2_DTSEC 5
533 #define CONFIG_SYS_NUM_FM2_10GEC 1
534 #define CONFIG_NUM_DDR_CONTROLLERS 2
535 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_4
536 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
537 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000
538 #define CONFIG_SYS_FSL_TBCLK_DIV 16
539 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4"
540 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
541 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
542 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE
543 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
544 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
545 #define CONFIG_SYS_FSL_ERRATUM_USB14
546 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003
547 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
548 #define CONFIG_SYS_FSL_ERRATUM_A004699
549 #define CONFIG_SYS_FSL_ERRATUM_A004510
550 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10
551 #define CONFIG_SYS_FSL_ERRATUM_A006261
552 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
553 #define CONFIG_SYS_FSL_ERRATUM_A005812
555 #elif defined(CONFIG_BSC9131)
556 #define CONFIG_MAX_CPUS 1
557 #define CONFIG_FSL_SDHC_V2_3
558 #define CONFIG_SYS_FSL_NUM_LAWS 12
559 #define CONFIG_TSECV2
560 #define CONFIG_SYS_FSL_SEC_COMPAT 4
561 #define CONFIG_NUM_DDR_CONTROLLERS 1
562 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_4
563 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
564 #define CONFIG_SYS_FSL_DSP_M2_RAM_ADDR 0xb0000000
565 #define CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT 0xff600000
566 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 3
567 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
568 #define CONFIG_NAND_FSL_IFC
569 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
570 #define CONFIG_SYS_FSL_ERRATUM_A005125
571 #define CONFIG_ESDHC_HC_BLK_ADDR
573 #elif defined(CONFIG_BSC9132)
574 #define CONFIG_MAX_CPUS 2
575 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 3
576 #define CONFIG_FSL_SDHC_V2_3
577 #define CONFIG_SYS_FSL_NUM_LAWS 12
578 #define CONFIG_TSECV2
579 #define CONFIG_SYS_FSL_SEC_COMPAT 4
580 #define CONFIG_NUM_DDR_CONTROLLERS 2
581 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_6
582 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
583 #define CONFIG_SYS_FSL_DSP_DDR_ADDR 0x40000000
584 #define CONFIG_SYS_FSL_DSP_M2_RAM_ADDR 0xb0000000
585 #define CONFIG_SYS_FSL_DSP_M3_RAM_ADDR 0xc0000000
586 #define CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT 0xff600000
587 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 3
588 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
589 #define CONFIG_NAND_FSL_IFC
590 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
591 #define CONFIG_SYS_FSL_ESDHC_P1010_BROKEN_SDCLK
592 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
593 #define CONFIG_SYS_FSL_ERRATUM_A005125
594 #define CONFIG_SYS_FSL_ERRATUM_A005434
595 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
596 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x11
597 #define CONFIG_ESDHC_HC_BLK_ADDR
599 #elif defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160) || \
600 defined(CONFIG_PPC_T4080)
602 #define CONFIG_SYS_PPC64 /* 64-bit core */
603 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
604 #define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */
605 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4
606 #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */
607 #ifdef CONFIG_PPC_T4240
608 #define CONFIG_MAX_CPUS 12
609 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 4 }
610 #define CONFIG_SYS_NUM_FM1_DTSEC 8
611 #define CONFIG_SYS_NUM_FM1_10GEC 2
612 #define CONFIG_SYS_NUM_FM2_DTSEC 8
613 #define CONFIG_SYS_NUM_FM2_10GEC 2
614 #define CONFIG_NUM_DDR_CONTROLLERS 3
616 #define CONFIG_SYS_NUM_FM1_DTSEC 6
617 #define CONFIG_SYS_NUM_FM1_10GEC 1
618 #define CONFIG_SYS_NUM_FM2_DTSEC 8
619 #define CONFIG_SYS_NUM_FM2_10GEC 1
620 #define CONFIG_NUM_DDR_CONTROLLERS 2
621 #if defined(CONFIG_PPC_T4160)
622 #define CONFIG_MAX_CPUS 8
623 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1 }
624 #elif defined(CONFIG_PPC_T4080)
625 #define CONFIG_MAX_CPUS 4
626 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1 }
629 #define CONFIG_SYS_FSL_NUM_CC_PLLS 5
630 #define CONFIG_SYS_FSL_NUM_LAWS 32
631 #define CONFIG_SYS_FSL_SRDS_1
632 #define CONFIG_SYS_FSL_SRDS_2
633 #define CONFIG_SYS_FSL_SRDS_3
634 #define CONFIG_SYS_FSL_SRDS_4
635 #define CONFIG_SYS_FSL_SEC_COMPAT 4
636 #define CONFIG_SYS_NUM_FMAN 2
637 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
638 #define CONFIG_SYS_PME_CLK 0
639 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7
640 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
641 #define CONFIG_SYS_FMAN_V3
642 #define CONFIG_SYS_FM1_CLK 3
643 #define CONFIG_SYS_FM2_CLK 3
644 #define CONFIG_SYS_FM_MURAM_SIZE 0x60000
645 #define CONFIG_SYS_FSL_TBCLK_DIV 16
646 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v3.0"
647 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
648 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
649 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
650 #define CONFIG_SYS_FSL_SRIO_LIODN
651 #define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
652 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
653 #define CONFIG_SYS_FSL_ERRATUM_A004468
654 #define CONFIG_SYS_FSL_ERRATUM_A_004934
655 #define CONFIG_SYS_FSL_ERRATUM_A005871
656 #define CONFIG_SYS_FSL_ERRATUM_A006261
657 #define CONFIG_SYS_FSL_ERRATUM_A006379
658 #define CONFIG_SYS_FSL_ERRATUM_A006593
659 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
660 #define CONFIG_SYS_FSL_PCI_VER_3_X
662 #elif defined(CONFIG_PPC_B4860) || defined(CONFIG_PPC_B4420)
664 #define CONFIG_SYS_PPC64 /* 64-bit core */
665 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
666 #define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */
667 #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */
668 #define CONFIG_SYS_FSL_NUM_LAWS 32
669 #define CONFIG_SYS_FSL_SRDS_1
670 #define CONFIG_SYS_FSL_SRDS_2
671 #define CONFIG_SYS_FSL_SEC_COMPAT 4
672 #define CONFIG_SYS_NUM_FMAN 1
673 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
674 #define CONFIG_SYS_FM1_CLK 0
675 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7
676 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 4
677 #define CONFIG_SYS_FMAN_V3
678 #define CONFIG_SYS_FM_MURAM_SIZE 0x60000
679 #define CONFIG_SYS_FSL_TBCLK_DIV 16
680 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4"
681 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
682 #define CONFIG_SYS_FSL_ERRATUM_A_004934
683 #define CONFIG_SYS_FSL_ERRATUM_A005871
684 #define CONFIG_SYS_FSL_ERRATUM_A006379
685 #define CONFIG_SYS_FSL_ERRATUM_A006593
686 #define CONFIG_SYS_FSL_ERRATUM_A007075
687 #define CONFIG_SYS_FSL_ERRATUM_A006475
688 #define CONFIG_SYS_FSL_ERRATUM_A006384
689 #define CONFIG_SYS_FSL_ERRATUM_A007212
690 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
692 #ifdef CONFIG_PPC_B4860
693 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4
694 #define CONFIG_MAX_CPUS 4
695 #define CONFIG_SYS_FSL_SRDS_NUM_PLLS 2
696 #define CONFIG_SYS_FSL_NUM_CC_PLLS 4
697 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4, 4, 4 }
698 #define CONFIG_SYS_NUM_FM1_DTSEC 6
699 #define CONFIG_SYS_NUM_FM1_10GEC 2
700 #define CONFIG_NUM_DDR_CONTROLLERS 2
701 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
702 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
703 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
704 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
705 #define CONFIG_SYS_FSL_SRIO_LIODN
707 #define CONFIG_MAX_CPUS 2
708 #define CONFIG_SYS_FSL_SRDS_NUM_PLLS 1
709 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 2
710 #define CONFIG_SYS_FSL_NUM_CC_PLLS 4
711 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4 }
712 #define CONFIG_SYS_NUM_FM1_DTSEC 4
713 #define CONFIG_SYS_NUM_FM1_10GEC 0
714 #define CONFIG_NUM_DDR_CONTROLLERS 1
717 #elif defined(CONFIG_PPC_T1040) || defined(CONFIG_PPC_T1042) ||\
718 defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022)
720 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
721 #define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */
722 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 1
723 #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */
724 #ifdef CONFIG_SYS_FSL_DDR4
725 #define CONFIG_SYS_FSL_DDRC_GEN4
727 #if defined(CONFIG_PPC_T1040) || defined(CONFIG_PPC_T1042)
728 #define CONFIG_MAX_CPUS 4
729 #elif defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022)
730 #define CONFIG_MAX_CPUS 2
732 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2
733 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 1, 1 }
734 #define CONFIG_SYS_SDHC_CLOCK 0
735 #define CONFIG_SYS_FSL_NUM_LAWS 16
736 #define CONFIG_SYS_FSL_SRDS_1
737 #define CONFIG_SYS_FSL_SEC_COMPAT 5
738 #define CONFIG_SYS_NUM_FMAN 1
739 #define CONFIG_SYS_NUM_FM1_DTSEC 5
740 #define CONFIG_NUM_DDR_CONTROLLERS 1
741 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
742 #define CONFIG_PME_PLAT_CLK_DIV 2
743 #define CONFIG_SYS_PME_CLK CONFIG_PME_PLAT_CLK_DIV
744 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_5_0
745 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
746 #define CONFIG_SYS_FMAN_V3
747 #define CONFIG_FM_PLAT_CLK_DIV 1
748 #define CONFIG_SYS_FM1_CLK CONFIG_FM_PLAT_CLK_DIV
749 #define CONFIG_SYS_FM_MURAM_SIZE 0x30000
750 #define CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
751 #define CONFIG_SYS_FSL_TBCLK_DIV 16
752 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4"
753 #define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
754 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
755 #define CONFIG_SYS_FSL_ERRATUM_A006261
756 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
757 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
758 #define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
759 #define QE_MURAM_SIZE 0x6000UL
760 #define MAX_QE_RISC 1
761 #define QE_NUM_OF_SNUM 28
763 #elif defined(CONFIG_PPC_T2080) || defined(CONFIG_PPC_T2081)
765 #define CONFIG_SYS_PPC64 /* 64-bit core */
766 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
767 #define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */
768 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4
769 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2
770 #define CONFIG_SYS_FSL_QMAN_V3
771 #define CONFIG_MAX_CPUS 4
772 #define CONFIG_SYS_FSL_NUM_LAWS 32
773 #define CONFIG_SYS_FSL_SEC_COMPAT 4
774 #define CONFIG_SYS_NUM_FMAN 1
775 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4, 4, 4 }
776 #define CONFIG_SYS_FSL_SRDS_1
777 #define CONFIG_SYS_FSL_PCI_VER_3_X
778 #if defined(CONFIG_PPC_T2080)
779 #define CONFIG_SYS_NUM_FM1_DTSEC 8
780 #define CONFIG_SYS_NUM_FM1_10GEC 4
781 #define CONFIG_SYS_FSL_SRDS_2
782 #define CONFIG_SYS_FSL_SRIO_LIODN
783 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
784 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
785 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
786 #elif defined(CONFIG_PPC_T2081)
787 #define CONFIG_SYS_NUM_FM1_DTSEC 6
788 #define CONFIG_SYS_NUM_FM1_10GEC 2
790 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
791 #define CONFIG_NUM_DDR_CONTROLLERS 1
792 #define CONFIG_PME_PLAT_CLK_DIV 1
793 #define CONFIG_SYS_PME_CLK CONFIG_PME_PLAT_CLK_DIV
794 #define CONFIG_SYS_FM1_CLK 0
795 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7
796 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
797 #define CONFIG_SYS_FMAN_V3
798 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000
799 #define CONFIG_SYS_FSL_TBCLK_DIV 16
800 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v3.0"
801 #define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
802 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
803 #define CONFIG_SYS_FSL_ERRATUM_A007212
804 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
805 #define CONFIG_SYS_FSL_SFP_VER_3_0
806 #define CONFIG_SYS_FSL_ISBC_VER 2
807 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
808 #define CONFIG_SYS_FSL_ERRATUM_A006261
809 #define CONFIG_SYS_FSL_ERRATUM_A006593
810 #define CONFIG_SYS_FSL_ERRATUM_A006379
811 #define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
814 #elif defined(CONFIG_PPC_C29X)
815 #define CONFIG_MAX_CPUS 1
816 #define CONFIG_FSL_SDHC_V2_3
817 #define CONFIG_SYS_FSL_NUM_LAWS 12
818 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 3
819 #define CONFIG_TSECV2_1
820 #define CONFIG_SYS_FSL_SEC_COMPAT 6
821 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
822 #define CONFIG_NUM_DDR_CONTROLLERS 1
823 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_6
824 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
825 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
826 #define CONFIG_SYS_FSL_ERRATUM_A005125
828 #elif defined(CONFIG_QEMU_E500)
829 #define CONFIG_MAX_CPUS 1
830 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xe0000000
833 #error Processor type not defined for this platform
836 #ifndef CONFIG_SYS_CCSRBAR_DEFAULT
837 #error "CONFIG_SYS_CCSRBAR_DEFAULT is not defined for this platform."
841 #define CONFIG_SYS_FSL_THREADS_PER_CORE 2
843 #define CONFIG_SYS_FSL_THREADS_PER_CORE 1
846 #if !defined(CONFIG_SYS_FSL_DDRC_GEN1) && \
847 !defined(CONFIG_SYS_FSL_DDRC_GEN2) && \
848 !defined(CONFIG_SYS_FSL_DDRC_GEN3) && \
849 !defined(CONFIG_SYS_FSL_DDRC_GEN4)
850 #define CONFIG_SYS_FSL_DDRC_GEN3
853 #endif /* _ASM_MPC85xx_CONFIG_H_ */