2 * Copyright 2011-2012 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
7 #ifndef _ASM_MPC85xx_CONFIG_H_
8 #define _ASM_MPC85xx_CONFIG_H_
10 /* SoC specific defines for Freescale MPC85xx (PQ3) and QorIQ processors */
12 #ifdef CONFIG_SYS_CCSRBAR_DEFAULT
13 #error "Do not define CONFIG_SYS_CCSRBAR_DEFAULT in the board header file."
17 * This macro should be removed when we no longer care about backwards
18 * compatibility with older operating systems.
20 #define CONFIG_PPC_SPINTABLE_COMPATIBLE
22 #include <fsl_ddrc_version.h>
23 #define CONFIG_SYS_FSL_DDR_BE
26 #define CONFIG_SYS_FSL_IFC_BE
28 /* Number of TLB CAM entries we have on FSL Book-E chips */
29 #if defined(CONFIG_E500MC)
30 #define CONFIG_SYS_NUM_TLBCAMS 64
31 #elif defined(CONFIG_E500)
32 #define CONFIG_SYS_NUM_TLBCAMS 16
35 #if defined(CONFIG_MPC8536)
36 #define CONFIG_MAX_CPUS 1
37 #define CONFIG_SYS_FSL_NUM_LAWS 12
38 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 1
39 #define CONFIG_SYS_FSL_SEC_COMPAT 2
40 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
41 #define CONFIG_SYS_FSL_ERRATUM_A005125
43 #elif defined(CONFIG_MPC8540)
44 #define CONFIG_MAX_CPUS 1
45 #define CONFIG_SYS_FSL_NUM_LAWS 8
46 #define CONFIG_SYS_FSL_DDRC_GEN1
47 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
49 #elif defined(CONFIG_MPC8541)
50 #define CONFIG_MAX_CPUS 1
51 #define CONFIG_SYS_FSL_NUM_LAWS 8
52 #define CONFIG_SYS_FSL_DDRC_GEN1
53 #define CONFIG_SYS_FSL_SEC_COMPAT 2
54 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
56 #elif defined(CONFIG_MPC8544)
57 #define CONFIG_MAX_CPUS 1
58 #define CONFIG_SYS_FSL_NUM_LAWS 10
59 #define CONFIG_SYS_FSL_DDRC_GEN2
60 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 0
61 #define CONFIG_SYS_FSL_SEC_COMPAT 2
62 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
63 #define CONFIG_SYS_FSL_ERRATUM_A005125
65 #elif defined(CONFIG_MPC8548)
66 #define CONFIG_MAX_CPUS 1
67 #define CONFIG_SYS_FSL_NUM_LAWS 10
68 #define CONFIG_SYS_FSL_DDRC_GEN2
69 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 0
70 #define CONFIG_SYS_FSL_SEC_COMPAT 2
71 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
72 #define CONFIG_SYS_FSL_ERRATUM_NMG_DDR120
73 #define CONFIG_SYS_FSL_ERRATUM_NMG_LBC103
74 #define CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129
75 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1
76 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
77 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
78 #define CONFIG_SYS_FSL_RMU
79 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
80 #define CONFIG_SYS_FSL_ERRATUM_A005125
81 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
82 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x00
84 #elif defined(CONFIG_MPC8555)
85 #define CONFIG_MAX_CPUS 1
86 #define CONFIG_SYS_FSL_NUM_LAWS 8
87 #define CONFIG_SYS_FSL_DDRC_GEN1
88 #define CONFIG_SYS_FSL_SEC_COMPAT 2
89 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
91 #elif defined(CONFIG_MPC8560)
92 #define CONFIG_MAX_CPUS 1
93 #define CONFIG_SYS_FSL_NUM_LAWS 8
94 #define CONFIG_SYS_FSL_DDRC_GEN1
95 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
97 #elif defined(CONFIG_MPC8568)
98 #define CONFIG_MAX_CPUS 1
99 #define CONFIG_SYS_FSL_NUM_LAWS 10
100 #define CONFIG_SYS_FSL_DDRC_GEN2
101 #define CONFIG_SYS_FSL_SEC_COMPAT 2
102 #define QE_MURAM_SIZE 0x10000UL
103 #define MAX_QE_RISC 2
104 #define QE_NUM_OF_SNUM 28
105 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
106 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1
107 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
108 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
109 #define CONFIG_SYS_FSL_RMU
110 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
112 #elif defined(CONFIG_MPC8569)
113 #define CONFIG_MAX_CPUS 1
114 #define CONFIG_SYS_FSL_NUM_LAWS 10
115 #define CONFIG_SYS_FSL_SEC_COMPAT 2
116 #define QE_MURAM_SIZE 0x20000UL
117 #define MAX_QE_RISC 4
118 #define QE_NUM_OF_SNUM 46
119 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
120 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1
121 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
122 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
123 #define CONFIG_SYS_FSL_RMU
124 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
125 #define CONFIG_SYS_FSL_ERRATUM_A005125
127 #elif defined(CONFIG_MPC8572)
128 #define CONFIG_MAX_CPUS 2
129 #define CONFIG_SYS_FSL_NUM_LAWS 12
130 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
131 #define CONFIG_SYS_FSL_SEC_COMPAT 2
132 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
133 #define CONFIG_SYS_FSL_ERRATUM_DDR_115
134 #define CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134
135 #define CONFIG_SYS_FSL_ERRATUM_A005125
137 #elif defined(CONFIG_P1010)
138 #define CONFIG_MAX_CPUS 1
139 #define CONFIG_FSL_SDHC_V2_3
140 #define CONFIG_SYS_FSL_NUM_LAWS 12
141 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 3
142 #define CONFIG_TSECV2
143 #define CONFIG_SYS_FSL_SEC_COMPAT 4
144 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
145 #define CONFIG_NUM_DDR_CONTROLLERS 1
146 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
147 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 4
148 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
149 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
150 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
151 #define CONFIG_SYS_FSL_ERRATUM_IFC_A002769
152 #define CONFIG_SYS_FSL_ERRATUM_P1010_A003549
153 #define CONFIG_SYS_FSL_ERRATUM_SEC_A003571
154 #define CONFIG_SYS_FSL_ERRATUM_IFC_A003399
155 #define CONFIG_SYS_FSL_ERRATUM_A005125
156 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
157 #define CONFIG_SYS_FSL_ERRATUM_A006261
158 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x10
159 #define CONFIG_ESDHC_HC_BLK_ADDR
161 /* P1011 is single core version of P1020 */
162 #elif defined(CONFIG_P1011)
163 #define CONFIG_MAX_CPUS 1
164 #define CONFIG_SYS_FSL_NUM_LAWS 12
165 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
166 #define CONFIG_TSECV2
167 #define CONFIG_FSL_PCIE_DISABLE_ASPM
168 #define CONFIG_SYS_FSL_SEC_COMPAT 2
169 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
170 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
171 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
172 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
173 #define CONFIG_SYS_FSL_ERRATUM_A005125
175 /* P1012 is single core version of P1021 */
176 #elif defined(CONFIG_P1012)
177 #define CONFIG_MAX_CPUS 1
178 #define CONFIG_SYS_FSL_NUM_LAWS 12
179 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
180 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
181 #define CONFIG_TSECV2
182 #define CONFIG_FSL_PCIE_DISABLE_ASPM
183 #define CONFIG_SYS_FSL_SEC_COMPAT 2
184 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
185 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
186 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
187 #define QE_MURAM_SIZE 0x6000UL
188 #define MAX_QE_RISC 1
189 #define QE_NUM_OF_SNUM 28
190 #define CONFIG_SYS_FSL_ERRATUM_A005125
192 /* P1013 is single core version of P1022 */
193 #elif defined(CONFIG_P1013)
194 #define CONFIG_MAX_CPUS 1
195 #define CONFIG_SYS_FSL_NUM_LAWS 12
196 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
197 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
198 #define CONFIG_TSECV2
199 #define CONFIG_SYS_FSL_SEC_COMPAT 2
200 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
201 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
202 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
203 #define CONFIG_FSL_SATA_ERRATUM_A001
204 #define CONFIG_SYS_FSL_ERRATUM_A005125
206 #elif defined(CONFIG_P1014)
207 #define CONFIG_MAX_CPUS 1
208 #define CONFIG_FSL_SDHC_V2_3
209 #define CONFIG_SYS_FSL_NUM_LAWS 12
210 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 3
211 #define CONFIG_TSECV2
212 #define CONFIG_SYS_FSL_SEC_COMPAT 4
213 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
214 #define CONFIG_NUM_DDR_CONTROLLERS 1
215 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
216 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
217 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
218 #define CONFIG_SYS_FSL_ERRATUM_IFC_A002769
219 #define CONFIG_SYS_FSL_ERRATUM_P1010_A003549
220 #define CONFIG_SYS_FSL_ERRATUM_IFC_A003399
222 /* P1017 is single core version of P1023 */
223 #elif defined(CONFIG_P1017)
224 #define CONFIG_MAX_CPUS 1
225 #define CONFIG_SYS_FSL_NUM_LAWS 12
226 #define CONFIG_SYS_FSL_SEC_COMPAT 4
227 #define CONFIG_SYS_NUM_FMAN 1
228 #define CONFIG_SYS_NUM_FM1_DTSEC 2
229 #define CONFIG_NUM_DDR_CONTROLLERS 1
230 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
231 #define CONFIG_SYS_QMAN_NUM_PORTALS 3
232 #define CONFIG_SYS_BMAN_NUM_PORTALS 3
233 #define CONFIG_SYS_FM_MURAM_SIZE 0x10000
234 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
235 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff600000
236 #define CONFIG_SYS_FSL_ERRATUM_A005125
238 #elif defined(CONFIG_P1020)
239 #define CONFIG_MAX_CPUS 2
240 #define CONFIG_SYS_FSL_NUM_LAWS 12
241 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
242 #define CONFIG_TSECV2
243 #define CONFIG_FSL_PCIE_DISABLE_ASPM
244 #define CONFIG_SYS_FSL_SEC_COMPAT 2
245 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
246 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
247 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
248 #define CONFIG_SYS_FSL_ERRATUM_A005125
249 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
251 #elif defined(CONFIG_P1021)
252 #define CONFIG_MAX_CPUS 2
253 #define CONFIG_SYS_FSL_NUM_LAWS 12
254 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
255 #define CONFIG_TSECV2
256 #define CONFIG_FSL_PCIE_DISABLE_ASPM
257 #define CONFIG_SYS_FSL_SEC_COMPAT 2
258 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
259 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
260 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
261 #define QE_MURAM_SIZE 0x6000UL
262 #define MAX_QE_RISC 1
263 #define QE_NUM_OF_SNUM 28
264 #define CONFIG_SYS_FSL_ERRATUM_A005125
265 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
267 #elif defined(CONFIG_P1022)
268 #define CONFIG_MAX_CPUS 2
269 #define CONFIG_SYS_FSL_NUM_LAWS 12
270 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
271 #define CONFIG_TSECV2
272 #define CONFIG_SYS_FSL_SEC_COMPAT 2
273 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
274 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
275 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
276 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
277 #define CONFIG_FSL_SATA_ERRATUM_A001
278 #define CONFIG_SYS_FSL_ERRATUM_A005125
280 #elif defined(CONFIG_P1023)
281 #define CONFIG_MAX_CPUS 2
282 #define CONFIG_SYS_FSL_NUM_LAWS 12
283 #define CONFIG_SYS_FSL_SEC_COMPAT 4
284 #define CONFIG_SYS_NUM_FMAN 1
285 #define CONFIG_SYS_NUM_FM1_DTSEC 2
286 #define CONFIG_NUM_DDR_CONTROLLERS 1
287 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
288 #define CONFIG_SYS_QMAN_NUM_PORTALS 3
289 #define CONFIG_SYS_BMAN_NUM_PORTALS 3
290 #define CONFIG_SYS_FM_MURAM_SIZE 0x10000
291 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
292 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff600000
293 #define CONFIG_SYS_FSL_ERRATUM_A005125
294 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
295 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x11
297 /* P1024 is lower end variant of P1020 */
298 #elif defined(CONFIG_P1024)
299 #define CONFIG_MAX_CPUS 2
300 #define CONFIG_SYS_FSL_NUM_LAWS 12
301 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
302 #define CONFIG_TSECV2
303 #define CONFIG_FSL_PCIE_DISABLE_ASPM
304 #define CONFIG_SYS_FSL_SEC_COMPAT 2
305 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
306 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
307 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
308 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
309 #define CONFIG_SYS_FSL_ERRATUM_A005125
311 /* P1025 is lower end variant of P1021 */
312 #elif defined(CONFIG_P1025)
313 #define CONFIG_MAX_CPUS 2
314 #define CONFIG_SYS_FSL_NUM_LAWS 12
315 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
316 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
317 #define CONFIG_TSECV2
318 #define CONFIG_FSL_PCIE_DISABLE_ASPM
319 #define CONFIG_SYS_FSL_SEC_COMPAT 2
320 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
321 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
322 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
323 #define QE_MURAM_SIZE 0x6000UL
324 #define MAX_QE_RISC 1
325 #define QE_NUM_OF_SNUM 28
326 #define CONFIG_SYS_FSL_ERRATUM_A005125
328 /* P2010 is single core version of P2020 */
329 #elif defined(CONFIG_P2010)
330 #define CONFIG_MAX_CPUS 1
331 #define CONFIG_SYS_FSL_NUM_LAWS 12
332 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
333 #define CONFIG_SYS_FSL_SEC_COMPAT 2
334 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
335 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
336 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
337 #define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001
338 #define CONFIG_SYS_FSL_ERRATUM_A005125
340 #elif defined(CONFIG_P2020)
341 #define CONFIG_MAX_CPUS 2
342 #define CONFIG_SYS_FSL_NUM_LAWS 12
343 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
344 #define CONFIG_SYS_FSL_SEC_COMPAT 2
345 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
346 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
347 #define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001
348 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
349 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
350 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
351 #define CONFIG_SYS_FSL_RMU
352 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
353 #define CONFIG_SYS_FSL_ERRATUM_A005125
354 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
355 #elif defined(CONFIG_PPC_P2041) /* also supports P2040 */
356 #define CONFIG_SYS_FSL_QORIQ_CHASSIS1
357 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
358 #define CONFIG_MAX_CPUS 4
359 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2
360 #define CONFIG_SYS_FSL_NUM_LAWS 32
361 #define CONFIG_SYS_FSL_SEC_COMPAT 4
362 #define CONFIG_SYS_NUM_FMAN 1
363 #define CONFIG_SYS_NUM_FM1_DTSEC 5
364 #define CONFIG_SYS_NUM_FM1_10GEC 1
365 #define CONFIG_NUM_DDR_CONTROLLERS 1
366 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
367 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000
368 #define CONFIG_SYS_FSL_TBCLK_DIV 32
369 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
370 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
371 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
372 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE
373 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
374 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
375 #define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011
376 #define CONFIG_SYS_FSL_ERRATUM_USB14
377 #define CONFIG_SYS_FSL_ERRATUM_CPU_A003999
378 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003
379 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
380 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
381 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
382 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
383 #define CONFIG_SYS_FSL_ERRATUM_A004510
384 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10
385 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2 0x11
386 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
387 #define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
388 #define CONFIG_SYS_FSL_ERRATUM_A004849
389 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
390 #define CONFIG_SYS_FSL_ERRATUM_A006261
391 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x11
393 #elif defined(CONFIG_PPC_P3041)
394 #define CONFIG_SYS_FSL_QORIQ_CHASSIS1
395 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
396 #define CONFIG_MAX_CPUS 4
397 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2
398 #define CONFIG_SYS_FSL_NUM_LAWS 32
399 #define CONFIG_SYS_FSL_SEC_COMPAT 4
400 #define CONFIG_SYS_NUM_FMAN 1
401 #define CONFIG_SYS_NUM_FM1_DTSEC 5
402 #define CONFIG_SYS_NUM_FM1_10GEC 1
403 #define CONFIG_NUM_DDR_CONTROLLERS 1
404 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_5
405 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000
406 #define CONFIG_SYS_FSL_TBCLK_DIV 32
407 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
408 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
409 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
410 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE
411 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
412 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
413 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
414 #define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011
415 #define CONFIG_SYS_FSL_ERRATUM_USB14
416 #define CONFIG_SYS_FSL_ERRATUM_CPU_A003999
417 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003
418 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
419 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
420 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
421 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
422 #define CONFIG_SYS_FSL_ERRATUM_A004510
423 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10
424 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2 0x11
425 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
426 #define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
427 #define CONFIG_SYS_FSL_ERRATUM_A004849
428 #define CONFIG_SYS_FSL_ERRATUM_A005812
429 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
430 #define CONFIG_SYS_FSL_ERRATUM_A006261
431 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x20
433 #elif defined(CONFIG_PPC_P4080) /* also supports P4040 */
434 #define CONFIG_SYS_FSL_QORIQ_CHASSIS1
435 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
436 #define CONFIG_MAX_CPUS 8
437 #define CONFIG_SYS_FSL_NUM_CC_PLLS 4
438 #define CONFIG_SYS_FSL_NUM_LAWS 32
439 #define CONFIG_SYS_FSL_SEC_COMPAT 4
440 #define CONFIG_SYS_NUM_FMAN 2
441 #define CONFIG_SYS_NUM_FM1_DTSEC 4
442 #define CONFIG_SYS_NUM_FM2_DTSEC 4
443 #define CONFIG_SYS_NUM_FM1_10GEC 1
444 #define CONFIG_SYS_NUM_FM2_10GEC 1
445 #define CONFIG_NUM_DDR_CONTROLLERS 2
446 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_4
447 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
448 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000
449 #define CONFIG_SYS_FSL_TBCLK_DIV 16
450 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,p4080-pcie"
451 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
452 #define CONFIG_SYS_FSL_ERRATUM_CPC_A002
453 #define CONFIG_SYS_FSL_ERRATUM_CPC_A003
454 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003
455 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
456 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
457 #define CONFIG_SYS_FSL_ERRATUM_ESDHC135
458 #define CONFIG_SYS_FSL_ERRATUM_ESDHC13
459 #define CONFIG_SYS_P4080_ERRATUM_CPU22
460 #define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011
461 #define CONFIG_SYS_P4080_ERRATUM_SERDES8
462 #define CONFIG_SYS_P4080_ERRATUM_SERDES9
463 #define CONFIG_SYS_P4080_ERRATUM_SERDES_A001
464 #define CONFIG_SYS_P4080_ERRATUM_SERDES_A005
465 #define CONFIG_SYS_FSL_ERRATUM_CPU_A003999
466 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
467 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
468 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
469 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
470 #define CONFIG_SYS_FSL_RMU
471 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
472 #define CONFIG_SYS_FSL_ERRATUM_A004510
473 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x20
474 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xff000000
475 #define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
476 #define CONFIG_SYS_FSL_ERRATUM_A004849
477 #define CONFIG_SYS_FSL_ERRATUM_A004580
478 #define CONFIG_SYS_P4080_ERRATUM_PCIE_A003
479 #define CONFIG_SYS_FSL_ERRATUM_A005812
480 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
481 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x20
483 #elif defined(CONFIG_PPC_P5020) /* also supports P5010 */
484 #define CONFIG_SYS_PPC64 /* 64-bit core */
485 #define CONFIG_SYS_FSL_QORIQ_CHASSIS1
486 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
487 #define CONFIG_MAX_CPUS 2
488 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2
489 #define CONFIG_SYS_FSL_NUM_LAWS 32
490 #define CONFIG_SYS_FSL_SEC_COMPAT 4
491 #define CONFIG_SYS_NUM_FMAN 1
492 #define CONFIG_SYS_NUM_FM1_DTSEC 5
493 #define CONFIG_SYS_NUM_FM1_10GEC 1
494 #define CONFIG_NUM_DDR_CONTROLLERS 2
495 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_4
496 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
497 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000
498 #define CONFIG_SYS_FSL_TBCLK_DIV 32
499 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
500 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
501 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
502 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE
503 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
504 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
505 #define CONFIG_SYS_FSL_ERRATUM_USB14
506 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003
507 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
508 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
509 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
510 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
511 #define CONFIG_SYS_FSL_ERRATUM_A004510
512 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10
513 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xc0000000
514 #define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
515 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
516 #define CONFIG_SYS_FSL_ERRATUM_A006261
517 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x20
519 #elif defined(CONFIG_PPC_P5040)
520 #define CONFIG_SYS_PPC64
521 #define CONFIG_SYS_FSL_QORIQ_CHASSIS1
522 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
523 #define CONFIG_MAX_CPUS 4
524 #define CONFIG_SYS_FSL_NUM_CC_PLLS 3
525 #define CONFIG_SYS_FSL_NUM_LAWS 32
526 #define CONFIG_SYS_FSL_SEC_COMPAT 4
527 #define CONFIG_SYS_NUM_FMAN 2
528 #define CONFIG_SYS_NUM_FM1_DTSEC 5
529 #define CONFIG_SYS_NUM_FM1_10GEC 1
530 #define CONFIG_SYS_NUM_FM2_DTSEC 5
531 #define CONFIG_SYS_NUM_FM2_10GEC 1
532 #define CONFIG_NUM_DDR_CONTROLLERS 2
533 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_4
534 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
535 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000
536 #define CONFIG_SYS_FSL_TBCLK_DIV 16
537 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4"
538 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
539 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
540 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE
541 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
542 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
543 #define CONFIG_SYS_FSL_ERRATUM_USB14
544 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003
545 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
546 #define CONFIG_SYS_FSL_ERRATUM_A004699
547 #define CONFIG_SYS_FSL_ERRATUM_A004510
548 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10
549 #define CONFIG_SYS_FSL_ERRATUM_A006261
550 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
551 #define CONFIG_SYS_FSL_ERRATUM_A005812
553 #elif defined(CONFIG_BSC9131)
554 #define CONFIG_MAX_CPUS 1
555 #define CONFIG_FSL_SDHC_V2_3
556 #define CONFIG_SYS_FSL_NUM_LAWS 12
557 #define CONFIG_TSECV2
558 #define CONFIG_SYS_FSL_SEC_COMPAT 4
559 #define CONFIG_NUM_DDR_CONTROLLERS 1
560 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_4
561 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
562 #define CONFIG_SYS_FSL_DSP_M2_RAM_ADDR 0xb0000000
563 #define CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT 0xff600000
564 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 3
565 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
566 #define CONFIG_NAND_FSL_IFC
567 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
568 #define CONFIG_SYS_FSL_ERRATUM_A005125
569 #define CONFIG_ESDHC_HC_BLK_ADDR
571 #elif defined(CONFIG_BSC9132)
572 #define CONFIG_MAX_CPUS 2
573 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 3
574 #define CONFIG_FSL_SDHC_V2_3
575 #define CONFIG_SYS_FSL_NUM_LAWS 12
576 #define CONFIG_TSECV2
577 #define CONFIG_SYS_FSL_SEC_COMPAT 4
578 #define CONFIG_NUM_DDR_CONTROLLERS 2
579 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_6
580 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
581 #define CONFIG_SYS_FSL_DSP_DDR_ADDR 0x40000000
582 #define CONFIG_SYS_FSL_DSP_M2_RAM_ADDR 0xb0000000
583 #define CONFIG_SYS_FSL_DSP_M3_RAM_ADDR 0xc0000000
584 #define CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT 0xff600000
585 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 3
586 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
587 #define CONFIG_NAND_FSL_IFC
588 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
589 #define CONFIG_SYS_FSL_ESDHC_P1010_BROKEN_SDCLK
590 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
591 #define CONFIG_SYS_FSL_ERRATUM_A005125
592 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
593 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x11
594 #define CONFIG_ESDHC_HC_BLK_ADDR
596 #elif defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160)
598 #define CONFIG_SYS_PPC64 /* 64-bit core */
599 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
600 #define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */
601 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4
602 #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */
603 #ifdef CONFIG_PPC_T4240
604 #define CONFIG_MAX_CPUS 12
605 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 4 }
606 #define CONFIG_SYS_NUM_FM1_DTSEC 8
607 #define CONFIG_SYS_NUM_FM1_10GEC 2
608 #define CONFIG_SYS_NUM_FM2_DTSEC 8
609 #define CONFIG_SYS_NUM_FM2_10GEC 2
610 #define CONFIG_NUM_DDR_CONTROLLERS 3
612 #define CONFIG_MAX_CPUS 8
613 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1 }
614 #define CONFIG_SYS_NUM_FM1_DTSEC 7
615 #define CONFIG_SYS_NUM_FM1_10GEC 1
616 #define CONFIG_SYS_NUM_FM2_DTSEC 7
617 #define CONFIG_SYS_NUM_FM2_10GEC 1
618 #define CONFIG_NUM_DDR_CONTROLLERS 2
620 #define CONFIG_SYS_FSL_NUM_CC_PLLS 5
621 #define CONFIG_SYS_FSL_NUM_LAWS 32
622 #define CONFIG_SYS_FSL_SRDS_1
623 #define CONFIG_SYS_FSL_SRDS_2
624 #define CONFIG_SYS_FSL_SRDS_3
625 #define CONFIG_SYS_FSL_SRDS_4
626 #define CONFIG_SYS_FSL_SEC_COMPAT 4
627 #define CONFIG_SYS_NUM_FMAN 2
628 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
629 #define CONFIG_SYS_PME_CLK 0
630 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7
631 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
632 #define CONFIG_SYS_FMAN_V3
633 #define CONFIG_SYS_FM1_CLK 3
634 #define CONFIG_SYS_FM2_CLK 3
635 #define CONFIG_SYS_FM_MURAM_SIZE 0x60000
636 #define CONFIG_SYS_FSL_TBCLK_DIV 16
637 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v3.0"
638 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
639 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
640 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
641 #define CONFIG_SYS_FSL_SRIO_LIODN
642 #define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
643 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
644 #define CONFIG_SYS_FSL_ERRATUM_A004468
645 #define CONFIG_SYS_FSL_ERRATUM_A_004934
646 #define CONFIG_SYS_FSL_ERRATUM_A005871
647 #define CONFIG_SYS_FSL_ERRATUM_A006261
648 #define CONFIG_SYS_FSL_ERRATUM_A006379
649 #define CONFIG_SYS_FSL_ERRATUM_A006593
650 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
651 #define CONFIG_SYS_FSL_PCI_VER_3_X
653 #elif defined(CONFIG_PPC_B4860) || defined(CONFIG_PPC_B4420)
655 #define CONFIG_SYS_PPC64 /* 64-bit core */
656 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
657 #define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */
658 #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */
659 #define CONFIG_SYS_FSL_NUM_LAWS 32
660 #define CONFIG_SYS_FSL_SRDS_1
661 #define CONFIG_SYS_FSL_SRDS_2
662 #define CONFIG_SYS_FSL_SEC_COMPAT 4
663 #define CONFIG_SYS_NUM_FMAN 1
664 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
665 #define CONFIG_SYS_FM1_CLK 0
666 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7
667 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 4
668 #define CONFIG_SYS_FMAN_V3
669 #define CONFIG_SYS_FM_MURAM_SIZE 0x60000
670 #define CONFIG_SYS_FSL_TBCLK_DIV 16
671 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4"
672 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
673 #define CONFIG_SYS_FSL_ERRATUM_A_004934
674 #define CONFIG_SYS_FSL_ERRATUM_A005871
675 #define CONFIG_SYS_FSL_ERRATUM_A006379
676 #define CONFIG_SYS_FSL_ERRATUM_A006593
677 #define CONFIG_SYS_FSL_ERRATUM_A006475
678 #define CONFIG_SYS_FSL_ERRATUM_A006384
679 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
681 #ifdef CONFIG_PPC_B4860
682 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4
683 #define CONFIG_MAX_CPUS 4
684 #define CONFIG_SYS_FSL_SRDS_NUM_PLLS 2
685 #define CONFIG_SYS_FSL_NUM_CC_PLLS 4
686 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4, 4, 4 }
687 #define CONFIG_SYS_NUM_FM1_DTSEC 6
688 #define CONFIG_SYS_NUM_FM1_10GEC 2
689 #define CONFIG_NUM_DDR_CONTROLLERS 2
690 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
691 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
692 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
693 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
694 #define CONFIG_SYS_FSL_SRIO_LIODN
696 #define CONFIG_MAX_CPUS 2
697 #define CONFIG_SYS_FSL_SRDS_NUM_PLLS 1
698 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 2
699 #define CONFIG_SYS_FSL_NUM_CC_PLLS 4
700 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4 }
701 #define CONFIG_SYS_NUM_FM1_DTSEC 4
702 #define CONFIG_SYS_NUM_FM1_10GEC 0
703 #define CONFIG_NUM_DDR_CONTROLLERS 1
706 #elif defined(CONFIG_PPC_T1040) || defined(CONFIG_PPC_T1042) ||\
707 defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022)
709 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
710 #define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */
711 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 1
712 #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */
713 #ifdef CONFIG_SYS_FSL_DDR4
714 #define CONFIG_SYS_FSL_DDRC_GEN4
716 #if defined(CONFIG_PPC_T1040) || defined(CONFIG_PPC_T1042)
717 #define CONFIG_MAX_CPUS 4
718 #elif defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022)
719 #define CONFIG_MAX_CPUS 2
721 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2
722 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 1, 1 }
723 #define CONFIG_SYS_SDHC_CLOCK 0
724 #define CONFIG_SYS_FSL_NUM_LAWS 16
725 #define CONFIG_SYS_FSL_SRDS_1
726 #define CONFIG_SYS_FSL_SEC_COMPAT 5
727 #define CONFIG_SYS_NUM_FMAN 1
728 #define CONFIG_SYS_NUM_FM1_DTSEC 5
729 #define CONFIG_NUM_DDR_CONTROLLERS 1
730 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
731 #define CONFIG_PME_PLAT_CLK_DIV 2
732 #define CONFIG_SYS_PME_CLK CONFIG_PME_PLAT_CLK_DIV
733 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_5_0
734 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
735 #define CONFIG_SYS_FMAN_V3
736 #define CONFIG_FM_PLAT_CLK_DIV 1
737 #define CONFIG_SYS_FM1_CLK CONFIG_FM_PLAT_CLK_DIV
738 #define CONFIG_SYS_FM_MURAM_SIZE 0x30000
739 #define CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
740 #define CONFIG_SYS_FSL_TBCLK_DIV 16
741 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4"
742 #define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
743 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
744 #define CONFIG_SYS_FSL_ERRATUM_A006261
745 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
746 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
747 #define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
748 #define QE_MURAM_SIZE 0x6000UL
749 #define MAX_QE_RISC 1
750 #define QE_NUM_OF_SNUM 28
752 #elif defined(CONFIG_PPC_T2080) || defined(CONFIG_PPC_T2081)
754 #define CONFIG_SYS_PPC64 /* 64-bit core */
755 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
756 #define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */
757 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4
758 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2
759 #define CONFIG_SYS_FSL_QMAN_V3
760 #define CONFIG_MAX_CPUS 4
761 #define CONFIG_SYS_FSL_NUM_LAWS 32
762 #define CONFIG_SYS_FSL_SEC_COMPAT 4
763 #define CONFIG_SYS_NUM_FMAN 1
764 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4, 4, 4 }
765 #define CONFIG_SYS_FSL_SRDS_1
766 #define CONFIG_SYS_FSL_PCI_VER_3_X
767 #if defined(CONFIG_PPC_T2080)
768 #define CONFIG_SYS_NUM_FM1_DTSEC 8
769 #define CONFIG_SYS_NUM_FM1_10GEC 4
770 #define CONFIG_SYS_FSL_SRDS_2
771 #define CONFIG_SYS_FSL_SRIO_LIODN
772 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
773 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
774 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
775 #elif defined(CONFIG_PPC_T2081)
776 #define CONFIG_SYS_NUM_FM1_DTSEC 6
777 #define CONFIG_SYS_NUM_FM1_10GEC 2
779 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
780 #define CONFIG_NUM_DDR_CONTROLLERS 1
781 #define CONFIG_PME_PLAT_CLK_DIV 1
782 #define CONFIG_SYS_PME_CLK CONFIG_PME_PLAT_CLK_DIV
783 #define CONFIG_SYS_FM1_CLK 0
784 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7
785 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
786 #define CONFIG_SYS_FMAN_V3
787 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000
788 #define CONFIG_SYS_FSL_TBCLK_DIV 16
789 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v3.0"
790 #define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
791 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
792 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
793 #define CONFIG_SYS_FSL_SFP_VER_3_0
794 #define CONFIG_SYS_FSL_ISBC_VER 2
795 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
796 #define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
799 #elif defined(CONFIG_PPC_C29X)
800 #define CONFIG_MAX_CPUS 1
801 #define CONFIG_FSL_SDHC_V2_3
802 #define CONFIG_SYS_FSL_NUM_LAWS 12
803 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 3
804 #define CONFIG_TSECV2_1
805 #define CONFIG_SYS_FSL_SEC_COMPAT 6
806 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
807 #define CONFIG_NUM_DDR_CONTROLLERS 1
808 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_6
809 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
810 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
811 #define CONFIG_SYS_FSL_ERRATUM_A005125
813 #elif defined(CONFIG_QEMU_E500)
814 #define CONFIG_MAX_CPUS 1
815 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xe0000000
818 #error Processor type not defined for this platform
821 #ifndef CONFIG_SYS_CCSRBAR_DEFAULT
822 #error "CONFIG_SYS_CCSRBAR_DEFAULT is not defined for this platform."
826 #define CONFIG_SYS_FSL_THREADS_PER_CORE 2
828 #define CONFIG_SYS_FSL_THREADS_PER_CORE 1
831 #if !defined(CONFIG_SYS_FSL_DDRC_GEN1) && \
832 !defined(CONFIG_SYS_FSL_DDRC_GEN2) && \
833 !defined(CONFIG_SYS_FSL_DDRC_GEN3) && \
834 !defined(CONFIG_SYS_FSL_DDRC_GEN4)
835 #define CONFIG_SYS_FSL_DDRC_GEN3
838 #endif /* _ASM_MPC85xx_CONFIG_H_ */