2 * Copyright 2008-2011 Freescale Semiconductor, Inc.
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * Version 2 as published by the Free Software Foundation.
9 #ifndef FSL_DDR_MEMCTL_H
10 #define FSL_DDR_MEMCTL_H
13 * Pick a basic DDR Technology.
17 #define SDRAM_TYPE_DDR1 2
18 #define SDRAM_TYPE_DDR2 3
19 #define SDRAM_TYPE_LPDDR1 6
20 #define SDRAM_TYPE_DDR3 7
22 #define DDR_BL4 4 /* burst length 4 */
23 #define DDR_BC4 DDR_BL4 /* burst chop for ddr3 */
24 #define DDR_OTF 6 /* on-the-fly BC4 and BL8 */
25 #define DDR_BL8 8 /* burst length 8 */
27 #define DDR3_RTT_OFF 0
28 #define DDR3_RTT_60_OHM 1 /* RTT_Nom = RZQ/4 */
29 #define DDR3_RTT_120_OHM 2 /* RTT_Nom = RZQ/2 */
30 #define DDR3_RTT_40_OHM 3 /* RTT_Nom = RZQ/6 */
31 #define DDR3_RTT_20_OHM 4 /* RTT_Nom = RZQ/12 */
32 #define DDR3_RTT_30_OHM 5 /* RTT_Nom = RZQ/8 */
34 #if defined(CONFIG_FSL_DDR1)
35 #define FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR (1)
36 typedef ddr1_spd_eeprom_t generic_spd_eeprom_t;
37 #ifndef CONFIG_FSL_SDRAM_TYPE
38 #define CONFIG_FSL_SDRAM_TYPE SDRAM_TYPE_DDR1
40 #elif defined(CONFIG_FSL_DDR2)
41 #define FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR (3)
42 typedef ddr2_spd_eeprom_t generic_spd_eeprom_t;
43 #ifndef CONFIG_FSL_SDRAM_TYPE
44 #define CONFIG_FSL_SDRAM_TYPE SDRAM_TYPE_DDR2
46 #elif defined(CONFIG_FSL_DDR3)
47 #define FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR (3) /* FIXME */
48 typedef ddr3_spd_eeprom_t generic_spd_eeprom_t;
49 #ifndef CONFIG_FSL_SDRAM_TYPE
50 #define CONFIG_FSL_SDRAM_TYPE SDRAM_TYPE_DDR3
52 #endif /* #if defined(CONFIG_FSL_DDR1) */
54 #define FSL_DDR_ODT_NEVER 0x0
55 #define FSL_DDR_ODT_CS 0x1
56 #define FSL_DDR_ODT_ALL_OTHER_CS 0x2
57 #define FSL_DDR_ODT_OTHER_DIMM 0x3
58 #define FSL_DDR_ODT_ALL 0x4
59 #define FSL_DDR_ODT_SAME_DIMM 0x5
60 #define FSL_DDR_ODT_CS_AND_OTHER_DIMM 0x6
61 #define FSL_DDR_ODT_OTHER_CS_ONSAMEDIMM 0x7
63 /* define bank(chip select) interleaving mode */
64 #define FSL_DDR_CS0_CS1 0x40
65 #define FSL_DDR_CS2_CS3 0x20
66 #define FSL_DDR_CS0_CS1_AND_CS2_CS3 (FSL_DDR_CS0_CS1 | FSL_DDR_CS2_CS3)
67 #define FSL_DDR_CS0_CS1_CS2_CS3 (FSL_DDR_CS0_CS1_AND_CS2_CS3 | 0x04)
69 /* define memory controller interleaving mode */
70 #define FSL_DDR_CACHE_LINE_INTERLEAVING 0x0
71 #define FSL_DDR_PAGE_INTERLEAVING 0x1
72 #define FSL_DDR_BANK_INTERLEAVING 0x2
73 #define FSL_DDR_SUPERBANK_INTERLEAVING 0x3
75 /* DDR_SDRAM_CFG - DDR SDRAM Control Configuration
77 #define SDRAM_CFG_MEM_EN 0x80000000
78 #define SDRAM_CFG_SREN 0x40000000
79 #define SDRAM_CFG_ECC_EN 0x20000000
80 #define SDRAM_CFG_RD_EN 0x10000000
81 #define SDRAM_CFG_SDRAM_TYPE_DDR1 0x02000000
82 #define SDRAM_CFG_SDRAM_TYPE_DDR2 0x03000000
83 #define SDRAM_CFG_SDRAM_TYPE_MASK 0x07000000
84 #define SDRAM_CFG_SDRAM_TYPE_SHIFT 24
85 #define SDRAM_CFG_DYN_PWR 0x00200000
86 #define SDRAM_CFG_32_BE 0x00080000
87 #define SDRAM_CFG_8_BE 0x00040000
88 #define SDRAM_CFG_NCAP 0x00020000
89 #define SDRAM_CFG_2T_EN 0x00008000
90 #define SDRAM_CFG_BI 0x00000001
92 #if defined(CONFIG_P4080)
93 #define RD_TO_PRE_MASK 0xf
94 #define RD_TO_PRE_SHIFT 13
95 #define WR_DATA_DELAY_MASK 0xf
96 #define WR_DATA_DELAY_SHIFT 9
98 #define RD_TO_PRE_MASK 0x7
99 #define RD_TO_PRE_SHIFT 13
100 #define WR_DATA_DELAY_MASK 0x7
101 #define WR_DATA_DELAY_SHIFT 10
104 /* Record of register values computed */
105 typedef struct fsl_ddr_cfg_regs_s {
109 unsigned int config_2;
110 } cs[CONFIG_CHIP_SELECTS_PER_CTRL];
111 unsigned int timing_cfg_3;
112 unsigned int timing_cfg_0;
113 unsigned int timing_cfg_1;
114 unsigned int timing_cfg_2;
115 unsigned int ddr_sdram_cfg;
116 unsigned int ddr_sdram_cfg_2;
117 unsigned int ddr_sdram_mode;
118 unsigned int ddr_sdram_mode_2;
119 unsigned int ddr_sdram_mode_3;
120 unsigned int ddr_sdram_mode_4;
121 unsigned int ddr_sdram_mode_5;
122 unsigned int ddr_sdram_mode_6;
123 unsigned int ddr_sdram_mode_7;
124 unsigned int ddr_sdram_mode_8;
125 unsigned int ddr_sdram_md_cntl;
126 unsigned int ddr_sdram_interval;
127 unsigned int ddr_data_init;
128 unsigned int ddr_sdram_clk_cntl;
129 unsigned int ddr_init_addr;
130 unsigned int ddr_init_ext_addr;
131 unsigned int timing_cfg_4;
132 unsigned int timing_cfg_5;
133 unsigned int ddr_zq_cntl;
134 unsigned int ddr_wrlvl_cntl;
135 unsigned int ddr_sr_cntr;
136 unsigned int ddr_sdram_rcw_1;
137 unsigned int ddr_sdram_rcw_2;
138 unsigned int ddr_eor;
139 unsigned int ddr_cdr1;
140 unsigned int ddr_cdr2;
141 unsigned int err_disable;
142 unsigned int err_int_en;
143 unsigned int debug[32];
144 } fsl_ddr_cfg_regs_t;
146 typedef struct memctl_options_partial_s {
147 unsigned int all_DIMMs_ECC_capable;
148 unsigned int all_DIMMs_tCKmax_ps;
149 unsigned int all_DIMMs_burst_lengths_bitmask;
150 unsigned int all_DIMMs_registered;
151 unsigned int all_DIMMs_unbuffered;
152 /* unsigned int lowest_common_SPD_caslat; */
153 unsigned int all_DIMMs_minimum_tRCD_ps;
154 } memctl_options_partial_t;
157 * Generalized parameters for memory controller configuration,
158 * might be a little specific to the FSL memory controller
160 typedef struct memctl_options_s {
162 * Memory organization parameters
164 * if DIMM is present in the system
165 * where DIMMs are with respect to chip select
166 * where chip selects are with respect to memory boundaries
168 unsigned int registered_dimm_en; /* use registered DIMM support */
170 /* Options local to a Chip Select */
171 struct cs_local_opts_s {
172 unsigned int auto_precharge;
173 unsigned int odt_rd_cfg;
174 unsigned int odt_wr_cfg;
175 unsigned int odt_rtt_norm;
176 unsigned int odt_rtt_wr;
177 } cs_local_opts[CONFIG_CHIP_SELECTS_PER_CTRL];
179 /* Special configurations for chip select */
180 unsigned int memctl_interleaving;
181 unsigned int memctl_interleaving_mode;
182 unsigned int ba_intlv_ctl;
183 unsigned int addr_hash;
185 /* Operational mode parameters */
186 unsigned int ECC_mode; /* Use ECC? */
187 /* Initialize ECC using memory controller? */
188 unsigned int ECC_init_using_memctl;
189 unsigned int DQS_config; /* Use DQS? maybe only with DDR2? */
190 /* SREN - self-refresh during sleep */
191 unsigned int self_refresh_in_sleep;
192 unsigned int dynamic_power; /* DYN_PWR */
193 /* memory data width to use (16-bit, 32-bit, 64-bit) */
194 unsigned int data_bus_width;
195 unsigned int burst_length; /* BL4, OTF and BL8 */
196 /* On-The-Fly Burst Chop enable */
197 unsigned int OTF_burst_chop_en;
198 /* mirrior DIMMs for DDR3 */
199 unsigned int mirrored_dimm;
200 unsigned int quad_rank_present;
201 unsigned int ap_en; /* address parity enable for RDIMM */
203 /* Global Timing Parameters */
204 unsigned int cas_latency_override;
205 unsigned int cas_latency_override_value;
206 unsigned int use_derated_caslat;
207 unsigned int additive_latency_override;
208 unsigned int additive_latency_override_value;
210 unsigned int clk_adjust; /* */
211 unsigned int cpo_override;
212 unsigned int write_data_delay; /* DQS adjust */
214 unsigned int wrlvl_override;
215 unsigned int wrlvl_sample; /* Write leveling */
216 unsigned int wrlvl_start;
218 unsigned int half_strength_driver_enable;
219 unsigned int twoT_en;
220 unsigned int threeT_en;
221 unsigned int bstopre;
222 unsigned int tCKE_clock_pulse_width_ps; /* tCKE */
223 unsigned int tFAW_window_four_activates_ps; /* tFAW -- FOUR_ACT */
226 unsigned int rtt_override; /* rtt_override enable */
227 unsigned int rtt_override_value; /* that is Rtt_Nom for DDR3 */
228 unsigned int rtt_wr_override_value; /* this is Rtt_WR for DDR3 */
230 /* Automatic self refresh */
231 unsigned int auto_self_refresh_en;
236 unsigned int wrlvl_en;
237 /* RCW override for RDIMM */
238 unsigned int rcw_override;
241 /* control register 1 */
242 unsigned int ddr_cdr1;
245 extern phys_size_t fsl_ddr_sdram(void);
246 extern int fsl_use_spd(void);
249 * The 85xx boards have a common prototype for fixed_sdram so put the
252 #ifdef CONFIG_MPC85xx
253 extern phys_size_t fixed_sdram(void);
256 #if defined(CONFIG_DDR_ECC)
257 extern void ddr_enable_ecc(unsigned int dram_size);
261 typedef struct fixed_ddr_parm{
264 fsl_ddr_cfg_regs_t *ddr_settings;