2 * Copyright 2010-2011 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
7 #ifndef __FSL_SECURE_BOOT_H
8 #define __FSL_SECURE_BOOT_H
9 #include <asm/config_mpc85xx.h>
11 #ifdef CONFIG_SECURE_BOOT
12 #if defined(CONFIG_FSL_CORENET)
13 #define CONFIG_SYS_PBI_FLASH_BASE 0xc0000000
14 #elif defined(CONFIG_TARGET_BSC9132QDS)
15 #define CONFIG_SYS_PBI_FLASH_BASE 0xc8000000
16 #elif defined(CONFIG_TARGET_C29XPCIE)
17 #define CONFIG_SYS_PBI_FLASH_BASE 0xcc000000
19 #define CONFIG_SYS_PBI_FLASH_BASE 0xce000000
21 #define CONFIG_SYS_PBI_FLASH_WINDOW 0xcff80000
23 #if defined(CONFIG_TARGET_B4860QDS) || \
24 defined(CONFIG_TARGET_B4420QDS) || \
25 defined(CONFIG_TARGET_T4160QDS) || \
26 defined(CONFIG_TARGET_T4240QDS) || \
27 defined(CONFIG_TARGET_T2080QDS) || \
28 defined(CONFIG_TARGET_T2080RDB) || \
29 defined(CONFIG_TARGET_T1040QDS) || \
30 defined(CONFIG_TARGET_T1040RDB) || \
31 defined(CONFIG_TARGET_T1040D4RDB) || \
32 defined(CONFIG_TARGET_T1042RDB) || \
33 defined(CONFIG_TARGET_T1042D4RDB) || \
34 defined(CONFIG_TARGET_T1042RDB_PI) || \
35 defined(CONFIG_ARCH_T1023) || \
36 defined(CONFIG_ARCH_T1024)
37 #ifndef CONFIG_SYS_RAMBOOT
38 #define CONFIG_SYS_CPC_REINIT_F
40 #define CONFIG_KEY_REVOCATION
41 #undef CONFIG_SYS_INIT_L3_ADDR
42 #define CONFIG_SYS_INIT_L3_ADDR 0xbff00000
45 #if defined(CONFIG_RAMBOOT_PBL)
46 #undef CONFIG_SYS_INIT_L3_ADDR
47 #ifdef CONFIG_SYS_INIT_L3_VADDR
48 #define CONFIG_SYS_INIT_L3_ADDR \
49 (CONFIG_SYS_INIT_L3_VADDR & ~0xFFF00000) | \
52 #define CONFIG_SYS_INIT_L3_ADDR 0xbff00000
56 #if defined(CONFIG_TARGET_C29XPCIE)
57 #define CONFIG_KEY_REVOCATION
60 #if defined(CONFIG_ARCH_P3041) || \
61 defined(CONFIG_ARCH_P4080) || \
62 defined(CONFIG_ARCH_P5020) || \
63 defined(CONFIG_ARCH_P5040) || \
64 defined(CONFIG_ARCH_P2041)
65 #define CONFIG_FSL_TRUST_ARCH_v1
68 #if defined(CONFIG_FSL_CORENET) && !defined(CONFIG_SYS_RAMBOOT)
69 /* The key used for verification of next level images
70 * is picked up from an Extension Table which has
71 * been verified by the ISBC (Internal Secure boot Code)
72 * in boot ROM of the SoC.
73 * The feature is only applicable in case of NOR boot and is
74 * not applicable in case of RAMBOOT (NAND, SD, SPI).
76 #define CONFIG_FSL_ISBC_KEY_EXT
78 #endif /* #ifdef CONFIG_SECURE_BOOT */
80 #ifdef CONFIG_CHAIN_OF_TRUST
81 #ifdef CONFIG_SPL_BUILD
83 * PPAACT and SPAACT table for PAMU must be placed on DDR after DDR init
84 * due to space crunch on CPC and thus malloc will not work.
86 #define CONFIG_SPL_PPAACT_ADDR 0x2e000000
87 #define CONFIG_SPL_SPAACT_ADDR 0x2f000000
88 #define CONFIG_SPL_JR0_LIODN_S 454
89 #define CONFIG_SPL_JR0_LIODN_NS 458
91 * Define the key hash for U-Boot here if public/private key pair used to
92 * sign U-boot are different from the SRK hash put in the fuse
93 * Example of defining KEY_HASH is
94 * #define CONFIG_SPL_UBOOT_KEY_HASH \
95 * "41066b564c6ffcef40ccbc1e0a5d0d519604000c785d97bbefd25e4d288d1c8b"
96 * else leave it defined as NULL
99 #define CONFIG_SPL_UBOOT_KEY_HASH NULL
100 #endif /* ifdef CONFIG_SPL_BUILD */
102 #define CONFIG_CMD_ESBC_VALIDATE
103 #define CONFIG_FSL_SEC_MON
105 #ifndef CONFIG_SPL_BUILD
107 * fsl_setenv_chain_of_trust() must be called from
111 /* If Boot Script is not on NOR and is required to be copied on RAM */
112 #ifdef CONFIG_BOOTSCRIPT_COPY_RAM
113 #define CONFIG_BS_HDR_ADDR_RAM 0x00010000
114 #define CONFIG_BS_HDR_ADDR_DEVICE 0x00800000
115 #define CONFIG_BS_HDR_SIZE 0x00002000
116 #define CONFIG_BS_ADDR_RAM 0x00012000
117 #define CONFIG_BS_ADDR_DEVICE 0x00802000
118 #define CONFIG_BS_SIZE 0x00001000
120 #define CONFIG_BOOTSCRIPT_HDR_ADDR CONFIG_BS_HDR_ADDR_RAM
123 /* The bootscript header address is different for B4860 because the NOR
124 * mapping is different on B4 due to reduced NOR size.
126 #if defined(CONFIG_TARGET_B4860QDS) || defined(CONFIG_TARGET_B4420QDS)
127 #define CONFIG_BOOTSCRIPT_HDR_ADDR 0xecc00000
128 #elif defined(CONFIG_FSL_CORENET)
129 #define CONFIG_BOOTSCRIPT_HDR_ADDR 0xe8e00000
130 #elif defined(CONFIG_TARGET_BSC9132QDS)
131 #define CONFIG_BOOTSCRIPT_HDR_ADDR 0x88020000
132 #elif defined(CONFIG_TARGET_C29XPCIE)
133 #define CONFIG_BOOTSCRIPT_HDR_ADDR 0xec020000
135 #define CONFIG_BOOTSCRIPT_HDR_ADDR 0xee020000
138 #endif /* #ifdef CONFIG_BOOTSCRIPT_COPY_RAM */
140 #include <config_fsl_chain_trust.h>
141 #endif /* #ifndef CONFIG_SPL_BUILD */
142 #endif /* #ifdef CONFIG_CHAIN_OF_TRUST */