2 * Copyright 2010 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
61 QSGMII_FM1_A, /* A indicates MACs 1-4 */
62 QSGMII_FM1_B, /* B indicates MACs 5,6,9,10 */
72 QSGMII_SW1_A, /* Indicates ports on L2 Switch */
74 SGMII_2500_FM1_DTSEC1,
75 SGMII_2500_FM1_DTSEC2,
76 SGMII_2500_FM1_DTSEC3,
77 SGMII_2500_FM1_DTSEC4,
78 SGMII_2500_FM1_DTSEC5,
79 SGMII_2500_FM1_DTSEC6,
80 SGMII_2500_FM1_DTSEC9,
81 SGMII_2500_FM1_DTSEC10,
82 SGMII_2500_FM2_DTSEC1,
83 SGMII_2500_FM2_DTSEC2,
84 SGMII_2500_FM2_DTSEC3,
85 SGMII_2500_FM2_DTSEC4,
86 SGMII_2500_FM2_DTSEC5,
87 SGMII_2500_FM2_DTSEC6,
88 SGMII_2500_FM2_DTSEC9,
89 SGMII_2500_FM2_DTSEC10,
90 SERDES_PRCTL_COUNT /* Keep this item the last one */
100 int is_serdes_configured(enum srds_prtcl device);
101 void fsl_serdes_init(void);
102 const char *serdes_clock_to_string(u32 clock);
104 #ifdef CONFIG_FSL_CORENET
105 #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
106 int serdes_get_first_lane(u32 sd, enum srds_prtcl device);
107 enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane);
109 int serdes_get_first_lane(enum srds_prtcl device);
111 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES9
112 void serdes_reset_rx(enum srds_prtcl device);
116 #endif /* __FSL_SERDES_H */