1 menu "x86 architecture"
8 prompt "Mainboard vendor"
9 default VENDOR_EMULATION
11 config VENDOR_COREBOOT
17 config VENDOR_EMULATION
28 # board-specific options below
29 source "board/coreboot/Kconfig"
30 source "board/efi/Kconfig"
31 source "board/emulation/Kconfig"
32 source "board/google/Kconfig"
33 source "board/intel/Kconfig"
35 # platform-specific options below
36 source "arch/x86/cpu/baytrail/Kconfig"
37 source "arch/x86/cpu/coreboot/Kconfig"
38 source "arch/x86/cpu/ivybridge/Kconfig"
39 source "arch/x86/cpu/qemu/Kconfig"
40 source "arch/x86/cpu/quark/Kconfig"
41 source "arch/x86/cpu/queensbay/Kconfig"
43 # architecture-specific options below
45 config SYS_MALLOC_F_LEN
54 depends on X86_RESET_VECTOR
63 default 0xfed00000 if !HPET_ADDRESS_OVERRIDE
72 config X86_RESET_VECTOR
76 config RESET_SEG_START
78 depends on X86_RESET_VECTOR
83 depends on X86_RESET_VECTOR
88 depends on X86_RESET_VECTOR
91 config SYS_X86_START16
93 depends on X86_RESET_VECTOR
96 config BOARD_ROMSIZE_KB_512
98 config BOARD_ROMSIZE_KB_1024
100 config BOARD_ROMSIZE_KB_2048
102 config BOARD_ROMSIZE_KB_4096
104 config BOARD_ROMSIZE_KB_8192
106 config BOARD_ROMSIZE_KB_16384
110 prompt "ROM chip size"
111 depends on X86_RESET_VECTOR
112 default UBOOT_ROMSIZE_KB_512 if BOARD_ROMSIZE_KB_512
113 default UBOOT_ROMSIZE_KB_1024 if BOARD_ROMSIZE_KB_1024
114 default UBOOT_ROMSIZE_KB_2048 if BOARD_ROMSIZE_KB_2048
115 default UBOOT_ROMSIZE_KB_4096 if BOARD_ROMSIZE_KB_4096
116 default UBOOT_ROMSIZE_KB_8192 if BOARD_ROMSIZE_KB_8192
117 default UBOOT_ROMSIZE_KB_16384 if BOARD_ROMSIZE_KB_16384
119 Select the size of the ROM chip you intend to flash U-Boot on.
121 The build system will take care of creating a u-boot.rom file
122 of the matching size.
124 config UBOOT_ROMSIZE_KB_512
127 Choose this option if you have a 512 KB ROM chip.
129 config UBOOT_ROMSIZE_KB_1024
130 bool "1024 KB (1 MB)"
132 Choose this option if you have a 1024 KB (1 MB) ROM chip.
134 config UBOOT_ROMSIZE_KB_2048
135 bool "2048 KB (2 MB)"
137 Choose this option if you have a 2048 KB (2 MB) ROM chip.
139 config UBOOT_ROMSIZE_KB_4096
140 bool "4096 KB (4 MB)"
142 Choose this option if you have a 4096 KB (4 MB) ROM chip.
144 config UBOOT_ROMSIZE_KB_8192
145 bool "8192 KB (8 MB)"
147 Choose this option if you have a 8192 KB (8 MB) ROM chip.
149 config UBOOT_ROMSIZE_KB_16384
150 bool "16384 KB (16 MB)"
152 Choose this option if you have a 16384 KB (16 MB) ROM chip.
156 # Map the config names to an integer (KB).
157 config UBOOT_ROMSIZE_KB
159 default 512 if UBOOT_ROMSIZE_KB_512
160 default 1024 if UBOOT_ROMSIZE_KB_1024
161 default 2048 if UBOOT_ROMSIZE_KB_2048
162 default 4096 if UBOOT_ROMSIZE_KB_4096
163 default 8192 if UBOOT_ROMSIZE_KB_8192
164 default 16384 if UBOOT_ROMSIZE_KB_16384
166 # Map the config names to a hex value (bytes).
169 default 0x80000 if UBOOT_ROMSIZE_KB_512
170 default 0x100000 if UBOOT_ROMSIZE_KB_1024
171 default 0x200000 if UBOOT_ROMSIZE_KB_2048
172 default 0x400000 if UBOOT_ROMSIZE_KB_4096
173 default 0x800000 if UBOOT_ROMSIZE_KB_8192
174 default 0xc00000 if UBOOT_ROMSIZE_KB_12288
175 default 0x1000000 if UBOOT_ROMSIZE_KB_16384
178 bool "Platform requires Intel Management Engine"
180 Newer higher-end devices have an Intel Management Engine (ME)
181 which is a very large binary blob (typically 1.5MB) which is
182 required for the platform to work. This enforces a particular
183 SPI flash format. You will need to supply the me.bin file in
184 your board directory.
187 bool "Perform a simple RAM test after SDRAM initialisation"
189 If there is something wrong with SDRAM then the platform will
190 often crash within U-Boot or the kernel. This option enables a
191 very simple RAM test that quickly checks whether the SDRAM seems
192 to work correctly. It is not exhaustive but can save time by
193 detecting obvious failures.
196 bool "Add an Firmware Support Package binary"
199 Select this option to add an Firmware Support Package binary to
200 the resulting U-Boot image. It is a binary blob which U-Boot uses
201 to set up SDRAM and other chipset specific initialization.
203 Note: Without this binary U-Boot will not be able to set up its
204 SDRAM so will not boot.
207 string "Firmware Support Package binary filename"
211 The filename of the file to use as Firmware Support Package binary
212 in the board directory.
215 hex "Firmware Support Package binary location"
219 FSP is not Position Independent Code (PIC) and the whole FSP has to
220 be rebased if it is placed at a location which is different from the
221 perferred base address specified during the FSP build. Use Intel's
222 Binary Configuration Tool (BCT) to do the rebase.
224 The default base address of 0xfffc0000 indicates that the binary must
225 be located at offset 0xc0000 from the beginning of a 1MB flash device.
227 config FSP_TEMP_RAM_ADDR
232 Stack top address which is used in fsp_init() after DRAM is ready and
235 config FSP_SYS_MALLOC_F_LEN
240 Additional size of malloc() pool before relocation.
247 Most FSPs use UPD data region for some FSP customization. But there
248 are still some FSPs that might not even have UPD. For such FSPs,
249 override this to n in their platform Kconfig files.
251 config FSP_BROKEN_HOB
255 Indicate some buggy FSPs that does not report memory used by FSP
256 itself as reserved in the resource descriptor HOB. Select this to
257 tell U-Boot to do some additional work to ensure U-Boot relocation
258 do not overwrite the important boot service data which is used by
259 FSP, otherwise the subsequent call to fsp_notify() will fail.
261 config ENABLE_MRC_CACHE
262 bool "Enable MRC cache"
263 depends on !EFI && !SYS_COREBOOT
265 Enable this feature to cause MRC data to be cached in NV storage
266 to be used for speeding up boot time on future reboots and/or
270 bool "Add a System Agent binary"
273 Select this option to add a System Agent binary to
274 the resulting U-Boot image. MRC stands for Memory Reference Code.
275 It is a binary blob which U-Boot uses to set up SDRAM.
277 Note: Without this binary U-Boot will not be able to set up its
278 SDRAM so will not boot.
285 Enable caching for the memory reference code binary. This uses an
286 MTRR (memory type range register) to turn on caching for the section
287 of SPI flash that contains the memory reference code. This makes
288 SDRAM init run faster.
290 config CACHE_MRC_SIZE_KB
295 Sets the size of the cached area for the memory reference code.
296 This ends at the end of SPI flash (address 0xffffffff) and is
297 measured in KB. Typically this is set to 512, providing for 0.5MB
300 config DCACHE_RAM_BASE
304 Sets the base of the data cache area in memory space. This is the
305 start address of the cache-as-RAM (CAR) area and the address varies
306 depending on the CPU. Once CAR is set up, read/write memory becomes
307 available at this address and can be used temporarily until SDRAM
310 config DCACHE_RAM_SIZE
315 Sets the total size of the data cache area in memory space. This
316 sets the size of the cache-as-RAM (CAR) area. Note that much of the
317 CAR space is required by the MRC. The CAR space available to U-Boot
318 is normally at the start and typically extends to 1/4 or 1/2 of the
321 config DCACHE_RAM_MRC_VAR_SIZE
325 This is the amount of CAR (Cache as RAM) reserved for use by the
326 memory reference code. This depends on the implementation of the
327 memory reference code and must be set correctly or the board will
331 bool "Add a Reference Code binary"
333 Select this option to add a Reference Code binary to the resulting
334 U-Boot image. This is an Intel binary blob that handles system
335 initialisation, in this case the PCH and System Agent.
337 Note: Without this binary (on platforms that need it such as
338 broadwell) U-Boot will be missing some critical setup steps.
339 Various peripherals may fail to work.
342 bool "Enable Symmetric Multiprocessing"
345 Enable use of more than one CPU in U-Boot and the Operating System
346 when loaded. Each CPU will be started up and information can be
347 obtained using the 'cpu' command. If this option is disabled, then
348 only one CPU will be enabled regardless of the number of CPUs
352 int "Maximum number of CPUs permitted"
356 When using multi-CPU chips it is possible for U-Boot to start up
357 more than one CPU. The stack memory used by all of these CPUs is
358 pre-allocated so at present U-Boot wants to know the maximum
359 number of CPUs that may be present. Set this to at least as high
360 as the number of CPUs in your system (it uses about 4KB of RAM for
368 Each additional CPU started by U-Boot requires its own stack. This
369 option sets the stack size used by each CPU and directly affects
370 the memory used by this initialisation process. Typically 4KB is
374 bool "Add a VGA BIOS image"
376 Select this option if you have a VGA BIOS image that you would
377 like to add to your ROM.
380 string "VGA BIOS image filename"
381 depends on HAVE_VGA_BIOS
384 The filename of the VGA BIOS image in the board directory.
387 hex "VGA BIOS image location"
388 depends on HAVE_VGA_BIOS
391 The location of VGA BIOS image in the SPI flash. For example, base
392 address of 0xfff90000 indicates that the image will be put at offset
393 0x90000 from the beginning of a 1MB flash device.
396 depends on !EFI && !SYS_COREBOOT
398 config GENERATE_PIRQ_TABLE
399 bool "Generate a PIRQ table"
402 Generate a PIRQ routing table for this board. The PIRQ routing table
403 is generated by U-Boot in the system memory from 0xf0000 to 0xfffff
404 at every 16-byte boundary with a PCI IRQ routing signature ("$PIR").
405 It specifies the interrupt router information as well how all the PCI
406 devices' interrupt pins are wired to PIRQs.
408 config GENERATE_SFI_TABLE
409 bool "Generate a SFI (Simple Firmware Interface) table"
411 The Simple Firmware Interface (SFI) provides a lightweight method
412 for platform firmware to pass information to the operating system
413 via static tables in memory. Kernel SFI support is required to
414 boot on SFI-only platforms. If you have ACPI tables then these are
417 U-Boot writes this table in write_sfi_table() just before booting
420 For more information, see http://simplefirmware.org
422 config GENERATE_MP_TABLE
423 bool "Generate an MP (Multi-Processor) table"
426 Generate an MP (Multi-Processor) table for this board. The MP table
427 provides a way for the operating system to support for symmetric
428 multiprocessing as well as symmetric I/O interrupt handling with
429 the local APIC and I/O APIC.
431 config GENERATE_ACPI_TABLE
432 bool "Generate an ACPI (Advanced Configuration and Power Interface) table"
435 The Advanced Configuration and Power Interface (ACPI) specification
436 provides an open standard for device configuration and management
437 by the operating system. It defines platform-independent interfaces
438 for configuration and power management monitoring.
440 config QEMU_ACPI_TABLE
441 bool "Load ACPI table from QEMU fw_cfg interface"
442 depends on GENERATE_ACPI_TABLE && QEMU
445 By default, U-Boot generates its own ACPI tables. This option, if
446 enabled, disables U-Boot's version and loads ACPI tables generated
449 config GENERATE_SMBIOS_TABLE
450 bool "Generate an SMBIOS (System Management BIOS) table"
453 The System Management BIOS (SMBIOS) specification addresses how
454 motherboard and system vendors present management information about
455 their products in a standard format by extending the BIOS interface
456 on Intel architecture systems.
458 Check http://www.dmtf.org/standards/smbios for details.
462 config MAX_PIRQ_LINKS
466 This variable specifies the number of PIRQ interrupt links which are
467 routable. On most older chipsets, this is 4, PIRQA through PIRQD.
468 Some newer chipsets offer more than four links, commonly up to PIRQH.
470 config IRQ_SLOT_COUNT
474 U-Boot can support up to 254 IRQ slot info in the PIRQ routing table
475 which in turns forms a table of exact 4KiB. The default value 128
476 should be enough for most boards. If this does not fit your board,
477 change it according to your needs.
479 config PCIE_ECAM_BASE
483 This is the memory-mapped address of PCI configuration space, which
484 is only available through the Enhanced Configuration Access
485 Mechanism (ECAM) with PCI Express. It can be set up almost
486 anywhere. Before it is set up, it is possible to access PCI
487 configuration space through I/O access, but memory access is more
488 convenient. Using this, PCI can be scanned and configured. This
489 should be set to a region that does not conflict with memory
490 assigned to PCI devices - i.e. the memory and prefetch regions, as
491 passed to pci_set_region().
493 config PCIE_ECAM_SIZE
497 This is the size of memory-mapped address of PCI configuration space,
498 which is only available through the Enhanced Configuration Access
499 Mechanism (ECAM) with PCI Express. Each bus consumes 1 MiB memory,
500 so a default 0x10000000 size covers all of the 256 buses which is the
501 maximum number of PCI buses as defined by the PCI specification.
507 Intel 8259 ISA compatible chipset incorporates two 8259 (master and
508 slave) interrupt controllers. Include this to have U-Boot set up
509 the interrupt correctly.
515 Intel 8254 timer contains three counters which have fixed uses.
516 Include this to have U-Boot set up the timer correctly.
525 bool "Support booting SeaBIOS"
527 SeaBIOS is an open source implementation of a 16-bit X86 BIOS.
528 It can run in an emulator or natively on X86 hardware with the use
529 of coreboot/U-Boot. By turning on this option, U-Boot prepares
530 all the configuration tables that are necessary to boot SeaBIOS.
532 Check http://www.seabios.org/SeaBIOS for details.
534 source "arch/x86/lib/efi/Kconfig"