1 menu "x86 architecture"
7 config USE_PRIVATE_LIBGCC
14 prompt "Mainboard vendor"
15 default VENDOR_COREBOOT
17 config VENDOR_COREBOOT
28 # board-specific options below
29 source "board/coreboot/Kconfig"
30 source "board/google/Kconfig"
31 source "board/intel/Kconfig"
33 # platform-specific options below
34 source "arch/x86/cpu/baytrail/Kconfig"
35 source "arch/x86/cpu/coreboot/Kconfig"
36 source "arch/x86/cpu/ivybridge/Kconfig"
37 source "arch/x86/cpu/quark/Kconfig"
38 source "arch/x86/cpu/queensbay/Kconfig"
40 # architecture-specific options below
42 config SYS_MALLOC_F_LEN
51 depends on X86_RESET_VECTOR
60 default 0xfed00000 if !HPET_ADDRESS_OVERRIDE
69 config X86_RESET_VECTOR
73 config SYS_X86_START16
75 depends on X86_RESET_VECTOR
78 config BOARD_ROMSIZE_KB_512
80 config BOARD_ROMSIZE_KB_1024
82 config BOARD_ROMSIZE_KB_2048
84 config BOARD_ROMSIZE_KB_4096
86 config BOARD_ROMSIZE_KB_8192
88 config BOARD_ROMSIZE_KB_16384
92 prompt "ROM chip size"
93 depends on X86_RESET_VECTOR
94 default UBOOT_ROMSIZE_KB_512 if BOARD_ROMSIZE_KB_512
95 default UBOOT_ROMSIZE_KB_1024 if BOARD_ROMSIZE_KB_1024
96 default UBOOT_ROMSIZE_KB_2048 if BOARD_ROMSIZE_KB_2048
97 default UBOOT_ROMSIZE_KB_4096 if BOARD_ROMSIZE_KB_4096
98 default UBOOT_ROMSIZE_KB_8192 if BOARD_ROMSIZE_KB_8192
99 default UBOOT_ROMSIZE_KB_16384 if BOARD_ROMSIZE_KB_16384
101 Select the size of the ROM chip you intend to flash U-Boot on.
103 The build system will take care of creating a u-boot.rom file
104 of the matching size.
106 config UBOOT_ROMSIZE_KB_512
109 Choose this option if you have a 512 KB ROM chip.
111 config UBOOT_ROMSIZE_KB_1024
112 bool "1024 KB (1 MB)"
114 Choose this option if you have a 1024 KB (1 MB) ROM chip.
116 config UBOOT_ROMSIZE_KB_2048
117 bool "2048 KB (2 MB)"
119 Choose this option if you have a 2048 KB (2 MB) ROM chip.
121 config UBOOT_ROMSIZE_KB_4096
122 bool "4096 KB (4 MB)"
124 Choose this option if you have a 4096 KB (4 MB) ROM chip.
126 config UBOOT_ROMSIZE_KB_8192
127 bool "8192 KB (8 MB)"
129 Choose this option if you have a 8192 KB (8 MB) ROM chip.
131 config UBOOT_ROMSIZE_KB_16384
132 bool "16384 KB (16 MB)"
134 Choose this option if you have a 16384 KB (16 MB) ROM chip.
138 # Map the config names to an integer (KB).
139 config UBOOT_ROMSIZE_KB
141 default 512 if UBOOT_ROMSIZE_KB_512
142 default 1024 if UBOOT_ROMSIZE_KB_1024
143 default 2048 if UBOOT_ROMSIZE_KB_2048
144 default 4096 if UBOOT_ROMSIZE_KB_4096
145 default 8192 if UBOOT_ROMSIZE_KB_8192
146 default 16384 if UBOOT_ROMSIZE_KB_16384
148 # Map the config names to a hex value (bytes).
151 default 0x80000 if UBOOT_ROMSIZE_KB_512
152 default 0x100000 if UBOOT_ROMSIZE_KB_1024
153 default 0x200000 if UBOOT_ROMSIZE_KB_2048
154 default 0x400000 if UBOOT_ROMSIZE_KB_4096
155 default 0x800000 if UBOOT_ROMSIZE_KB_8192
156 default 0xc00000 if UBOOT_ROMSIZE_KB_12288
157 default 0x1000000 if UBOOT_ROMSIZE_KB_16384
160 bool "Platform requires Intel Management Engine"
162 Newer higher-end devices have an Intel Management Engine (ME)
163 which is a very large binary blob (typically 1.5MB) which is
164 required for the platform to work. This enforces a particular
165 SPI flash format. You will need to supply the me.bin file in
166 your board directory.
169 bool "Perform a simple RAM test after SDRAM initialisation"
171 If there is something wrong with SDRAM then the platform will
172 often crash within U-Boot or the kernel. This option enables a
173 very simple RAM test that quickly checks whether the SDRAM seems
174 to work correctly. It is not exhaustive but can save time by
175 detecting obvious failures.
177 config MARK_GRAPHICS_MEM_WRCOMB
178 bool "Mark graphics memory as write-combining"
181 The graphics performance may increase if the graphics
182 memory is set as write-combining cache type. This option
183 enables marking the graphics memory as write-combining.
187 config FRAMEBUFFER_SET_VESA_MODE
188 prompt "Set framebuffer graphics resolution"
191 Set VESA/native framebuffer mode (needed for bootsplash and graphical framebuffer console)
194 prompt "framebuffer graphics resolution"
195 default FRAMEBUFFER_VESA_MODE_117
196 depends on FRAMEBUFFER_SET_VESA_MODE
198 This option sets the resolution used for the coreboot framebuffer (and
201 config FRAMEBUFFER_VESA_MODE_100
202 bool "640x400 256-color"
204 config FRAMEBUFFER_VESA_MODE_101
205 bool "640x480 256-color"
207 config FRAMEBUFFER_VESA_MODE_102
208 bool "800x600 16-color"
210 config FRAMEBUFFER_VESA_MODE_103
211 bool "800x600 256-color"
213 config FRAMEBUFFER_VESA_MODE_104
214 bool "1024x768 16-color"
216 config FRAMEBUFFER_VESA_MODE_105
217 bool "1024x7686 256-color"
219 config FRAMEBUFFER_VESA_MODE_106
220 bool "1280x1024 16-color"
222 config FRAMEBUFFER_VESA_MODE_107
223 bool "1280x1024 256-color"
225 config FRAMEBUFFER_VESA_MODE_108
228 config FRAMEBUFFER_VESA_MODE_109
231 config FRAMEBUFFER_VESA_MODE_10A
234 config FRAMEBUFFER_VESA_MODE_10B
237 config FRAMEBUFFER_VESA_MODE_10C
240 config FRAMEBUFFER_VESA_MODE_10D
241 bool "320x200 32k-color (1:5:5:5)"
243 config FRAMEBUFFER_VESA_MODE_10E
244 bool "320x200 64k-color (5:6:5)"
246 config FRAMEBUFFER_VESA_MODE_10F
247 bool "320x200 16.8M-color (8:8:8)"
249 config FRAMEBUFFER_VESA_MODE_110
250 bool "640x480 32k-color (1:5:5:5)"
252 config FRAMEBUFFER_VESA_MODE_111
253 bool "640x480 64k-color (5:6:5)"
255 config FRAMEBUFFER_VESA_MODE_112
256 bool "640x480 16.8M-color (8:8:8)"
258 config FRAMEBUFFER_VESA_MODE_113
259 bool "800x600 32k-color (1:5:5:5)"
261 config FRAMEBUFFER_VESA_MODE_114
262 bool "800x600 64k-color (5:6:5)"
264 config FRAMEBUFFER_VESA_MODE_115
265 bool "800x600 16.8M-color (8:8:8)"
267 config FRAMEBUFFER_VESA_MODE_116
268 bool "1024x768 32k-color (1:5:5:5)"
270 config FRAMEBUFFER_VESA_MODE_117
271 bool "1024x768 64k-color (5:6:5)"
273 config FRAMEBUFFER_VESA_MODE_118
274 bool "1024x768 16.8M-color (8:8:8)"
276 config FRAMEBUFFER_VESA_MODE_119
277 bool "1280x1024 32k-color (1:5:5:5)"
279 config FRAMEBUFFER_VESA_MODE_11A
280 bool "1280x1024 64k-color (5:6:5)"
282 config FRAMEBUFFER_VESA_MODE_11B
283 bool "1280x1024 16.8M-color (8:8:8)"
285 config FRAMEBUFFER_VESA_MODE_USER
286 bool "Manually select VESA mode"
290 # Map the config names to an integer (KB).
291 config FRAMEBUFFER_VESA_MODE
292 prompt "VESA mode" if FRAMEBUFFER_VESA_MODE_USER
294 default 0x100 if FRAMEBUFFER_VESA_MODE_100
295 default 0x101 if FRAMEBUFFER_VESA_MODE_101
296 default 0x102 if FRAMEBUFFER_VESA_MODE_102
297 default 0x103 if FRAMEBUFFER_VESA_MODE_103
298 default 0x104 if FRAMEBUFFER_VESA_MODE_104
299 default 0x105 if FRAMEBUFFER_VESA_MODE_105
300 default 0x106 if FRAMEBUFFER_VESA_MODE_106
301 default 0x107 if FRAMEBUFFER_VESA_MODE_107
302 default 0x108 if FRAMEBUFFER_VESA_MODE_108
303 default 0x109 if FRAMEBUFFER_VESA_MODE_109
304 default 0x10A if FRAMEBUFFER_VESA_MODE_10A
305 default 0x10B if FRAMEBUFFER_VESA_MODE_10B
306 default 0x10C if FRAMEBUFFER_VESA_MODE_10C
307 default 0x10D if FRAMEBUFFER_VESA_MODE_10D
308 default 0x10E if FRAMEBUFFER_VESA_MODE_10E
309 default 0x10F if FRAMEBUFFER_VESA_MODE_10F
310 default 0x110 if FRAMEBUFFER_VESA_MODE_110
311 default 0x111 if FRAMEBUFFER_VESA_MODE_111
312 default 0x112 if FRAMEBUFFER_VESA_MODE_112
313 default 0x113 if FRAMEBUFFER_VESA_MODE_113
314 default 0x114 if FRAMEBUFFER_VESA_MODE_114
315 default 0x115 if FRAMEBUFFER_VESA_MODE_115
316 default 0x116 if FRAMEBUFFER_VESA_MODE_116
317 default 0x117 if FRAMEBUFFER_VESA_MODE_117
318 default 0x118 if FRAMEBUFFER_VESA_MODE_118
319 default 0x119 if FRAMEBUFFER_VESA_MODE_119
320 default 0x11A if FRAMEBUFFER_VESA_MODE_11A
321 default 0x11B if FRAMEBUFFER_VESA_MODE_11B
322 default 0x117 if FRAMEBUFFER_VESA_MODE_USER
327 bool "Add an Firmware Support Package binary"
329 Select this option to add an Firmware Support Package binary to
330 the resulting U-Boot image. It is a binary blob which U-Boot uses
331 to set up SDRAM and other chipset specific initialization.
333 Note: Without this binary U-Boot will not be able to set up its
334 SDRAM so will not boot.
337 string "Firmware Support Package binary filename"
341 The filename of the file to use as Firmware Support Package binary
342 in the board directory.
345 hex "Firmware Support Package binary location"
349 FSP is not Position Independent Code (PIC) and the whole FSP has to
350 be rebased if it is placed at a location which is different from the
351 perferred base address specified during the FSP build. Use Intel's
352 Binary Configuration Tool (BCT) to do the rebase.
354 The default base address of 0xfffc0000 indicates that the binary must
355 be located at offset 0xc0000 from the beginning of a 1MB flash device.
357 config FSP_TEMP_RAM_ADDR
361 Stack top address which is used in FspInit after DRAM is ready and
364 config TSC_CALIBRATION_BYPASS
365 bool "Bypass Time-Stamp Counter (TSC) calibration"
368 By default U-Boot automatically calibrates Time-Stamp Counter (TSC)
369 running frequency via Model-Specific Register (MSR) and Programmable
370 Interval Timer (PIT). If the calibration does not work on your board,
371 select this option and provide a hardcoded TSC running frequency with
372 CONFIG_TSC_FREQ_IN_MHZ below.
374 Normally this option should be turned on in a simulation environment
377 config TSC_FREQ_IN_MHZ
378 int "Time-Stamp Counter (TSC) running frequency in MHz"
379 depends on TSC_CALIBRATION_BYPASS
382 The running frequency in MHz of Time-Stamp Counter (TSC).
386 config GENERATE_PIRQ_TABLE
387 bool "Generate a PIRQ table"
390 Generate a PIRQ routing table for this board. The PIRQ routing table
391 is generated by U-Boot in the system memory from 0xf0000 to 0xfffff
392 at every 16-byte boundary with a PCI IRQ routing signature ("$PIR").
393 It specifies the interrupt router information as well how all the PCI
394 devices' interrupt pins are wired to PIRQs.
396 config GENERATE_SFI_TABLE
397 bool "Generate a SFI (Simple Firmware Interface) table"
399 The Simple Firmware Interface (SFI) provides a lightweight method
400 for platform firmware to pass information to the operating system
401 via static tables in memory. Kernel SFI support is required to
402 boot on SFI-only platforms. If you have ACPI tables then these are
405 U-Boot writes this table in write_sfi_table() just before booting
408 For more information, see http://simplefirmware.org
412 config MAX_PIRQ_LINKS
416 This variable specifies the number of PIRQ interrupt links which are
417 routable. On most older chipsets, this is 4, PIRQA through PIRQD.
418 Some newer chipsets offer more than four links, commonly up to PIRQH.
420 config IRQ_SLOT_COUNT
424 U-Boot can support up to 254 IRQ slot info in the PIRQ routing table
425 which in turns forms a table of exact 4KiB. The default value 128
426 should be enough for most boards. If this does not fit your board,
427 change it according to your needs.
429 config PCIE_ECAM_BASE
433 This is the memory-mapped address of PCI configuration space, which
434 is only available through the Enhanced Configuration Access
435 Mechanism (ECAM) with PCI Express. It can be set up almost
436 anywhere. Before it is set up, it is possible to access PCI
437 configuration space through I/O access, but memory access is more
438 convenient. Using this, PCI can be scanned and configured. This
439 should be set to a region that does not conflict with memory
440 assigned to PCI devices - i.e. the memory and prefetch regions, as
441 passed to pci_set_region().
446 config BOOTSTAGE_REPORT