1 menu "x86 architecture"
8 prompt "Run U-Boot in 32/64-bit mode"
11 U-Boot can be built as a 32-bit binary which runs in 32-bit mode
12 even on 64-bit machines. In this case SPL is not used, and U-Boot
13 runs directly from the reset vector (via 16-bit start-up).
15 Alternatively it can be run as a 64-bit binary, thus requiring a
16 64-bit machine. In this case SPL runs in 32-bit mode (via 16-bit
17 start-up) then jumps to U-Boot in 64-bit mode.
19 For now, 32-bit mode is recommended, as 64-bit is still
20 experimental and is missing a lot of features.
25 Build U-Boot as a 32-bit binary with no SPL. This is the currently
26 supported normal setup. U-Boot will stay in 32-bit mode even on
27 64-bit machines. When booting a 64-bit kernel, U-Boot will switch
28 to 64-bit just before starting the kernel. Only the bottom 4GB of
29 memory can be accessed through normal means, although
30 arch_phys_memset() can be used for basic access to other memory.
37 select SPL_SEPARATE_BSS
39 Build U-Boot as a 64-bit binary with a 32-bit SPL. This is
40 experimental and many features are missing. U-Boot SPL starts up,
41 runs through the 16-bit and 32-bit init, then switches to 64-bit
42 mode and jumps to U-Boot proper.
54 prompt "Mainboard vendor"
55 default VENDOR_EMULATION
57 config VENDOR_ADVANTECH
60 config VENDOR_CONGATEC
63 config VENDOR_COREBOOT
72 config VENDOR_EMULATION
83 # board-specific options below
84 source "board/advantech/Kconfig"
85 source "board/congatec/Kconfig"
86 source "board/coreboot/Kconfig"
87 source "board/dfi/Kconfig"
88 source "board/efi/Kconfig"
89 source "board/emulation/Kconfig"
90 source "board/google/Kconfig"
91 source "board/intel/Kconfig"
93 # platform-specific options below
94 source "arch/x86/cpu/baytrail/Kconfig"
95 source "arch/x86/cpu/broadwell/Kconfig"
96 source "arch/x86/cpu/coreboot/Kconfig"
97 source "arch/x86/cpu/ivybridge/Kconfig"
98 source "arch/x86/cpu/qemu/Kconfig"
99 source "arch/x86/cpu/quark/Kconfig"
100 source "arch/x86/cpu/queensbay/Kconfig"
102 # architecture-specific options below
107 config SYS_MALLOC_F_LEN
116 depends on X86_RESET_VECTOR
125 default 0xfed00000 if !HPET_ADDRESS_OVERRIDE
134 config X86_RESET_VECTOR
138 config RESET_SEG_START
140 depends on X86_RESET_VECTOR
143 config RESET_SEG_SIZE
145 depends on X86_RESET_VECTOR
150 depends on X86_RESET_VECTOR
153 config SYS_X86_START16
155 depends on X86_RESET_VECTOR
158 config BOARD_ROMSIZE_KB_512
160 config BOARD_ROMSIZE_KB_1024
162 config BOARD_ROMSIZE_KB_2048
164 config BOARD_ROMSIZE_KB_4096
166 config BOARD_ROMSIZE_KB_8192
168 config BOARD_ROMSIZE_KB_16384
172 prompt "ROM chip size"
173 depends on X86_RESET_VECTOR
174 default UBOOT_ROMSIZE_KB_512 if BOARD_ROMSIZE_KB_512
175 default UBOOT_ROMSIZE_KB_1024 if BOARD_ROMSIZE_KB_1024
176 default UBOOT_ROMSIZE_KB_2048 if BOARD_ROMSIZE_KB_2048
177 default UBOOT_ROMSIZE_KB_4096 if BOARD_ROMSIZE_KB_4096
178 default UBOOT_ROMSIZE_KB_8192 if BOARD_ROMSIZE_KB_8192
179 default UBOOT_ROMSIZE_KB_16384 if BOARD_ROMSIZE_KB_16384
181 Select the size of the ROM chip you intend to flash U-Boot on.
183 The build system will take care of creating a u-boot.rom file
184 of the matching size.
186 config UBOOT_ROMSIZE_KB_512
189 Choose this option if you have a 512 KB ROM chip.
191 config UBOOT_ROMSIZE_KB_1024
192 bool "1024 KB (1 MB)"
194 Choose this option if you have a 1024 KB (1 MB) ROM chip.
196 config UBOOT_ROMSIZE_KB_2048
197 bool "2048 KB (2 MB)"
199 Choose this option if you have a 2048 KB (2 MB) ROM chip.
201 config UBOOT_ROMSIZE_KB_4096
202 bool "4096 KB (4 MB)"
204 Choose this option if you have a 4096 KB (4 MB) ROM chip.
206 config UBOOT_ROMSIZE_KB_8192
207 bool "8192 KB (8 MB)"
209 Choose this option if you have a 8192 KB (8 MB) ROM chip.
211 config UBOOT_ROMSIZE_KB_16384
212 bool "16384 KB (16 MB)"
214 Choose this option if you have a 16384 KB (16 MB) ROM chip.
218 # Map the config names to an integer (KB).
219 config UBOOT_ROMSIZE_KB
221 default 512 if UBOOT_ROMSIZE_KB_512
222 default 1024 if UBOOT_ROMSIZE_KB_1024
223 default 2048 if UBOOT_ROMSIZE_KB_2048
224 default 4096 if UBOOT_ROMSIZE_KB_4096
225 default 8192 if UBOOT_ROMSIZE_KB_8192
226 default 16384 if UBOOT_ROMSIZE_KB_16384
228 # Map the config names to a hex value (bytes).
231 default 0x80000 if UBOOT_ROMSIZE_KB_512
232 default 0x100000 if UBOOT_ROMSIZE_KB_1024
233 default 0x200000 if UBOOT_ROMSIZE_KB_2048
234 default 0x400000 if UBOOT_ROMSIZE_KB_4096
235 default 0x800000 if UBOOT_ROMSIZE_KB_8192
236 default 0xc00000 if UBOOT_ROMSIZE_KB_12288
237 default 0x1000000 if UBOOT_ROMSIZE_KB_16384
240 bool "Platform requires Intel Management Engine"
242 Newer higher-end devices have an Intel Management Engine (ME)
243 which is a very large binary blob (typically 1.5MB) which is
244 required for the platform to work. This enforces a particular
245 SPI flash format. You will need to supply the me.bin file in
246 your board directory.
249 bool "Perform a simple RAM test after SDRAM initialisation"
251 If there is something wrong with SDRAM then the platform will
252 often crash within U-Boot or the kernel. This option enables a
253 very simple RAM test that quickly checks whether the SDRAM seems
254 to work correctly. It is not exhaustive but can save time by
255 detecting obvious failures.
258 bool "Add an Firmware Support Package binary"
261 Select this option to add an Firmware Support Package binary to
262 the resulting U-Boot image. It is a binary blob which U-Boot uses
263 to set up SDRAM and other chipset specific initialization.
265 Note: Without this binary U-Boot will not be able to set up its
266 SDRAM so will not boot.
269 string "Firmware Support Package binary filename"
273 The filename of the file to use as Firmware Support Package binary
274 in the board directory.
277 hex "Firmware Support Package binary location"
281 FSP is not Position Independent Code (PIC) and the whole FSP has to
282 be rebased if it is placed at a location which is different from the
283 perferred base address specified during the FSP build. Use Intel's
284 Binary Configuration Tool (BCT) to do the rebase.
286 The default base address of 0xfffc0000 indicates that the binary must
287 be located at offset 0xc0000 from the beginning of a 1MB flash device.
289 config FSP_TEMP_RAM_ADDR
294 Stack top address which is used in fsp_init() after DRAM is ready and
297 config FSP_SYS_MALLOC_F_LEN
302 Additional size of malloc() pool before relocation.
309 Most FSPs use UPD data region for some FSP customization. But there
310 are still some FSPs that might not even have UPD. For such FSPs,
311 override this to n in their platform Kconfig files.
313 config FSP_BROKEN_HOB
317 Indicate some buggy FSPs that does not report memory used by FSP
318 itself as reserved in the resource descriptor HOB. Select this to
319 tell U-Boot to do some additional work to ensure U-Boot relocation
320 do not overwrite the important boot service data which is used by
321 FSP, otherwise the subsequent call to fsp_notify() will fail.
323 config ENABLE_MRC_CACHE
324 bool "Enable MRC cache"
325 depends on !EFI && !SYS_COREBOOT
327 Enable this feature to cause MRC data to be cached in NV storage
328 to be used for speeding up boot time on future reboots and/or
331 For platforms that use Intel FSP for the memory initialization,
332 please check FSP output HOB via U-Boot command 'fsp hob' to see
333 if there is FSP_NON_VOLATILE_STORAGE_HOB_GUID (asm/fsp/fsp_hob.h).
334 If such GUID does not exist, MRC cache is not avaiable on such
335 platform (eg: Intel Queensbay), which means selecting this option
336 here does not make any difference.
339 bool "Add a System Agent binary"
342 Select this option to add a System Agent binary to
343 the resulting U-Boot image. MRC stands for Memory Reference Code.
344 It is a binary blob which U-Boot uses to set up SDRAM.
346 Note: Without this binary U-Boot will not be able to set up its
347 SDRAM so will not boot.
354 Enable caching for the memory reference code binary. This uses an
355 MTRR (memory type range register) to turn on caching for the section
356 of SPI flash that contains the memory reference code. This makes
357 SDRAM init run faster.
359 config CACHE_MRC_SIZE_KB
364 Sets the size of the cached area for the memory reference code.
365 This ends at the end of SPI flash (address 0xffffffff) and is
366 measured in KB. Typically this is set to 512, providing for 0.5MB
369 config DCACHE_RAM_BASE
373 Sets the base of the data cache area in memory space. This is the
374 start address of the cache-as-RAM (CAR) area and the address varies
375 depending on the CPU. Once CAR is set up, read/write memory becomes
376 available at this address and can be used temporarily until SDRAM
379 config DCACHE_RAM_SIZE
384 Sets the total size of the data cache area in memory space. This
385 sets the size of the cache-as-RAM (CAR) area. Note that much of the
386 CAR space is required by the MRC. The CAR space available to U-Boot
387 is normally at the start and typically extends to 1/4 or 1/2 of the
390 config DCACHE_RAM_MRC_VAR_SIZE
394 This is the amount of CAR (Cache as RAM) reserved for use by the
395 memory reference code. This depends on the implementation of the
396 memory reference code and must be set correctly or the board will
400 bool "Add a Reference Code binary"
402 Select this option to add a Reference Code binary to the resulting
403 U-Boot image. This is an Intel binary blob that handles system
404 initialisation, in this case the PCH and System Agent.
406 Note: Without this binary (on platforms that need it such as
407 broadwell) U-Boot will be missing some critical setup steps.
408 Various peripherals may fail to work.
411 bool "Enable Symmetric Multiprocessing"
414 Enable use of more than one CPU in U-Boot and the Operating System
415 when loaded. Each CPU will be started up and information can be
416 obtained using the 'cpu' command. If this option is disabled, then
417 only one CPU will be enabled regardless of the number of CPUs
421 int "Maximum number of CPUs permitted"
425 When using multi-CPU chips it is possible for U-Boot to start up
426 more than one CPU. The stack memory used by all of these CPUs is
427 pre-allocated so at present U-Boot wants to know the maximum
428 number of CPUs that may be present. Set this to at least as high
429 as the number of CPUs in your system (it uses about 4KB of RAM for
437 Each additional CPU started by U-Boot requires its own stack. This
438 option sets the stack size used by each CPU and directly affects
439 the memory used by this initialisation process. Typically 4KB is
443 bool "Add a VGA BIOS image"
445 Select this option if you have a VGA BIOS image that you would
446 like to add to your ROM.
449 string "VGA BIOS image filename"
450 depends on HAVE_VGA_BIOS
453 The filename of the VGA BIOS image in the board directory.
456 hex "VGA BIOS image location"
457 depends on HAVE_VGA_BIOS
460 The location of VGA BIOS image in the SPI flash. For example, base
461 address of 0xfff90000 indicates that the image will be put at offset
462 0x90000 from the beginning of a 1MB flash device.
465 depends on !EFI && !SYS_COREBOOT
467 config GENERATE_PIRQ_TABLE
468 bool "Generate a PIRQ table"
471 Generate a PIRQ routing table for this board. The PIRQ routing table
472 is generated by U-Boot in the system memory from 0xf0000 to 0xfffff
473 at every 16-byte boundary with a PCI IRQ routing signature ("$PIR").
474 It specifies the interrupt router information as well how all the PCI
475 devices' interrupt pins are wired to PIRQs.
477 config GENERATE_SFI_TABLE
478 bool "Generate a SFI (Simple Firmware Interface) table"
480 The Simple Firmware Interface (SFI) provides a lightweight method
481 for platform firmware to pass information to the operating system
482 via static tables in memory. Kernel SFI support is required to
483 boot on SFI-only platforms. If you have ACPI tables then these are
486 U-Boot writes this table in write_sfi_table() just before booting
489 For more information, see http://simplefirmware.org
491 config GENERATE_MP_TABLE
492 bool "Generate an MP (Multi-Processor) table"
495 Generate an MP (Multi-Processor) table for this board. The MP table
496 provides a way for the operating system to support for symmetric
497 multiprocessing as well as symmetric I/O interrupt handling with
498 the local APIC and I/O APIC.
500 config GENERATE_ACPI_TABLE
501 bool "Generate an ACPI (Advanced Configuration and Power Interface) table"
505 The Advanced Configuration and Power Interface (ACPI) specification
506 provides an open standard for device configuration and management
507 by the operating system. It defines platform-independent interfaces
508 for configuration and power management monitoring.
512 config MAX_PIRQ_LINKS
516 This variable specifies the number of PIRQ interrupt links which are
517 routable. On most older chipsets, this is 4, PIRQA through PIRQD.
518 Some newer chipsets offer more than four links, commonly up to PIRQH.
520 config IRQ_SLOT_COUNT
524 U-Boot can support up to 254 IRQ slot info in the PIRQ routing table
525 which in turns forms a table of exact 4KiB. The default value 128
526 should be enough for most boards. If this does not fit your board,
527 change it according to your needs.
529 config PCIE_ECAM_BASE
533 This is the memory-mapped address of PCI configuration space, which
534 is only available through the Enhanced Configuration Access
535 Mechanism (ECAM) with PCI Express. It can be set up almost
536 anywhere. Before it is set up, it is possible to access PCI
537 configuration space through I/O access, but memory access is more
538 convenient. Using this, PCI can be scanned and configured. This
539 should be set to a region that does not conflict with memory
540 assigned to PCI devices - i.e. the memory and prefetch regions, as
541 passed to pci_set_region().
543 config PCIE_ECAM_SIZE
547 This is the size of memory-mapped address of PCI configuration space,
548 which is only available through the Enhanced Configuration Access
549 Mechanism (ECAM) with PCI Express. Each bus consumes 1 MiB memory,
550 so a default 0x10000000 size covers all of the 256 buses which is the
551 maximum number of PCI buses as defined by the PCI specification.
557 Intel 8259 ISA compatible chipset incorporates two 8259 (master and
558 slave) interrupt controllers. Include this to have U-Boot set up
559 the interrupt correctly.
565 Intel 8254 timer contains three counters which have fixed uses.
566 Include this to have U-Boot set up the timer correctly.
569 bool "Support booting SeaBIOS"
571 SeaBIOS is an open source implementation of a 16-bit X86 BIOS.
572 It can run in an emulator or natively on X86 hardware with the use
573 of coreboot/U-Boot. By turning on this option, U-Boot prepares
574 all the configuration tables that are necessary to boot SeaBIOS.
576 Check http://www.seabios.org/SeaBIOS for details.
578 config HIGH_TABLE_SIZE
579 hex "Size of configuration tables which reside in high memory"
583 SeaBIOS itself resides in E seg and F seg, where U-Boot puts all
584 configuration tables like PIRQ/MP/ACPI. To avoid conflicts, U-Boot
585 puts a copy of configuration tables in high memory region which
586 is reserved on the stack before relocation. The region size is
587 determined by this option.
589 Increse it if the default size does not fit the board's needs.
590 This is most likely due to a large ACPI DSDT table is used.
592 source "arch/x86/lib/efi/Kconfig"