1 menu "x86 architecture"
7 config USE_PRIVATE_LIBGCC
11 prompt "Target select"
13 config TARGET_COREBOOT
14 bool "Support coreboot"
16 This target is used for running U-Boot on top of Coreboot. In
17 this case Coreboot does the early inititalisation, and U-Boot
18 takes over once the RAM, video and CPU are fully running.
19 U-Boot is loaded as a fallback payload from Coreboot, in
20 Coreboot terminology. This method was used for the Chromebook
23 config TARGET_CHROMEBOOK_LINK
24 bool "Support Chromebook link"
26 This is the Chromebook Pixel released in 2013. It uses an Intel
27 i5 Ivybridge which is a die-shrink of Sandybridge, with 4GB of
28 SDRAM. It has a Panther Point platform controller hub, PCIe
29 WiFi and Bluetooth. It also includes a 720p webcam, USB SD
30 reader, microphone and speakers, display port and 32GB SATA
31 solid state drive. There is a Chrome OS EC connected on LPC,
32 and it provides a 2560x1700 high resolution touch-enabled LCD
35 config TARGET_CHROMEBOX_PANTHER
36 bool "Support Chromebox panther (not available)"
39 Note: At present this must be used with Coreboot. See README.x86
42 This is the Asus Chromebox CN60 released in 2014. It uses an Intel
43 Haswell Celeron 2955U Dual Core CPU with 2GB of SDRAM. It has a
44 Lynx Point platform controller hub, PCIe WiFi and Bluetooth. It also
45 includes a USB SD reader, four USB3 ports, display port and HDMI
46 video output and a 16GB SATA solid state drive. There is no Chrome
49 config TARGET_CROWNBAY
50 bool "Support Intel Crown Bay CRB"
52 This is the Intel Crown Bay Customer Reference Board. It contains
53 the Intel Atom Processor E6xx populated on the COM Express module
54 with 1GB DDR2 soldered down memory and a carrier board with the
55 Intel Platform Controller Hub EG20T, other system components and
56 peripheral connectors for PCIe/SATA/USB/LAN/SD/UART/Audio/LVDS.
58 config TARGET_MINNOWMAX
59 bool "Support Intel Minnowboard MAX"
61 This is the Intel Minnowboard MAX. It contains an Atom E3800
62 processor in a small form factor with Ethernet, micro-SD, USB 2,
63 USB 3, SATA, serial console, some GPIOs and HDMI 1.3 video out.
64 It requires some binary blobs - see README.x86 for details.
66 Note that PCIE_ECAM_BASE is set up by the FSP so the value used
67 by U-Boot matches that value.
70 bool "Support Intel Galileo"
72 This is the Intel Galileo board, which is the first in a family of
73 Arduino-certified development and prototyping boards based on Intel
74 architecture. It includes an Intel Quark SoC X1000 processor, a 32-bit
75 single-core, single-thread, Intel Pentium processor instrunction set
76 architecture (ISA) compatible, operating at speeds up to 400Mhz,
77 along with 256MB DDR3 memory. It supports a wide range of industry
78 standard I/O interfaces, including a full-sized mini-PCIe slot,
79 one 100Mb Ethernet port, a microSD card slot, a USB host port and
90 config SYS_MALLOC_F_LEN
99 depends on X86_RESET_VECTOR
108 default 0xfed00000 if !HPET_ADDRESS_OVERRIDE
117 config X86_RESET_VECTOR
121 config SYS_X86_START16
123 depends on X86_RESET_VECTOR
126 config BOARD_ROMSIZE_KB_512
128 config BOARD_ROMSIZE_KB_1024
130 config BOARD_ROMSIZE_KB_2048
132 config BOARD_ROMSIZE_KB_4096
134 config BOARD_ROMSIZE_KB_8192
136 config BOARD_ROMSIZE_KB_16384
140 prompt "ROM chip size"
141 depends on X86_RESET_VECTOR
142 default UBOOT_ROMSIZE_KB_512 if BOARD_ROMSIZE_KB_512
143 default UBOOT_ROMSIZE_KB_1024 if BOARD_ROMSIZE_KB_1024
144 default UBOOT_ROMSIZE_KB_2048 if BOARD_ROMSIZE_KB_2048
145 default UBOOT_ROMSIZE_KB_4096 if BOARD_ROMSIZE_KB_4096
146 default UBOOT_ROMSIZE_KB_8192 if BOARD_ROMSIZE_KB_8192
147 default UBOOT_ROMSIZE_KB_16384 if BOARD_ROMSIZE_KB_16384
149 Select the size of the ROM chip you intend to flash U-Boot on.
151 The build system will take care of creating a u-boot.rom file
152 of the matching size.
154 config UBOOT_ROMSIZE_KB_512
157 Choose this option if you have a 512 KB ROM chip.
159 config UBOOT_ROMSIZE_KB_1024
160 bool "1024 KB (1 MB)"
162 Choose this option if you have a 1024 KB (1 MB) ROM chip.
164 config UBOOT_ROMSIZE_KB_2048
165 bool "2048 KB (2 MB)"
167 Choose this option if you have a 2048 KB (2 MB) ROM chip.
169 config UBOOT_ROMSIZE_KB_4096
170 bool "4096 KB (4 MB)"
172 Choose this option if you have a 4096 KB (4 MB) ROM chip.
174 config UBOOT_ROMSIZE_KB_8192
175 bool "8192 KB (8 MB)"
177 Choose this option if you have a 8192 KB (8 MB) ROM chip.
179 config UBOOT_ROMSIZE_KB_16384
180 bool "16384 KB (16 MB)"
182 Choose this option if you have a 16384 KB (16 MB) ROM chip.
186 # Map the config names to an integer (KB).
187 config UBOOT_ROMSIZE_KB
189 default 512 if UBOOT_ROMSIZE_KB_512
190 default 1024 if UBOOT_ROMSIZE_KB_1024
191 default 2048 if UBOOT_ROMSIZE_KB_2048
192 default 4096 if UBOOT_ROMSIZE_KB_4096
193 default 8192 if UBOOT_ROMSIZE_KB_8192
194 default 16384 if UBOOT_ROMSIZE_KB_16384
196 # Map the config names to a hex value (bytes).
199 default 0x80000 if UBOOT_ROMSIZE_KB_512
200 default 0x100000 if UBOOT_ROMSIZE_KB_1024
201 default 0x200000 if UBOOT_ROMSIZE_KB_2048
202 default 0x400000 if UBOOT_ROMSIZE_KB_4096
203 default 0x800000 if UBOOT_ROMSIZE_KB_8192
204 default 0xc00000 if UBOOT_ROMSIZE_KB_12288
205 default 0x1000000 if UBOOT_ROMSIZE_KB_16384
208 bool "Platform requires Intel Management Engine"
210 Newer higher-end devices have an Intel Management Engine (ME)
211 which is a very large binary blob (typically 1.5MB) which is
212 required for the platform to work. This enforces a particular
213 SPI flash format. You will need to supply the me.bin file in
214 your board directory.
217 bool "Perform a simple RAM test after SDRAM initialisation"
219 If there is something wrong with SDRAM then the platform will
220 often crash within U-Boot or the kernel. This option enables a
221 very simple RAM test that quickly checks whether the SDRAM seems
222 to work correctly. It is not exhaustive but can save time by
223 detecting obvious failures.
225 config MARK_GRAPHICS_MEM_WRCOMB
226 bool "Mark graphics memory as write-combining."
229 The graphics performance may increase if the graphics
230 memory is set as write-combining cache type. This option
231 enables marking the graphics memory as write-combining.
235 config FRAMEBUFFER_SET_VESA_MODE
236 prompt "Set framebuffer graphics resolution"
239 Set VESA/native framebuffer mode (needed for bootsplash and graphical framebuffer console)
242 prompt "framebuffer graphics resolution"
243 default FRAMEBUFFER_VESA_MODE_117
244 depends on FRAMEBUFFER_SET_VESA_MODE
246 This option sets the resolution used for the coreboot framebuffer (and
249 config FRAMEBUFFER_VESA_MODE_100
250 bool "640x400 256-color"
252 config FRAMEBUFFER_VESA_MODE_101
253 bool "640x480 256-color"
255 config FRAMEBUFFER_VESA_MODE_102
256 bool "800x600 16-color"
258 config FRAMEBUFFER_VESA_MODE_103
259 bool "800x600 256-color"
261 config FRAMEBUFFER_VESA_MODE_104
262 bool "1024x768 16-color"
264 config FRAMEBUFFER_VESA_MODE_105
265 bool "1024x7686 256-color"
267 config FRAMEBUFFER_VESA_MODE_106
268 bool "1280x1024 16-color"
270 config FRAMEBUFFER_VESA_MODE_107
271 bool "1280x1024 256-color"
273 config FRAMEBUFFER_VESA_MODE_108
276 config FRAMEBUFFER_VESA_MODE_109
279 config FRAMEBUFFER_VESA_MODE_10A
282 config FRAMEBUFFER_VESA_MODE_10B
285 config FRAMEBUFFER_VESA_MODE_10C
288 config FRAMEBUFFER_VESA_MODE_10D
289 bool "320x200 32k-color (1:5:5:5)"
291 config FRAMEBUFFER_VESA_MODE_10E
292 bool "320x200 64k-color (5:6:5)"
294 config FRAMEBUFFER_VESA_MODE_10F
295 bool "320x200 16.8M-color (8:8:8)"
297 config FRAMEBUFFER_VESA_MODE_110
298 bool "640x480 32k-color (1:5:5:5)"
300 config FRAMEBUFFER_VESA_MODE_111
301 bool "640x480 64k-color (5:6:5)"
303 config FRAMEBUFFER_VESA_MODE_112
304 bool "640x480 16.8M-color (8:8:8)"
306 config FRAMEBUFFER_VESA_MODE_113
307 bool "800x600 32k-color (1:5:5:5)"
309 config FRAMEBUFFER_VESA_MODE_114
310 bool "800x600 64k-color (5:6:5)"
312 config FRAMEBUFFER_VESA_MODE_115
313 bool "800x600 16.8M-color (8:8:8)"
315 config FRAMEBUFFER_VESA_MODE_116
316 bool "1024x768 32k-color (1:5:5:5)"
318 config FRAMEBUFFER_VESA_MODE_117
319 bool "1024x768 64k-color (5:6:5)"
321 config FRAMEBUFFER_VESA_MODE_118
322 bool "1024x768 16.8M-color (8:8:8)"
324 config FRAMEBUFFER_VESA_MODE_119
325 bool "1280x1024 32k-color (1:5:5:5)"
327 config FRAMEBUFFER_VESA_MODE_11A
328 bool "1280x1024 64k-color (5:6:5)"
330 config FRAMEBUFFER_VESA_MODE_11B
331 bool "1280x1024 16.8M-color (8:8:8)"
333 config FRAMEBUFFER_VESA_MODE_USER
334 bool "Manually select VESA mode"
338 # Map the config names to an integer (KB).
339 config FRAMEBUFFER_VESA_MODE
340 prompt "VESA mode" if FRAMEBUFFER_VESA_MODE_USER
342 default 0x100 if FRAMEBUFFER_VESA_MODE_100
343 default 0x101 if FRAMEBUFFER_VESA_MODE_101
344 default 0x102 if FRAMEBUFFER_VESA_MODE_102
345 default 0x103 if FRAMEBUFFER_VESA_MODE_103
346 default 0x104 if FRAMEBUFFER_VESA_MODE_104
347 default 0x105 if FRAMEBUFFER_VESA_MODE_105
348 default 0x106 if FRAMEBUFFER_VESA_MODE_106
349 default 0x107 if FRAMEBUFFER_VESA_MODE_107
350 default 0x108 if FRAMEBUFFER_VESA_MODE_108
351 default 0x109 if FRAMEBUFFER_VESA_MODE_109
352 default 0x10A if FRAMEBUFFER_VESA_MODE_10A
353 default 0x10B if FRAMEBUFFER_VESA_MODE_10B
354 default 0x10C if FRAMEBUFFER_VESA_MODE_10C
355 default 0x10D if FRAMEBUFFER_VESA_MODE_10D
356 default 0x10E if FRAMEBUFFER_VESA_MODE_10E
357 default 0x10F if FRAMEBUFFER_VESA_MODE_10F
358 default 0x110 if FRAMEBUFFER_VESA_MODE_110
359 default 0x111 if FRAMEBUFFER_VESA_MODE_111
360 default 0x112 if FRAMEBUFFER_VESA_MODE_112
361 default 0x113 if FRAMEBUFFER_VESA_MODE_113
362 default 0x114 if FRAMEBUFFER_VESA_MODE_114
363 default 0x115 if FRAMEBUFFER_VESA_MODE_115
364 default 0x116 if FRAMEBUFFER_VESA_MODE_116
365 default 0x117 if FRAMEBUFFER_VESA_MODE_117
366 default 0x118 if FRAMEBUFFER_VESA_MODE_118
367 default 0x119 if FRAMEBUFFER_VESA_MODE_119
368 default 0x11A if FRAMEBUFFER_VESA_MODE_11A
369 default 0x11B if FRAMEBUFFER_VESA_MODE_11B
370 default 0x117 if FRAMEBUFFER_VESA_MODE_USER
375 bool "Add an Firmware Support Package binary"
377 Select this option to add an Firmware Support Package binary to
378 the resulting U-Boot image. It is a binary blob which U-Boot uses
379 to set up SDRAM and other chipset specific initialization.
381 Note: Without this binary U-Boot will not be able to set up its
382 SDRAM so will not boot.
385 string "Firmware Support Package binary filename"
389 The filename of the file to use as Firmware Support Package binary
390 in the board directory.
393 hex "Firmware Support Package binary location"
397 FSP is not Position Independent Code (PIC) and the whole FSP has to
398 be rebased if it is placed at a location which is different from the
399 perferred base address specified during the FSP build. Use Intel's
400 Binary Configuration Tool (BCT) to do the rebase.
402 The default base address of 0xfffc0000 indicates that the binary must
403 be located at offset 0xc0000 from the beginning of a 1MB flash device.
405 config FSP_TEMP_RAM_ADDR
409 Stack top address which is used in FspInit after DRAM is ready and
412 source "arch/x86/cpu/baytrail/Kconfig"
414 source "arch/x86/cpu/coreboot/Kconfig"
416 source "arch/x86/cpu/ivybridge/Kconfig"
418 source "arch/x86/cpu/quark/Kconfig"
420 source "arch/x86/cpu/queensbay/Kconfig"
422 config TSC_CALIBRATION_BYPASS
423 bool "Bypass Time-Stamp Counter (TSC) calibration"
426 By default U-Boot automatically calibrates Time-Stamp Counter (TSC)
427 running frequency via Model-Specific Register (MSR) and Programmable
428 Interval Timer (PIT). If the calibration does not work on your board,
429 select this option and provide a hardcoded TSC running frequency with
430 CONFIG_TSC_FREQ_IN_MHZ below.
432 Normally this option should be turned on in a simulation environment
435 config TSC_FREQ_IN_MHZ
436 int "Time-Stamp Counter (TSC) running frequency in MHz"
437 depends on TSC_CALIBRATION_BYPASS
440 The running frequency in MHz of Time-Stamp Counter (TSC).
442 source "board/coreboot/coreboot/Kconfig"
444 source "board/google/chromebook_link/Kconfig"
446 source "board/google/chromebox_panther/Kconfig"
448 source "board/intel/crownbay/Kconfig"
450 source "board/intel/minnowmax/Kconfig"
452 source "board/intel/galileo/Kconfig"
454 config PCIE_ECAM_BASE
458 This is the memory-mapped address of PCI configuration space, which
459 is only available through the Enhanced Configuration Access
460 Mechanism (ECAM) with PCI Express. It can be set up almost
461 anywhere. Before it is set up, it is possible to access PCI
462 configuration space through I/O access, but memory access is more
463 convenient. Using this, PCI can be scanned and configured. This
464 should be set to a region that does not conflict with memory
465 assigned to PCI devices - i.e. the memory and prefetch regions, as
466 passed to pci_set_region().