1 menu "x86 architecture"
7 config USE_PRIVATE_LIBGCC
11 prompt "Target select"
13 config TARGET_COREBOOT
14 bool "Support coreboot"
16 This target is used for running U-Boot on top of Coreboot. In
17 this case Coreboot does the early inititalisation, and U-Boot
18 takes over once the RAM, video and CPU are fully running.
19 U-Boot is loaded as a fallback payload from Coreboot, in
20 Coreboot terminology. This method was used for the Chromebook
23 config TARGET_CHROMEBOOK_LINK
24 bool "Support Chromebook link"
26 This is the Chromebook Pixel released in 2013. It uses an Intel
27 i5 Ivybridge which is a die-shrink of Sandybridge, with 4GB of
28 SDRAM. It has a Panther Point platform controller hub, PCIe
29 WiFi and Bluetooth. It also includes a 720p webcam, USB SD
30 reader, microphone and speakers, display port and 32GB SATA
31 solid state drive. There is a Chrome OS EC connected on LPC,
32 and it provides a 2560x1700 high resolution touch-enabled LCD
35 config TARGET_CROWNBAY
36 bool "Support Intel Crown Bay CRB"
38 This is the Intel Crown Bay Customer Reference Board. It contains
39 the Intel Atom Processor E6xx populated on the COM Express module
40 with 1GB DDR2 soldered down memory and a carrier board with the
41 Intel Platform Controller Hub EG20T, other system components and
42 peripheral connectors for PCIe/SATA/USB/LAN/SD/UART/Audio/LVDS.
52 depends on X86_RESET_VECTOR
61 default 0xfed00000 if !HPET_ADDRESS_OVERRIDE
70 config X86_RESET_VECTOR
74 config SYS_X86_START16
76 depends on X86_RESET_VECTOR
79 config BOARD_ROMSIZE_KB_512
81 config BOARD_ROMSIZE_KB_1024
83 config BOARD_ROMSIZE_KB_2048
85 config BOARD_ROMSIZE_KB_4096
87 config BOARD_ROMSIZE_KB_8192
89 config BOARD_ROMSIZE_KB_16384
93 prompt "ROM chip size"
94 depends on X86_RESET_VECTOR
95 default UBOOT_ROMSIZE_KB_512 if BOARD_ROMSIZE_KB_512
96 default UBOOT_ROMSIZE_KB_1024 if BOARD_ROMSIZE_KB_1024
97 default UBOOT_ROMSIZE_KB_2048 if BOARD_ROMSIZE_KB_2048
98 default UBOOT_ROMSIZE_KB_4096 if BOARD_ROMSIZE_KB_4096
99 default UBOOT_ROMSIZE_KB_8192 if BOARD_ROMSIZE_KB_8192
100 default UBOOT_ROMSIZE_KB_16384 if BOARD_ROMSIZE_KB_16384
102 Select the size of the ROM chip you intend to flash U-Boot on.
104 The build system will take care of creating a u-boot.rom file
105 of the matching size.
107 config UBOOT_ROMSIZE_KB_512
110 Choose this option if you have a 512 KB ROM chip.
112 config UBOOT_ROMSIZE_KB_1024
113 bool "1024 KB (1 MB)"
115 Choose this option if you have a 1024 KB (1 MB) ROM chip.
117 config UBOOT_ROMSIZE_KB_2048
118 bool "2048 KB (2 MB)"
120 Choose this option if you have a 2048 KB (2 MB) ROM chip.
122 config UBOOT_ROMSIZE_KB_4096
123 bool "4096 KB (4 MB)"
125 Choose this option if you have a 4096 KB (4 MB) ROM chip.
127 config UBOOT_ROMSIZE_KB_8192
128 bool "8192 KB (8 MB)"
130 Choose this option if you have a 8192 KB (8 MB) ROM chip.
132 config UBOOT_ROMSIZE_KB_16384
133 bool "16384 KB (16 MB)"
135 Choose this option if you have a 16384 KB (16 MB) ROM chip.
139 # Map the config names to an integer (KB).
140 config UBOOT_ROMSIZE_KB
142 default 512 if UBOOT_ROMSIZE_KB_512
143 default 1024 if UBOOT_ROMSIZE_KB_1024
144 default 2048 if UBOOT_ROMSIZE_KB_2048
145 default 4096 if UBOOT_ROMSIZE_KB_4096
146 default 8192 if UBOOT_ROMSIZE_KB_8192
147 default 16384 if UBOOT_ROMSIZE_KB_16384
149 # Map the config names to a hex value (bytes).
152 default 0x80000 if UBOOT_ROMSIZE_KB_512
153 default 0x100000 if UBOOT_ROMSIZE_KB_1024
154 default 0x200000 if UBOOT_ROMSIZE_KB_2048
155 default 0x400000 if UBOOT_ROMSIZE_KB_4096
156 default 0x800000 if UBOOT_ROMSIZE_KB_8192
157 default 0xc00000 if UBOOT_ROMSIZE_KB_12288
158 default 0x1000000 if UBOOT_ROMSIZE_KB_16384
161 bool "Platform requires Intel Management Engine"
163 Newer higher-end devices have an Intel Management Engine (ME)
164 which is a very large binary blob (typically 1.5MB) which is
165 required for the platform to work. This enforces a particular
166 SPI flash format. You will need to supply the me.bin file in
167 your board directory.
170 bool "Perform a simple RAM test after SDRAM initialisation"
172 If there is something wrong with SDRAM then the platform will
173 often crash within U-Boot or the kernel. This option enables a
174 very simple RAM test that quickly checks whether the SDRAM seems
175 to work correctly. It is not exhaustive but can save time by
176 detecting obvious failures.
178 config MARK_GRAPHICS_MEM_WRCOMB
179 bool "Mark graphics memory as write-combining."
182 The graphics performance may increase if the graphics
183 memory is set as write-combining cache type. This option
184 enables marking the graphics memory as write-combining.
188 config FRAMEBUFFER_SET_VESA_MODE
189 prompt "Set framebuffer graphics resolution"
192 Set VESA/native framebuffer mode (needed for bootsplash and graphical framebuffer console)
195 prompt "framebuffer graphics resolution"
196 default FRAMEBUFFER_VESA_MODE_117
197 depends on FRAMEBUFFER_SET_VESA_MODE
199 This option sets the resolution used for the coreboot framebuffer (and
202 config FRAMEBUFFER_VESA_MODE_100
203 bool "640x400 256-color"
205 config FRAMEBUFFER_VESA_MODE_101
206 bool "640x480 256-color"
208 config FRAMEBUFFER_VESA_MODE_102
209 bool "800x600 16-color"
211 config FRAMEBUFFER_VESA_MODE_103
212 bool "800x600 256-color"
214 config FRAMEBUFFER_VESA_MODE_104
215 bool "1024x768 16-color"
217 config FRAMEBUFFER_VESA_MODE_105
218 bool "1024x7686 256-color"
220 config FRAMEBUFFER_VESA_MODE_106
221 bool "1280x1024 16-color"
223 config FRAMEBUFFER_VESA_MODE_107
224 bool "1280x1024 256-color"
226 config FRAMEBUFFER_VESA_MODE_108
229 config FRAMEBUFFER_VESA_MODE_109
232 config FRAMEBUFFER_VESA_MODE_10A
235 config FRAMEBUFFER_VESA_MODE_10B
238 config FRAMEBUFFER_VESA_MODE_10C
241 config FRAMEBUFFER_VESA_MODE_10D
242 bool "320x200 32k-color (1:5:5:5)"
244 config FRAMEBUFFER_VESA_MODE_10E
245 bool "320x200 64k-color (5:6:5)"
247 config FRAMEBUFFER_VESA_MODE_10F
248 bool "320x200 16.8M-color (8:8:8)"
250 config FRAMEBUFFER_VESA_MODE_110
251 bool "640x480 32k-color (1:5:5:5)"
253 config FRAMEBUFFER_VESA_MODE_111
254 bool "640x480 64k-color (5:6:5)"
256 config FRAMEBUFFER_VESA_MODE_112
257 bool "640x480 16.8M-color (8:8:8)"
259 config FRAMEBUFFER_VESA_MODE_113
260 bool "800x600 32k-color (1:5:5:5)"
262 config FRAMEBUFFER_VESA_MODE_114
263 bool "800x600 64k-color (5:6:5)"
265 config FRAMEBUFFER_VESA_MODE_115
266 bool "800x600 16.8M-color (8:8:8)"
268 config FRAMEBUFFER_VESA_MODE_116
269 bool "1024x768 32k-color (1:5:5:5)"
271 config FRAMEBUFFER_VESA_MODE_117
272 bool "1024x768 64k-color (5:6:5)"
274 config FRAMEBUFFER_VESA_MODE_118
275 bool "1024x768 16.8M-color (8:8:8)"
277 config FRAMEBUFFER_VESA_MODE_119
278 bool "1280x1024 32k-color (1:5:5:5)"
280 config FRAMEBUFFER_VESA_MODE_11A
281 bool "1280x1024 64k-color (5:6:5)"
283 config FRAMEBUFFER_VESA_MODE_11B
284 bool "1280x1024 16.8M-color (8:8:8)"
286 config FRAMEBUFFER_VESA_MODE_USER
287 bool "Manually select VESA mode"
291 # Map the config names to an integer (KB).
292 config FRAMEBUFFER_VESA_MODE
293 prompt "VESA mode" if FRAMEBUFFER_VESA_MODE_USER
295 default 0x100 if FRAMEBUFFER_VESA_MODE_100
296 default 0x101 if FRAMEBUFFER_VESA_MODE_101
297 default 0x102 if FRAMEBUFFER_VESA_MODE_102
298 default 0x103 if FRAMEBUFFER_VESA_MODE_103
299 default 0x104 if FRAMEBUFFER_VESA_MODE_104
300 default 0x105 if FRAMEBUFFER_VESA_MODE_105
301 default 0x106 if FRAMEBUFFER_VESA_MODE_106
302 default 0x107 if FRAMEBUFFER_VESA_MODE_107
303 default 0x108 if FRAMEBUFFER_VESA_MODE_108
304 default 0x109 if FRAMEBUFFER_VESA_MODE_109
305 default 0x10A if FRAMEBUFFER_VESA_MODE_10A
306 default 0x10B if FRAMEBUFFER_VESA_MODE_10B
307 default 0x10C if FRAMEBUFFER_VESA_MODE_10C
308 default 0x10D if FRAMEBUFFER_VESA_MODE_10D
309 default 0x10E if FRAMEBUFFER_VESA_MODE_10E
310 default 0x10F if FRAMEBUFFER_VESA_MODE_10F
311 default 0x110 if FRAMEBUFFER_VESA_MODE_110
312 default 0x111 if FRAMEBUFFER_VESA_MODE_111
313 default 0x112 if FRAMEBUFFER_VESA_MODE_112
314 default 0x113 if FRAMEBUFFER_VESA_MODE_113
315 default 0x114 if FRAMEBUFFER_VESA_MODE_114
316 default 0x115 if FRAMEBUFFER_VESA_MODE_115
317 default 0x116 if FRAMEBUFFER_VESA_MODE_116
318 default 0x117 if FRAMEBUFFER_VESA_MODE_117
319 default 0x118 if FRAMEBUFFER_VESA_MODE_118
320 default 0x119 if FRAMEBUFFER_VESA_MODE_119
321 default 0x11A if FRAMEBUFFER_VESA_MODE_11A
322 default 0x11B if FRAMEBUFFER_VESA_MODE_11B
323 default 0x117 if FRAMEBUFFER_VESA_MODE_USER
327 config TSC_CALIBRATION_BYPASS
328 bool "Bypass Time-Stamp Counter (TSC) calibration"
331 By default U-Boot automatically calibrates Time-Stamp Counter (TSC)
332 running frequency via Model-Specific Register (MSR) and Programmable
333 Interval Timer (PIT). If the calibration does not work on your board,
334 select this option and provide a hardcoded TSC running frequency with
335 CONFIG_TSC_FREQ_IN_MHZ below.
337 Normally this option should be turned on in a simulation environment
340 config TSC_FREQ_IN_MHZ
341 int "Time-Stamp Counter (TSC) running frequency in MHz"
342 depends on TSC_CALIBRATION_BYPASS
345 The running frequency in MHz of Time-Stamp Counter (TSC).
347 source "arch/x86/cpu/coreboot/Kconfig"
349 source "arch/x86/cpu/ivybridge/Kconfig"
351 source "arch/x86/cpu/queensbay/Kconfig"
353 source "board/coreboot/coreboot/Kconfig"
355 source "board/google/chromebook_link/Kconfig"
357 source "board/intel/crownbay/Kconfig"
359 config PCIE_ECAM_BASE
363 This is the memory-mapped address of PCI configuration space, which
364 is only available through the Enhanced Configuration Access
365 Mechanism (ECAM) with PCI Express. It can be set up almost
366 anywhere. Before it is set up, it is possible to access PCI
367 configuration space through I/O access, but memory access is more
368 convenient. Using this, PCI can be scanned and configured. This
369 should be set to a region that does not conflict with memory
370 assigned to PCI devices - i.e. the memory and prefetch regions, as
371 passed to pci_set_region().