1 menu "x86 architecture"
7 config USE_PRIVATE_LIBGCC
11 prompt "Target select"
13 config TARGET_COREBOOT
14 bool "Support coreboot"
16 This target is used for running U-Boot on top of Coreboot. In
17 this case Coreboot does the early inititalisation, and U-Boot
18 takes over once the RAM, video and CPU are fully running.
19 U-Boot is loaded as a fallback payload from Coreboot, in
20 Coreboot terminology. This method was used for the Chromebook
23 config TARGET_CHROMEBOOK_LINK
24 bool "Support Chromebook link"
26 This is the Chromebook Pixel released in 2013. It uses an Intel
27 i5 Ivybridge which is a die-shrink of Sandybridge, with 4GB of
28 SDRAM. It has a Panther Point platform controller hub, PCIe
29 WiFi and Bluetooth. It also includes a 720p webcam, USB SD
30 reader, microphone and speakers, display port and 32GB SATA
31 solid state drive. There is a Chrome OS EC connected on LPC,
32 and it provides a 2560x1700 high resolution touch-enabled LCD
35 config TARGET_CROWNBAY
36 bool "Support Intel Crown Bay CRB"
38 This is the Intel Crown Bay Customer Reference Board. It contains
39 the Intel Atom Processor E6xx populated on the COM Express module
40 with 1GB DDR2 soldered down memory and a carrier board with the
41 Intel Platform Controller Hub EG20T, other system components and
42 peripheral connectors for PCIe/SATA/USB/LAN/SD/UART/Audio/LVDS.
44 config TARGET_MINNOWMAX
45 bool "Support Intel Minnowboard MAX"
47 This is the Intel Minnowboard MAX. It contains an Atom E3800
48 processor in a small form factor with Ethernet, micro-SD, USB 2,
49 USB 3, SATA, serial console, some GPIOs and HDMI 1.3 video out.
50 It requires some binary blobs - see README.x86 for details.
52 Note that PCIE_ECAM_BASE is set up by the FSP so the value used
53 by U-Boot matches that value.
56 bool "Support Intel Galileo"
58 This is the Intel Galileo board, which is the first in a family of
59 Arduino-certified development and prototyping boards based on Intel
60 architecture. It includes an Intel Quark SoC X1000 processor, a 32-bit
61 single-core, single-thread, Intel Pentium processor instrunction set
62 architecture (ISA) compatible, operating at speeds up to 400Mhz,
63 along with 256MB DDR3 memory. It supports a wide range of industry
64 standard I/O interfaces, including a full-sized mini-PCIe slot,
65 one 100Mb Ethernet port, a microSD card slot, a USB host port and
85 depends on X86_RESET_VECTOR
94 default 0xfed00000 if !HPET_ADDRESS_OVERRIDE
103 config X86_RESET_VECTOR
107 config SYS_X86_START16
109 depends on X86_RESET_VECTOR
112 config BOARD_ROMSIZE_KB_512
114 config BOARD_ROMSIZE_KB_1024
116 config BOARD_ROMSIZE_KB_2048
118 config BOARD_ROMSIZE_KB_4096
120 config BOARD_ROMSIZE_KB_8192
122 config BOARD_ROMSIZE_KB_16384
126 prompt "ROM chip size"
127 depends on X86_RESET_VECTOR
128 default UBOOT_ROMSIZE_KB_512 if BOARD_ROMSIZE_KB_512
129 default UBOOT_ROMSIZE_KB_1024 if BOARD_ROMSIZE_KB_1024
130 default UBOOT_ROMSIZE_KB_2048 if BOARD_ROMSIZE_KB_2048
131 default UBOOT_ROMSIZE_KB_4096 if BOARD_ROMSIZE_KB_4096
132 default UBOOT_ROMSIZE_KB_8192 if BOARD_ROMSIZE_KB_8192
133 default UBOOT_ROMSIZE_KB_16384 if BOARD_ROMSIZE_KB_16384
135 Select the size of the ROM chip you intend to flash U-Boot on.
137 The build system will take care of creating a u-boot.rom file
138 of the matching size.
140 config UBOOT_ROMSIZE_KB_512
143 Choose this option if you have a 512 KB ROM chip.
145 config UBOOT_ROMSIZE_KB_1024
146 bool "1024 KB (1 MB)"
148 Choose this option if you have a 1024 KB (1 MB) ROM chip.
150 config UBOOT_ROMSIZE_KB_2048
151 bool "2048 KB (2 MB)"
153 Choose this option if you have a 2048 KB (2 MB) ROM chip.
155 config UBOOT_ROMSIZE_KB_4096
156 bool "4096 KB (4 MB)"
158 Choose this option if you have a 4096 KB (4 MB) ROM chip.
160 config UBOOT_ROMSIZE_KB_8192
161 bool "8192 KB (8 MB)"
163 Choose this option if you have a 8192 KB (8 MB) ROM chip.
165 config UBOOT_ROMSIZE_KB_16384
166 bool "16384 KB (16 MB)"
168 Choose this option if you have a 16384 KB (16 MB) ROM chip.
172 # Map the config names to an integer (KB).
173 config UBOOT_ROMSIZE_KB
175 default 512 if UBOOT_ROMSIZE_KB_512
176 default 1024 if UBOOT_ROMSIZE_KB_1024
177 default 2048 if UBOOT_ROMSIZE_KB_2048
178 default 4096 if UBOOT_ROMSIZE_KB_4096
179 default 8192 if UBOOT_ROMSIZE_KB_8192
180 default 16384 if UBOOT_ROMSIZE_KB_16384
182 # Map the config names to a hex value (bytes).
185 default 0x80000 if UBOOT_ROMSIZE_KB_512
186 default 0x100000 if UBOOT_ROMSIZE_KB_1024
187 default 0x200000 if UBOOT_ROMSIZE_KB_2048
188 default 0x400000 if UBOOT_ROMSIZE_KB_4096
189 default 0x800000 if UBOOT_ROMSIZE_KB_8192
190 default 0xc00000 if UBOOT_ROMSIZE_KB_12288
191 default 0x1000000 if UBOOT_ROMSIZE_KB_16384
194 bool "Platform requires Intel Management Engine"
196 Newer higher-end devices have an Intel Management Engine (ME)
197 which is a very large binary blob (typically 1.5MB) which is
198 required for the platform to work. This enforces a particular
199 SPI flash format. You will need to supply the me.bin file in
200 your board directory.
203 bool "Perform a simple RAM test after SDRAM initialisation"
205 If there is something wrong with SDRAM then the platform will
206 often crash within U-Boot or the kernel. This option enables a
207 very simple RAM test that quickly checks whether the SDRAM seems
208 to work correctly. It is not exhaustive but can save time by
209 detecting obvious failures.
211 config MARK_GRAPHICS_MEM_WRCOMB
212 bool "Mark graphics memory as write-combining."
215 The graphics performance may increase if the graphics
216 memory is set as write-combining cache type. This option
217 enables marking the graphics memory as write-combining.
221 config FRAMEBUFFER_SET_VESA_MODE
222 prompt "Set framebuffer graphics resolution"
225 Set VESA/native framebuffer mode (needed for bootsplash and graphical framebuffer console)
228 prompt "framebuffer graphics resolution"
229 default FRAMEBUFFER_VESA_MODE_117
230 depends on FRAMEBUFFER_SET_VESA_MODE
232 This option sets the resolution used for the coreboot framebuffer (and
235 config FRAMEBUFFER_VESA_MODE_100
236 bool "640x400 256-color"
238 config FRAMEBUFFER_VESA_MODE_101
239 bool "640x480 256-color"
241 config FRAMEBUFFER_VESA_MODE_102
242 bool "800x600 16-color"
244 config FRAMEBUFFER_VESA_MODE_103
245 bool "800x600 256-color"
247 config FRAMEBUFFER_VESA_MODE_104
248 bool "1024x768 16-color"
250 config FRAMEBUFFER_VESA_MODE_105
251 bool "1024x7686 256-color"
253 config FRAMEBUFFER_VESA_MODE_106
254 bool "1280x1024 16-color"
256 config FRAMEBUFFER_VESA_MODE_107
257 bool "1280x1024 256-color"
259 config FRAMEBUFFER_VESA_MODE_108
262 config FRAMEBUFFER_VESA_MODE_109
265 config FRAMEBUFFER_VESA_MODE_10A
268 config FRAMEBUFFER_VESA_MODE_10B
271 config FRAMEBUFFER_VESA_MODE_10C
274 config FRAMEBUFFER_VESA_MODE_10D
275 bool "320x200 32k-color (1:5:5:5)"
277 config FRAMEBUFFER_VESA_MODE_10E
278 bool "320x200 64k-color (5:6:5)"
280 config FRAMEBUFFER_VESA_MODE_10F
281 bool "320x200 16.8M-color (8:8:8)"
283 config FRAMEBUFFER_VESA_MODE_110
284 bool "640x480 32k-color (1:5:5:5)"
286 config FRAMEBUFFER_VESA_MODE_111
287 bool "640x480 64k-color (5:6:5)"
289 config FRAMEBUFFER_VESA_MODE_112
290 bool "640x480 16.8M-color (8:8:8)"
292 config FRAMEBUFFER_VESA_MODE_113
293 bool "800x600 32k-color (1:5:5:5)"
295 config FRAMEBUFFER_VESA_MODE_114
296 bool "800x600 64k-color (5:6:5)"
298 config FRAMEBUFFER_VESA_MODE_115
299 bool "800x600 16.8M-color (8:8:8)"
301 config FRAMEBUFFER_VESA_MODE_116
302 bool "1024x768 32k-color (1:5:5:5)"
304 config FRAMEBUFFER_VESA_MODE_117
305 bool "1024x768 64k-color (5:6:5)"
307 config FRAMEBUFFER_VESA_MODE_118
308 bool "1024x768 16.8M-color (8:8:8)"
310 config FRAMEBUFFER_VESA_MODE_119
311 bool "1280x1024 32k-color (1:5:5:5)"
313 config FRAMEBUFFER_VESA_MODE_11A
314 bool "1280x1024 64k-color (5:6:5)"
316 config FRAMEBUFFER_VESA_MODE_11B
317 bool "1280x1024 16.8M-color (8:8:8)"
319 config FRAMEBUFFER_VESA_MODE_USER
320 bool "Manually select VESA mode"
324 # Map the config names to an integer (KB).
325 config FRAMEBUFFER_VESA_MODE
326 prompt "VESA mode" if FRAMEBUFFER_VESA_MODE_USER
328 default 0x100 if FRAMEBUFFER_VESA_MODE_100
329 default 0x101 if FRAMEBUFFER_VESA_MODE_101
330 default 0x102 if FRAMEBUFFER_VESA_MODE_102
331 default 0x103 if FRAMEBUFFER_VESA_MODE_103
332 default 0x104 if FRAMEBUFFER_VESA_MODE_104
333 default 0x105 if FRAMEBUFFER_VESA_MODE_105
334 default 0x106 if FRAMEBUFFER_VESA_MODE_106
335 default 0x107 if FRAMEBUFFER_VESA_MODE_107
336 default 0x108 if FRAMEBUFFER_VESA_MODE_108
337 default 0x109 if FRAMEBUFFER_VESA_MODE_109
338 default 0x10A if FRAMEBUFFER_VESA_MODE_10A
339 default 0x10B if FRAMEBUFFER_VESA_MODE_10B
340 default 0x10C if FRAMEBUFFER_VESA_MODE_10C
341 default 0x10D if FRAMEBUFFER_VESA_MODE_10D
342 default 0x10E if FRAMEBUFFER_VESA_MODE_10E
343 default 0x10F if FRAMEBUFFER_VESA_MODE_10F
344 default 0x110 if FRAMEBUFFER_VESA_MODE_110
345 default 0x111 if FRAMEBUFFER_VESA_MODE_111
346 default 0x112 if FRAMEBUFFER_VESA_MODE_112
347 default 0x113 if FRAMEBUFFER_VESA_MODE_113
348 default 0x114 if FRAMEBUFFER_VESA_MODE_114
349 default 0x115 if FRAMEBUFFER_VESA_MODE_115
350 default 0x116 if FRAMEBUFFER_VESA_MODE_116
351 default 0x117 if FRAMEBUFFER_VESA_MODE_117
352 default 0x118 if FRAMEBUFFER_VESA_MODE_118
353 default 0x119 if FRAMEBUFFER_VESA_MODE_119
354 default 0x11A if FRAMEBUFFER_VESA_MODE_11A
355 default 0x11B if FRAMEBUFFER_VESA_MODE_11B
356 default 0x117 if FRAMEBUFFER_VESA_MODE_USER
361 bool "Add an Firmware Support Package binary"
363 Select this option to add an Firmware Support Package binary to
364 the resulting U-Boot image. It is a binary blob which U-Boot uses
365 to set up SDRAM and other chipset specific initialization.
367 Note: Without this binary U-Boot will not be able to set up its
368 SDRAM so will not boot.
371 string "Firmware Support Package binary filename"
375 The filename of the file to use as Firmware Support Package binary
376 in the board directory.
379 hex "Firmware Support Package binary location"
383 FSP is not Position Independent Code (PIC) and the whole FSP has to
384 be rebased if it is placed at a location which is different from the
385 perferred base address specified during the FSP build. Use Intel's
386 Binary Configuration Tool (BCT) to do the rebase.
388 The default base address of 0xfffc0000 indicates that the binary must
389 be located at offset 0xc0000 from the beginning of a 1MB flash device.
391 config FSP_TEMP_RAM_ADDR
395 Stack top address which is used in FspInit after DRAM is ready and
398 source "arch/x86/cpu/baytrail/Kconfig"
400 source "arch/x86/cpu/coreboot/Kconfig"
402 source "arch/x86/cpu/ivybridge/Kconfig"
404 source "arch/x86/cpu/quark/Kconfig"
406 source "arch/x86/cpu/queensbay/Kconfig"
408 config TSC_CALIBRATION_BYPASS
409 bool "Bypass Time-Stamp Counter (TSC) calibration"
412 By default U-Boot automatically calibrates Time-Stamp Counter (TSC)
413 running frequency via Model-Specific Register (MSR) and Programmable
414 Interval Timer (PIT). If the calibration does not work on your board,
415 select this option and provide a hardcoded TSC running frequency with
416 CONFIG_TSC_FREQ_IN_MHZ below.
418 Normally this option should be turned on in a simulation environment
421 config TSC_FREQ_IN_MHZ
422 int "Time-Stamp Counter (TSC) running frequency in MHz"
423 depends on TSC_CALIBRATION_BYPASS
426 The running frequency in MHz of Time-Stamp Counter (TSC).
428 source "board/coreboot/coreboot/Kconfig"
430 source "board/google/chromebook_link/Kconfig"
432 source "board/intel/crownbay/Kconfig"
434 source "board/intel/minnowmax/Kconfig"
436 source "board/intel/galileo/Kconfig"
438 config PCIE_ECAM_BASE
442 This is the memory-mapped address of PCI configuration space, which
443 is only available through the Enhanced Configuration Access
444 Mechanism (ECAM) with PCI Express. It can be set up almost
445 anywhere. Before it is set up, it is possible to access PCI
446 configuration space through I/O access, but memory access is more
447 convenient. Using this, PCI can be scanned and configured. This
448 should be set to a region that does not conflict with memory
449 assigned to PCI devices - i.e. the memory and prefetch regions, as
450 passed to pci_set_region().