1 menu "x86 architecture"
7 config USE_PRIVATE_LIBGCC
14 prompt "Mainboard vendor"
15 default VENDOR_COREBOOT
17 config VENDOR_COREBOOT
28 # board-specific options below
29 source "board/coreboot/Kconfig"
30 source "board/google/Kconfig"
31 source "board/intel/Kconfig"
39 config SYS_MALLOC_F_LEN
48 depends on X86_RESET_VECTOR
57 default 0xfed00000 if !HPET_ADDRESS_OVERRIDE
66 config X86_RESET_VECTOR
70 config SYS_X86_START16
72 depends on X86_RESET_VECTOR
75 config BOARD_ROMSIZE_KB_512
77 config BOARD_ROMSIZE_KB_1024
79 config BOARD_ROMSIZE_KB_2048
81 config BOARD_ROMSIZE_KB_4096
83 config BOARD_ROMSIZE_KB_8192
85 config BOARD_ROMSIZE_KB_16384
89 prompt "ROM chip size"
90 depends on X86_RESET_VECTOR
91 default UBOOT_ROMSIZE_KB_512 if BOARD_ROMSIZE_KB_512
92 default UBOOT_ROMSIZE_KB_1024 if BOARD_ROMSIZE_KB_1024
93 default UBOOT_ROMSIZE_KB_2048 if BOARD_ROMSIZE_KB_2048
94 default UBOOT_ROMSIZE_KB_4096 if BOARD_ROMSIZE_KB_4096
95 default UBOOT_ROMSIZE_KB_8192 if BOARD_ROMSIZE_KB_8192
96 default UBOOT_ROMSIZE_KB_16384 if BOARD_ROMSIZE_KB_16384
98 Select the size of the ROM chip you intend to flash U-Boot on.
100 The build system will take care of creating a u-boot.rom file
101 of the matching size.
103 config UBOOT_ROMSIZE_KB_512
106 Choose this option if you have a 512 KB ROM chip.
108 config UBOOT_ROMSIZE_KB_1024
109 bool "1024 KB (1 MB)"
111 Choose this option if you have a 1024 KB (1 MB) ROM chip.
113 config UBOOT_ROMSIZE_KB_2048
114 bool "2048 KB (2 MB)"
116 Choose this option if you have a 2048 KB (2 MB) ROM chip.
118 config UBOOT_ROMSIZE_KB_4096
119 bool "4096 KB (4 MB)"
121 Choose this option if you have a 4096 KB (4 MB) ROM chip.
123 config UBOOT_ROMSIZE_KB_8192
124 bool "8192 KB (8 MB)"
126 Choose this option if you have a 8192 KB (8 MB) ROM chip.
128 config UBOOT_ROMSIZE_KB_16384
129 bool "16384 KB (16 MB)"
131 Choose this option if you have a 16384 KB (16 MB) ROM chip.
135 # Map the config names to an integer (KB).
136 config UBOOT_ROMSIZE_KB
138 default 512 if UBOOT_ROMSIZE_KB_512
139 default 1024 if UBOOT_ROMSIZE_KB_1024
140 default 2048 if UBOOT_ROMSIZE_KB_2048
141 default 4096 if UBOOT_ROMSIZE_KB_4096
142 default 8192 if UBOOT_ROMSIZE_KB_8192
143 default 16384 if UBOOT_ROMSIZE_KB_16384
145 # Map the config names to a hex value (bytes).
148 default 0x80000 if UBOOT_ROMSIZE_KB_512
149 default 0x100000 if UBOOT_ROMSIZE_KB_1024
150 default 0x200000 if UBOOT_ROMSIZE_KB_2048
151 default 0x400000 if UBOOT_ROMSIZE_KB_4096
152 default 0x800000 if UBOOT_ROMSIZE_KB_8192
153 default 0xc00000 if UBOOT_ROMSIZE_KB_12288
154 default 0x1000000 if UBOOT_ROMSIZE_KB_16384
157 bool "Platform requires Intel Management Engine"
159 Newer higher-end devices have an Intel Management Engine (ME)
160 which is a very large binary blob (typically 1.5MB) which is
161 required for the platform to work. This enforces a particular
162 SPI flash format. You will need to supply the me.bin file in
163 your board directory.
166 bool "Perform a simple RAM test after SDRAM initialisation"
168 If there is something wrong with SDRAM then the platform will
169 often crash within U-Boot or the kernel. This option enables a
170 very simple RAM test that quickly checks whether the SDRAM seems
171 to work correctly. It is not exhaustive but can save time by
172 detecting obvious failures.
174 config MARK_GRAPHICS_MEM_WRCOMB
175 bool "Mark graphics memory as write-combining."
178 The graphics performance may increase if the graphics
179 memory is set as write-combining cache type. This option
180 enables marking the graphics memory as write-combining.
184 config FRAMEBUFFER_SET_VESA_MODE
185 prompt "Set framebuffer graphics resolution"
188 Set VESA/native framebuffer mode (needed for bootsplash and graphical framebuffer console)
191 prompt "framebuffer graphics resolution"
192 default FRAMEBUFFER_VESA_MODE_117
193 depends on FRAMEBUFFER_SET_VESA_MODE
195 This option sets the resolution used for the coreboot framebuffer (and
198 config FRAMEBUFFER_VESA_MODE_100
199 bool "640x400 256-color"
201 config FRAMEBUFFER_VESA_MODE_101
202 bool "640x480 256-color"
204 config FRAMEBUFFER_VESA_MODE_102
205 bool "800x600 16-color"
207 config FRAMEBUFFER_VESA_MODE_103
208 bool "800x600 256-color"
210 config FRAMEBUFFER_VESA_MODE_104
211 bool "1024x768 16-color"
213 config FRAMEBUFFER_VESA_MODE_105
214 bool "1024x7686 256-color"
216 config FRAMEBUFFER_VESA_MODE_106
217 bool "1280x1024 16-color"
219 config FRAMEBUFFER_VESA_MODE_107
220 bool "1280x1024 256-color"
222 config FRAMEBUFFER_VESA_MODE_108
225 config FRAMEBUFFER_VESA_MODE_109
228 config FRAMEBUFFER_VESA_MODE_10A
231 config FRAMEBUFFER_VESA_MODE_10B
234 config FRAMEBUFFER_VESA_MODE_10C
237 config FRAMEBUFFER_VESA_MODE_10D
238 bool "320x200 32k-color (1:5:5:5)"
240 config FRAMEBUFFER_VESA_MODE_10E
241 bool "320x200 64k-color (5:6:5)"
243 config FRAMEBUFFER_VESA_MODE_10F
244 bool "320x200 16.8M-color (8:8:8)"
246 config FRAMEBUFFER_VESA_MODE_110
247 bool "640x480 32k-color (1:5:5:5)"
249 config FRAMEBUFFER_VESA_MODE_111
250 bool "640x480 64k-color (5:6:5)"
252 config FRAMEBUFFER_VESA_MODE_112
253 bool "640x480 16.8M-color (8:8:8)"
255 config FRAMEBUFFER_VESA_MODE_113
256 bool "800x600 32k-color (1:5:5:5)"
258 config FRAMEBUFFER_VESA_MODE_114
259 bool "800x600 64k-color (5:6:5)"
261 config FRAMEBUFFER_VESA_MODE_115
262 bool "800x600 16.8M-color (8:8:8)"
264 config FRAMEBUFFER_VESA_MODE_116
265 bool "1024x768 32k-color (1:5:5:5)"
267 config FRAMEBUFFER_VESA_MODE_117
268 bool "1024x768 64k-color (5:6:5)"
270 config FRAMEBUFFER_VESA_MODE_118
271 bool "1024x768 16.8M-color (8:8:8)"
273 config FRAMEBUFFER_VESA_MODE_119
274 bool "1280x1024 32k-color (1:5:5:5)"
276 config FRAMEBUFFER_VESA_MODE_11A
277 bool "1280x1024 64k-color (5:6:5)"
279 config FRAMEBUFFER_VESA_MODE_11B
280 bool "1280x1024 16.8M-color (8:8:8)"
282 config FRAMEBUFFER_VESA_MODE_USER
283 bool "Manually select VESA mode"
287 # Map the config names to an integer (KB).
288 config FRAMEBUFFER_VESA_MODE
289 prompt "VESA mode" if FRAMEBUFFER_VESA_MODE_USER
291 default 0x100 if FRAMEBUFFER_VESA_MODE_100
292 default 0x101 if FRAMEBUFFER_VESA_MODE_101
293 default 0x102 if FRAMEBUFFER_VESA_MODE_102
294 default 0x103 if FRAMEBUFFER_VESA_MODE_103
295 default 0x104 if FRAMEBUFFER_VESA_MODE_104
296 default 0x105 if FRAMEBUFFER_VESA_MODE_105
297 default 0x106 if FRAMEBUFFER_VESA_MODE_106
298 default 0x107 if FRAMEBUFFER_VESA_MODE_107
299 default 0x108 if FRAMEBUFFER_VESA_MODE_108
300 default 0x109 if FRAMEBUFFER_VESA_MODE_109
301 default 0x10A if FRAMEBUFFER_VESA_MODE_10A
302 default 0x10B if FRAMEBUFFER_VESA_MODE_10B
303 default 0x10C if FRAMEBUFFER_VESA_MODE_10C
304 default 0x10D if FRAMEBUFFER_VESA_MODE_10D
305 default 0x10E if FRAMEBUFFER_VESA_MODE_10E
306 default 0x10F if FRAMEBUFFER_VESA_MODE_10F
307 default 0x110 if FRAMEBUFFER_VESA_MODE_110
308 default 0x111 if FRAMEBUFFER_VESA_MODE_111
309 default 0x112 if FRAMEBUFFER_VESA_MODE_112
310 default 0x113 if FRAMEBUFFER_VESA_MODE_113
311 default 0x114 if FRAMEBUFFER_VESA_MODE_114
312 default 0x115 if FRAMEBUFFER_VESA_MODE_115
313 default 0x116 if FRAMEBUFFER_VESA_MODE_116
314 default 0x117 if FRAMEBUFFER_VESA_MODE_117
315 default 0x118 if FRAMEBUFFER_VESA_MODE_118
316 default 0x119 if FRAMEBUFFER_VESA_MODE_119
317 default 0x11A if FRAMEBUFFER_VESA_MODE_11A
318 default 0x11B if FRAMEBUFFER_VESA_MODE_11B
319 default 0x117 if FRAMEBUFFER_VESA_MODE_USER
324 bool "Add an Firmware Support Package binary"
326 Select this option to add an Firmware Support Package binary to
327 the resulting U-Boot image. It is a binary blob which U-Boot uses
328 to set up SDRAM and other chipset specific initialization.
330 Note: Without this binary U-Boot will not be able to set up its
331 SDRAM so will not boot.
334 string "Firmware Support Package binary filename"
338 The filename of the file to use as Firmware Support Package binary
339 in the board directory.
342 hex "Firmware Support Package binary location"
346 FSP is not Position Independent Code (PIC) and the whole FSP has to
347 be rebased if it is placed at a location which is different from the
348 perferred base address specified during the FSP build. Use Intel's
349 Binary Configuration Tool (BCT) to do the rebase.
351 The default base address of 0xfffc0000 indicates that the binary must
352 be located at offset 0xc0000 from the beginning of a 1MB flash device.
354 config FSP_TEMP_RAM_ADDR
358 Stack top address which is used in FspInit after DRAM is ready and
361 source "arch/x86/cpu/baytrail/Kconfig"
363 source "arch/x86/cpu/coreboot/Kconfig"
365 source "arch/x86/cpu/ivybridge/Kconfig"
367 source "arch/x86/cpu/quark/Kconfig"
369 source "arch/x86/cpu/queensbay/Kconfig"
371 config TSC_CALIBRATION_BYPASS
372 bool "Bypass Time-Stamp Counter (TSC) calibration"
375 By default U-Boot automatically calibrates Time-Stamp Counter (TSC)
376 running frequency via Model-Specific Register (MSR) and Programmable
377 Interval Timer (PIT). If the calibration does not work on your board,
378 select this option and provide a hardcoded TSC running frequency with
379 CONFIG_TSC_FREQ_IN_MHZ below.
381 Normally this option should be turned on in a simulation environment
384 config TSC_FREQ_IN_MHZ
385 int "Time-Stamp Counter (TSC) running frequency in MHz"
386 depends on TSC_CALIBRATION_BYPASS
389 The running frequency in MHz of Time-Stamp Counter (TSC).
393 config GENERATE_PIRQ_TABLE
394 bool "Generate a PIRQ table"
397 Generate a PIRQ routing table for this board. The PIRQ routing table
398 is generated by U-Boot in the system memory from 0xf0000 to 0xfffff
399 at every 16-byte boundary with a PCI IRQ routing signature ("$PIR").
400 It specifies the interrupt router information as well how all the PCI
401 devices' interrupt pins are wired to PIRQs.
405 config MAX_PIRQ_LINKS
409 This variable specifies the number of PIRQ interrupt links which are
410 routable. On most older chipsets, this is 4, PIRQA through PIRQD.
411 Some newer chipsets offer more than four links, commonly up to PIRQH.
413 config IRQ_SLOT_COUNT
417 U-Boot can support up to 254 IRQ slot info in the PIRQ routing table
418 which in turns forms a table of exact 4KiB. The default value 128
419 should be enough for most boards. If this does not fit your board,
420 change it according to your needs.
422 config PCIE_ECAM_BASE
426 This is the memory-mapped address of PCI configuration space, which
427 is only available through the Enhanced Configuration Access
428 Mechanism (ECAM) with PCI Express. It can be set up almost
429 anywhere. Before it is set up, it is possible to access PCI
430 configuration space through I/O access, but memory access is more
431 convenient. Using this, PCI can be scanned and configured. This
432 should be set to a region that does not conflict with memory
433 assigned to PCI devices - i.e. the memory and prefetch regions, as
434 passed to pci_set_region().
439 config BOOTSTAGE_REPORT