1 menu "x86 architecture"
8 prompt "Mainboard vendor"
9 default VENDOR_EMULATION
11 config VENDOR_COREBOOT
17 config VENDOR_EMULATION
28 # board-specific options below
29 source "board/coreboot/Kconfig"
30 source "board/efi/Kconfig"
31 source "board/emulation/Kconfig"
32 source "board/google/Kconfig"
33 source "board/intel/Kconfig"
35 # platform-specific options below
36 source "arch/x86/cpu/baytrail/Kconfig"
37 source "arch/x86/cpu/coreboot/Kconfig"
38 source "arch/x86/cpu/ivybridge/Kconfig"
39 source "arch/x86/cpu/qemu/Kconfig"
40 source "arch/x86/cpu/quark/Kconfig"
41 source "arch/x86/cpu/queensbay/Kconfig"
43 # architecture-specific options below
45 config SYS_MALLOC_F_LEN
54 depends on X86_RESET_VECTOR
63 default 0xfed00000 if !HPET_ADDRESS_OVERRIDE
72 config X86_RESET_VECTOR
76 config RESET_SEG_START
78 depends on X86_RESET_VECTOR
83 depends on X86_RESET_VECTOR
88 depends on X86_RESET_VECTOR
91 config SYS_X86_START16
93 depends on X86_RESET_VECTOR
96 config BOARD_ROMSIZE_KB_512
98 config BOARD_ROMSIZE_KB_1024
100 config BOARD_ROMSIZE_KB_2048
102 config BOARD_ROMSIZE_KB_4096
104 config BOARD_ROMSIZE_KB_8192
106 config BOARD_ROMSIZE_KB_16384
110 prompt "ROM chip size"
111 depends on X86_RESET_VECTOR
112 default UBOOT_ROMSIZE_KB_512 if BOARD_ROMSIZE_KB_512
113 default UBOOT_ROMSIZE_KB_1024 if BOARD_ROMSIZE_KB_1024
114 default UBOOT_ROMSIZE_KB_2048 if BOARD_ROMSIZE_KB_2048
115 default UBOOT_ROMSIZE_KB_4096 if BOARD_ROMSIZE_KB_4096
116 default UBOOT_ROMSIZE_KB_8192 if BOARD_ROMSIZE_KB_8192
117 default UBOOT_ROMSIZE_KB_16384 if BOARD_ROMSIZE_KB_16384
119 Select the size of the ROM chip you intend to flash U-Boot on.
121 The build system will take care of creating a u-boot.rom file
122 of the matching size.
124 config UBOOT_ROMSIZE_KB_512
127 Choose this option if you have a 512 KB ROM chip.
129 config UBOOT_ROMSIZE_KB_1024
130 bool "1024 KB (1 MB)"
132 Choose this option if you have a 1024 KB (1 MB) ROM chip.
134 config UBOOT_ROMSIZE_KB_2048
135 bool "2048 KB (2 MB)"
137 Choose this option if you have a 2048 KB (2 MB) ROM chip.
139 config UBOOT_ROMSIZE_KB_4096
140 bool "4096 KB (4 MB)"
142 Choose this option if you have a 4096 KB (4 MB) ROM chip.
144 config UBOOT_ROMSIZE_KB_8192
145 bool "8192 KB (8 MB)"
147 Choose this option if you have a 8192 KB (8 MB) ROM chip.
149 config UBOOT_ROMSIZE_KB_16384
150 bool "16384 KB (16 MB)"
152 Choose this option if you have a 16384 KB (16 MB) ROM chip.
156 # Map the config names to an integer (KB).
157 config UBOOT_ROMSIZE_KB
159 default 512 if UBOOT_ROMSIZE_KB_512
160 default 1024 if UBOOT_ROMSIZE_KB_1024
161 default 2048 if UBOOT_ROMSIZE_KB_2048
162 default 4096 if UBOOT_ROMSIZE_KB_4096
163 default 8192 if UBOOT_ROMSIZE_KB_8192
164 default 16384 if UBOOT_ROMSIZE_KB_16384
166 # Map the config names to a hex value (bytes).
169 default 0x80000 if UBOOT_ROMSIZE_KB_512
170 default 0x100000 if UBOOT_ROMSIZE_KB_1024
171 default 0x200000 if UBOOT_ROMSIZE_KB_2048
172 default 0x400000 if UBOOT_ROMSIZE_KB_4096
173 default 0x800000 if UBOOT_ROMSIZE_KB_8192
174 default 0xc00000 if UBOOT_ROMSIZE_KB_12288
175 default 0x1000000 if UBOOT_ROMSIZE_KB_16384
178 bool "Platform requires Intel Management Engine"
180 Newer higher-end devices have an Intel Management Engine (ME)
181 which is a very large binary blob (typically 1.5MB) which is
182 required for the platform to work. This enforces a particular
183 SPI flash format. You will need to supply the me.bin file in
184 your board directory.
187 bool "Perform a simple RAM test after SDRAM initialisation"
189 If there is something wrong with SDRAM then the platform will
190 often crash within U-Boot or the kernel. This option enables a
191 very simple RAM test that quickly checks whether the SDRAM seems
192 to work correctly. It is not exhaustive but can save time by
193 detecting obvious failures.
196 bool "Add an Firmware Support Package binary"
199 Select this option to add an Firmware Support Package binary to
200 the resulting U-Boot image. It is a binary blob which U-Boot uses
201 to set up SDRAM and other chipset specific initialization.
203 Note: Without this binary U-Boot will not be able to set up its
204 SDRAM so will not boot.
207 string "Firmware Support Package binary filename"
211 The filename of the file to use as Firmware Support Package binary
212 in the board directory.
215 hex "Firmware Support Package binary location"
219 FSP is not Position Independent Code (PIC) and the whole FSP has to
220 be rebased if it is placed at a location which is different from the
221 perferred base address specified during the FSP build. Use Intel's
222 Binary Configuration Tool (BCT) to do the rebase.
224 The default base address of 0xfffc0000 indicates that the binary must
225 be located at offset 0xc0000 from the beginning of a 1MB flash device.
227 config FSP_TEMP_RAM_ADDR
232 Stack top address which is used in fsp_init() after DRAM is ready and
235 config FSP_SYS_MALLOC_F_LEN
240 Additional size of malloc() pool before relocation.
242 config ENABLE_MRC_CACHE
243 bool "Enable MRC cache"
244 depends on !EFI && !SYS_COREBOOT
246 Enable this feature to cause MRC data to be cached in NV storage
247 to be used for speeding up boot time on future reboots and/or
251 bool "Enable Symmetric Multiprocessing"
254 Enable use of more than one CPU in U-Boot and the Operating System
255 when loaded. Each CPU will be started up and information can be
256 obtained using the 'cpu' command. If this option is disabled, then
257 only one CPU will be enabled regardless of the number of CPUs
261 int "Maximum number of CPUs permitted"
265 When using multi-CPU chips it is possible for U-Boot to start up
266 more than one CPU. The stack memory used by all of these CPUs is
267 pre-allocated so at present U-Boot wants to know the maximum
268 number of CPUs that may be present. Set this to at least as high
269 as the number of CPUs in your system (it uses about 4KB of RAM for
277 Each additional CPU started by U-Boot requires its own stack. This
278 option sets the stack size used by each CPU and directly affects
279 the memory used by this initialisation process. Typically 4KB is
282 config TSC_CALIBRATION_BYPASS
283 bool "Bypass Time-Stamp Counter (TSC) calibration"
286 By default U-Boot automatically calibrates Time-Stamp Counter (TSC)
287 running frequency via Model-Specific Register (MSR) and Programmable
288 Interval Timer (PIT). If the calibration does not work on your board,
289 select this option and provide a hardcoded TSC running frequency with
290 CONFIG_TSC_FREQ_IN_MHZ below.
292 Normally this option should be turned on in a simulation environment
295 config TSC_FREQ_IN_MHZ
296 int "Time-Stamp Counter (TSC) running frequency in MHz"
297 depends on TSC_CALIBRATION_BYPASS
300 The running frequency in MHz of Time-Stamp Counter (TSC).
303 bool "Add a VGA BIOS image"
305 Select this option if you have a VGA BIOS image that you would
306 like to add to your ROM.
309 string "VGA BIOS image filename"
310 depends on HAVE_VGA_BIOS
313 The filename of the VGA BIOS image in the board directory.
316 hex "VGA BIOS image location"
317 depends on HAVE_VGA_BIOS
320 The location of VGA BIOS image in the SPI flash. For example, base
321 address of 0xfff90000 indicates that the image will be put at offset
322 0x90000 from the beginning of a 1MB flash device.
325 depends on !EFI && !SYS_COREBOOT
327 config GENERATE_PIRQ_TABLE
328 bool "Generate a PIRQ table"
331 Generate a PIRQ routing table for this board. The PIRQ routing table
332 is generated by U-Boot in the system memory from 0xf0000 to 0xfffff
333 at every 16-byte boundary with a PCI IRQ routing signature ("$PIR").
334 It specifies the interrupt router information as well how all the PCI
335 devices' interrupt pins are wired to PIRQs.
337 config GENERATE_SFI_TABLE
338 bool "Generate a SFI (Simple Firmware Interface) table"
340 The Simple Firmware Interface (SFI) provides a lightweight method
341 for platform firmware to pass information to the operating system
342 via static tables in memory. Kernel SFI support is required to
343 boot on SFI-only platforms. If you have ACPI tables then these are
346 U-Boot writes this table in write_sfi_table() just before booting
349 For more information, see http://simplefirmware.org
351 config GENERATE_MP_TABLE
352 bool "Generate an MP (Multi-Processor) table"
355 Generate an MP (Multi-Processor) table for this board. The MP table
356 provides a way for the operating system to support for symmetric
357 multiprocessing as well as symmetric I/O interrupt handling with
358 the local APIC and I/O APIC.
360 config GENERATE_ACPI_TABLE
361 bool "Generate an ACPI (Advanced Configuration and Power Interface) table"
364 The Advanced Configuration and Power Interface (ACPI) specification
365 provides an open standard for device configuration and management
366 by the operating system. It defines platform-independent interfaces
367 for configuration and power management monitoring.
369 config GENERATE_SMBIOS_TABLE
370 bool "Generate an SMBIOS (System Management BIOS) table"
373 The System Management BIOS (SMBIOS) specification addresses how
374 motherboard and system vendors present management information about
375 their products in a standard format by extending the BIOS interface
376 on Intel architecture systems.
378 Check http://www.dmtf.org/standards/smbios for details.
382 config MAX_PIRQ_LINKS
386 This variable specifies the number of PIRQ interrupt links which are
387 routable. On most older chipsets, this is 4, PIRQA through PIRQD.
388 Some newer chipsets offer more than four links, commonly up to PIRQH.
390 config IRQ_SLOT_COUNT
394 U-Boot can support up to 254 IRQ slot info in the PIRQ routing table
395 which in turns forms a table of exact 4KiB. The default value 128
396 should be enough for most boards. If this does not fit your board,
397 change it according to your needs.
399 config PCIE_ECAM_BASE
403 This is the memory-mapped address of PCI configuration space, which
404 is only available through the Enhanced Configuration Access
405 Mechanism (ECAM) with PCI Express. It can be set up almost
406 anywhere. Before it is set up, it is possible to access PCI
407 configuration space through I/O access, but memory access is more
408 convenient. Using this, PCI can be scanned and configured. This
409 should be set to a region that does not conflict with memory
410 assigned to PCI devices - i.e. the memory and prefetch regions, as
411 passed to pci_set_region().
413 config PCIE_ECAM_SIZE
417 This is the size of memory-mapped address of PCI configuration space,
418 which is only available through the Enhanced Configuration Access
419 Mechanism (ECAM) with PCI Express. Each bus consumes 1 MiB memory,
420 so a default 0x10000000 size covers all of the 256 buses which is the
421 maximum number of PCI buses as defined by the PCI specification.
423 source "arch/x86/lib/efi/Kconfig"