2 * Copyright (c) 2011 The Chromium OS Authors.
3 * (C) Copyright 2008,2009
4 * Graeme Russ, <graeme.russ@gmail.com>
7 * Daniel Engström, Omicron Ceti AB, <daniel@omicron.se>
9 * SPDX-License-Identifier: GPL-2.0+
16 static struct pci_controller coreboot_hose;
18 static void config_pci_bridge(struct pci_controller *hose, pci_dev_t dev,
19 struct pci_config_table *table)
22 hose->read_byte(hose, dev, PCI_SECONDARY_BUS, &secondary);
23 hose->last_busno = max(hose->last_busno, secondary);
24 pci_hose_scan_bus(hose, secondary);
27 static struct pci_config_table pci_coreboot_config_table[] = {
28 /* vendor, device, class, bus, dev, func */
29 { PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_BRIDGE_PCI,
30 PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, &config_pci_bridge },
34 void pci_init_board(void)
36 coreboot_hose.config_table = pci_coreboot_config_table;
37 coreboot_hose.first_busno = 0;
38 coreboot_hose.last_busno = 0;
40 pci_set_region(coreboot_hose.regions + 0, 0x0, 0x0, 0xffffffff,
42 coreboot_hose.region_count = 1;
44 pci_setup_type1(&coreboot_hose);
46 pci_register_hose(&coreboot_hose);
48 pci_hose_scan(&coreboot_hose);