2 * (C) Copyright 2008-2011
3 * Graeme Russ, <graeme.russ@gmail.com>
6 * Daniel Engström, Omicron Ceti AB, <daniel@omicron.se>
9 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
10 * Marius Groeger <mgroeger@sysgo.de>
13 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
14 * Alex Zuepke <azu@sysgo.de>
16 * Part of this file is adapted from coreboot
17 * src/arch/x86/lib/cpu.c
19 * SPDX-License-Identifier: GPL-2.0+
26 #include <asm/control_regs.h>
29 #include <asm/processor.h>
30 #include <asm/processor-flags.h>
31 #include <asm/interrupt.h>
32 #include <asm/tables.h>
33 #include <linux/compiler.h>
35 DECLARE_GLOBAL_DATA_PTR;
38 * Constructor for a conventional segment GDT (or LDT) entry
39 * This is a macro so it can be used in initialisers
41 #define GDT_ENTRY(flags, base, limit) \
42 ((((base) & 0xff000000ULL) << (56-24)) | \
43 (((flags) & 0x0000f0ffULL) << 40) | \
44 (((limit) & 0x000f0000ULL) << (48-16)) | \
45 (((base) & 0x00ffffffULL) << 16) | \
46 (((limit) & 0x0000ffffULL)))
53 struct cpu_device_id {
59 uint8_t x86; /* CPU family */
60 uint8_t x86_vendor; /* CPU vendor */
66 * List of cpu vendor strings along with their normalized
73 { X86_VENDOR_INTEL, "GenuineIntel", },
74 { X86_VENDOR_CYRIX, "CyrixInstead", },
75 { X86_VENDOR_AMD, "AuthenticAMD", },
76 { X86_VENDOR_UMC, "UMC UMC UMC ", },
77 { X86_VENDOR_NEXGEN, "NexGenDriven", },
78 { X86_VENDOR_CENTAUR, "CentaurHauls", },
79 { X86_VENDOR_RISE, "RiseRiseRise", },
80 { X86_VENDOR_TRANSMETA, "GenuineTMx86", },
81 { X86_VENDOR_TRANSMETA, "TransmetaCPU", },
82 { X86_VENDOR_NSC, "Geode by NSC", },
83 { X86_VENDOR_SIS, "SiS SiS SiS ", },
86 static const char *const x86_vendor_name[] = {
87 [X86_VENDOR_INTEL] = "Intel",
88 [X86_VENDOR_CYRIX] = "Cyrix",
89 [X86_VENDOR_AMD] = "AMD",
90 [X86_VENDOR_UMC] = "UMC",
91 [X86_VENDOR_NEXGEN] = "NexGen",
92 [X86_VENDOR_CENTAUR] = "Centaur",
93 [X86_VENDOR_RISE] = "Rise",
94 [X86_VENDOR_TRANSMETA] = "Transmeta",
95 [X86_VENDOR_NSC] = "NSC",
96 [X86_VENDOR_SIS] = "SiS",
99 static void load_ds(u32 segment)
101 asm volatile("movl %0, %%ds" : : "r" (segment * X86_GDT_ENTRY_SIZE));
104 static void load_es(u32 segment)
106 asm volatile("movl %0, %%es" : : "r" (segment * X86_GDT_ENTRY_SIZE));
109 static void load_fs(u32 segment)
111 asm volatile("movl %0, %%fs" : : "r" (segment * X86_GDT_ENTRY_SIZE));
114 static void load_gs(u32 segment)
116 asm volatile("movl %0, %%gs" : : "r" (segment * X86_GDT_ENTRY_SIZE));
119 static void load_ss(u32 segment)
121 asm volatile("movl %0, %%ss" : : "r" (segment * X86_GDT_ENTRY_SIZE));
124 static void load_gdt(const u64 *boot_gdt, u16 num_entries)
128 gdt.len = (num_entries * X86_GDT_ENTRY_SIZE) - 1;
129 gdt.ptr = (u32)boot_gdt;
131 asm volatile("lgdtl %0\n" : : "m" (gdt));
134 void setup_gdt(gd_t *id, u64 *gdt_addr)
136 id->arch.gdt = gdt_addr;
137 /* CS: code, read/execute, 4 GB, base 0 */
138 gdt_addr[X86_GDT_ENTRY_32BIT_CS] = GDT_ENTRY(0xc09b, 0, 0xfffff);
140 /* DS: data, read/write, 4 GB, base 0 */
141 gdt_addr[X86_GDT_ENTRY_32BIT_DS] = GDT_ENTRY(0xc093, 0, 0xfffff);
143 /* FS: data, read/write, 4 GB, base (Global Data Pointer) */
144 id->arch.gd_addr = id;
145 gdt_addr[X86_GDT_ENTRY_32BIT_FS] = GDT_ENTRY(0xc093,
146 (ulong)&id->arch.gd_addr, 0xfffff);
148 /* 16-bit CS: code, read/execute, 64 kB, base 0 */
149 gdt_addr[X86_GDT_ENTRY_16BIT_CS] = GDT_ENTRY(0x009b, 0, 0x0ffff);
151 /* 16-bit DS: data, read/write, 64 kB, base 0 */
152 gdt_addr[X86_GDT_ENTRY_16BIT_DS] = GDT_ENTRY(0x0093, 0, 0x0ffff);
154 gdt_addr[X86_GDT_ENTRY_16BIT_FLAT_CS] = GDT_ENTRY(0x809b, 0, 0xfffff);
155 gdt_addr[X86_GDT_ENTRY_16BIT_FLAT_DS] = GDT_ENTRY(0x8093, 0, 0xfffff);
157 load_gdt(gdt_addr, X86_GDT_NUM_ENTRIES);
158 load_ds(X86_GDT_ENTRY_32BIT_DS);
159 load_es(X86_GDT_ENTRY_32BIT_DS);
160 load_gs(X86_GDT_ENTRY_32BIT_DS);
161 load_ss(X86_GDT_ENTRY_32BIT_DS);
162 load_fs(X86_GDT_ENTRY_32BIT_FS);
165 int __weak x86_cleanup_before_linux(void)
167 #ifdef CONFIG_BOOTSTAGE_STASH
168 bootstage_stash((void *)CONFIG_BOOTSTAGE_STASH_ADDR,
169 CONFIG_BOOTSTAGE_STASH_SIZE);
176 * Cyrix CPUs without cpuid or with cpuid not yet enabled can be detected
177 * by the fact that they preserve the flags across the division of 5/2.
178 * PII and PPro exhibit this behavior too, but they have cpuid available.
182 * Perform the Cyrix 5/2 test. A Cyrix won't change
183 * the flags, while other 486 chips will.
185 static inline int test_cyrix_52div(void)
189 __asm__ __volatile__(
190 "sahf\n\t" /* clear flags (%eax = 0x0005) */
191 "div %b2\n\t" /* divide 5 by 2 */
192 "lahf" /* store flags into %ah */
197 /* AH is 0x02 on Cyrix after the divide.. */
198 return (unsigned char) (test >> 8) == 0x02;
202 * Detect a NexGen CPU running without BIOS hypercode new enough
203 * to have CPUID. (Thanks to Herbert Oppmann)
206 static int deep_magic_nexgen_probe(void)
210 __asm__ __volatile__ (
211 " movw $0x5555, %%ax\n"
219 : "=a" (ret) : : "cx", "dx");
223 static bool has_cpuid(void)
225 return flag_is_changeable_p(X86_EFLAGS_ID);
228 static bool has_mtrr(void)
230 return cpuid_edx(0x00000001) & (1 << 12) ? true : false;
233 static int build_vendor_name(char *vendor_name)
235 struct cpuid_result result;
236 result = cpuid(0x00000000);
237 unsigned int *name_as_ints = (unsigned int *)vendor_name;
239 name_as_ints[0] = result.ebx;
240 name_as_ints[1] = result.edx;
241 name_as_ints[2] = result.ecx;
246 static void identify_cpu(struct cpu_device_id *cpu)
248 char vendor_name[16];
251 vendor_name[0] = '\0'; /* Unset */
252 cpu->device = 0; /* fix gcc 4.4.4 warning */
254 /* Find the id and vendor_name */
256 /* Its a 486 if we can modify the AC flag */
257 if (flag_is_changeable_p(X86_EFLAGS_AC))
258 cpu->device = 0x00000400; /* 486 */
260 cpu->device = 0x00000300; /* 386 */
261 if ((cpu->device == 0x00000400) && test_cyrix_52div()) {
262 memcpy(vendor_name, "CyrixInstead", 13);
263 /* If we ever care we can enable cpuid here */
265 /* Detect NexGen with old hypercode */
266 else if (deep_magic_nexgen_probe())
267 memcpy(vendor_name, "NexGenDriven", 13);
272 cpuid_level = build_vendor_name(vendor_name);
273 vendor_name[12] = '\0';
275 /* Intel-defined flags: level 0x00000001 */
276 if (cpuid_level >= 0x00000001) {
277 cpu->device = cpuid_eax(0x00000001);
279 /* Have CPUID level 0 only unheard of */
280 cpu->device = 0x00000400;
283 cpu->vendor = X86_VENDOR_UNKNOWN;
284 for (i = 0; i < ARRAY_SIZE(x86_vendors); i++) {
285 if (memcmp(vendor_name, x86_vendors[i].name, 12) == 0) {
286 cpu->vendor = x86_vendors[i].vendor;
292 static inline void get_fms(struct cpuinfo_x86 *c, uint32_t tfms)
294 c->x86 = (tfms >> 8) & 0xf;
295 c->x86_model = (tfms >> 4) & 0xf;
296 c->x86_mask = tfms & 0xf;
298 c->x86 += (tfms >> 20) & 0xff;
300 c->x86_model += ((tfms >> 16) & 0xF) << 4;
303 int x86_cpu_init_f(void)
305 const u32 em_rst = ~X86_CR0_EM;
306 const u32 mp_ne_set = X86_CR0_MP | X86_CR0_NE;
308 /* initialize FPU, reset EM, set MP and NE */
310 "movl %%cr0, %%eax\n" \
313 "movl %%eax, %%cr0\n" \
314 : : "i" (em_rst), "i" (mp_ne_set) : "eax");
316 /* identify CPU via cpuid and store the decoded info into gd->arch */
318 struct cpu_device_id cpu;
319 struct cpuinfo_x86 c;
322 get_fms(&c, cpu.device);
323 gd->arch.x86 = c.x86;
324 gd->arch.x86_vendor = cpu.vendor;
325 gd->arch.x86_model = c.x86_model;
326 gd->arch.x86_mask = c.x86_mask;
327 gd->arch.x86_device = cpu.device;
329 gd->arch.has_mtrr = has_mtrr();
335 void x86_enable_caches(void)
340 cr0 &= ~(X86_CR0_NW | X86_CR0_CD);
344 void enable_caches(void) __attribute__((weak, alias("x86_enable_caches")));
346 void x86_disable_caches(void)
351 cr0 |= X86_CR0_NW | X86_CR0_CD;
356 void disable_caches(void) __attribute__((weak, alias("x86_disable_caches")));
358 int x86_init_cache(void)
364 int init_cache(void) __attribute__((weak, alias("x86_init_cache")));
366 int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
368 printf("resetting ...\n");
372 disable_interrupts();
379 void flush_cache(unsigned long dummy1, unsigned long dummy2)
384 __weak void reset_cpu(ulong addr)
386 /* Do a hard reset through the chipset's reset control register */
387 outb(SYS_RST | RST_CPU, PORT_RESET);
392 void x86_full_reset(void)
394 outb(FULL_RST | SYS_RST | RST_CPU, PORT_RESET);
397 int dcache_status(void)
399 return !(read_cr0() & 0x40000000);
402 /* Define these functions to allow ehch-hcd to function */
403 void flush_dcache_range(unsigned long start, unsigned long stop)
407 void invalidate_dcache_range(unsigned long start, unsigned long stop)
411 void dcache_enable(void)
416 void dcache_disable(void)
421 void icache_enable(void)
425 void icache_disable(void)
429 int icache_status(void)
434 void cpu_enable_paging_pae(ulong cr3)
436 __asm__ __volatile__(
437 /* Load the page table address */
440 "movl %%cr4, %%eax\n"
441 "orl $0x00000020, %%eax\n"
442 "movl %%eax, %%cr4\n"
444 "movl %%cr0, %%eax\n"
445 "orl $0x80000000, %%eax\n"
446 "movl %%eax, %%cr0\n"
452 void cpu_disable_paging_pae(void)
454 /* Turn off paging */
455 __asm__ __volatile__ (
457 "movl %%cr0, %%eax\n"
458 "andl $0x7fffffff, %%eax\n"
459 "movl %%eax, %%cr0\n"
461 "movl %%cr4, %%eax\n"
462 "andl $0xffffffdf, %%eax\n"
463 "movl %%eax, %%cr4\n"
469 static bool can_detect_long_mode(void)
471 return cpuid_eax(0x80000000) > 0x80000000UL;
474 static bool has_long_mode(void)
476 return cpuid_edx(0x80000001) & (1 << 29) ? true : false;
479 int cpu_has_64bit(void)
481 return has_cpuid() && can_detect_long_mode() &&
485 const char *cpu_vendor_name(int vendor)
488 name = "<invalid cpu vendor>";
489 if ((vendor < (ARRAY_SIZE(x86_vendor_name))) &&
490 (x86_vendor_name[vendor] != 0))
491 name = x86_vendor_name[vendor];
496 char *cpu_get_name(char *name)
498 unsigned int *name_as_ints = (unsigned int *)name;
499 struct cpuid_result regs;
503 /* This bit adds up to 48 bytes */
504 for (i = 0; i < 3; i++) {
505 regs = cpuid(0x80000002 + i);
506 name_as_ints[i * 4 + 0] = regs.eax;
507 name_as_ints[i * 4 + 1] = regs.ebx;
508 name_as_ints[i * 4 + 2] = regs.ecx;
509 name_as_ints[i * 4 + 3] = regs.edx;
511 name[CPU_MAX_NAME_LEN - 1] = '\0';
513 /* Skip leading spaces. */
521 int default_print_cpuinfo(void)
523 printf("CPU: %s, vendor %s, device %xh\n",
524 cpu_has_64bit() ? "x86_64" : "x86",
525 cpu_vendor_name(gd->arch.x86_vendor), gd->arch.x86_device);
530 #define PAGETABLE_SIZE (6 * 4096)
533 * build_pagetable() - build a flat 4GiB page table structure for 64-bti mode
535 * @pgtable: Pointer to a 24iKB block of memory
537 static void build_pagetable(uint32_t *pgtable)
541 memset(pgtable, '\0', PAGETABLE_SIZE);
543 /* Level 4 needs a single entry */
544 pgtable[0] = (uint32_t)&pgtable[1024] + 7;
546 /* Level 3 has one 64-bit entry for each GiB of memory */
547 for (i = 0; i < 4; i++) {
548 pgtable[1024 + i * 2] = (uint32_t)&pgtable[2048] +
552 /* Level 2 has 2048 64-bit entries, each repesenting 2MiB */
553 for (i = 0; i < 2048; i++)
554 pgtable[2048 + i * 2] = 0x183 + (i << 21UL);
557 int cpu_jump_to_64bit(ulong setup_base, ulong target)
561 pgtable = memalign(4096, PAGETABLE_SIZE);
565 build_pagetable(pgtable);
566 cpu_call64((ulong)pgtable, setup_base, target);
572 void show_boot_progress(int val)
574 #if MIN_PORT80_KCLOCKS_DELAY
576 * Scale the time counter reading to avoid using 64 bit arithmetics.
577 * Can't use get_timer() here becuase it could be not yet
578 * initialized or even implemented.
580 if (!gd->arch.tsc_prev) {
581 gd->arch.tsc_base_kclocks = rdtsc() / 1000;
582 gd->arch.tsc_prev = 0;
587 now = rdtsc() / 1000 - gd->arch.tsc_base_kclocks;
588 } while (now < (gd->arch.tsc_prev + MIN_PORT80_KCLOCKS_DELAY));
589 gd->arch.tsc_prev = now;
592 outb(val, POST_PORT);
595 #ifndef CONFIG_SYS_COREBOOT
596 int last_stage_init(void)