2 * (C) Copyright 2008-2011
3 * Graeme Russ, <graeme.russ@gmail.com>
6 * Daniel Engström, Omicron Ceti AB, <daniel@omicron.se>
9 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
10 * Marius Groeger <mgroeger@sysgo.de>
13 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
14 * Alex Zuepke <azu@sysgo.de>
16 * Part of this file is adapted from coreboot
17 * src/arch/x86/lib/cpu.c
19 * SPDX-License-Identifier: GPL-2.0+
27 #include <asm/control_regs.h>
29 #include <asm/lapic.h>
34 #include <asm/processor.h>
35 #include <asm/processor-flags.h>
36 #include <asm/interrupt.h>
37 #include <asm/tables.h>
38 #include <linux/compiler.h>
40 DECLARE_GLOBAL_DATA_PTR;
43 * Constructor for a conventional segment GDT (or LDT) entry
44 * This is a macro so it can be used in initialisers
46 #define GDT_ENTRY(flags, base, limit) \
47 ((((base) & 0xff000000ULL) << (56-24)) | \
48 (((flags) & 0x0000f0ffULL) << 40) | \
49 (((limit) & 0x000f0000ULL) << (48-16)) | \
50 (((base) & 0x00ffffffULL) << 16) | \
51 (((limit) & 0x0000ffffULL)))
58 struct cpu_device_id {
64 uint8_t x86; /* CPU family */
65 uint8_t x86_vendor; /* CPU vendor */
71 * List of cpu vendor strings along with their normalized
78 { X86_VENDOR_INTEL, "GenuineIntel", },
79 { X86_VENDOR_CYRIX, "CyrixInstead", },
80 { X86_VENDOR_AMD, "AuthenticAMD", },
81 { X86_VENDOR_UMC, "UMC UMC UMC ", },
82 { X86_VENDOR_NEXGEN, "NexGenDriven", },
83 { X86_VENDOR_CENTAUR, "CentaurHauls", },
84 { X86_VENDOR_RISE, "RiseRiseRise", },
85 { X86_VENDOR_TRANSMETA, "GenuineTMx86", },
86 { X86_VENDOR_TRANSMETA, "TransmetaCPU", },
87 { X86_VENDOR_NSC, "Geode by NSC", },
88 { X86_VENDOR_SIS, "SiS SiS SiS ", },
91 static const char *const x86_vendor_name[] = {
92 [X86_VENDOR_INTEL] = "Intel",
93 [X86_VENDOR_CYRIX] = "Cyrix",
94 [X86_VENDOR_AMD] = "AMD",
95 [X86_VENDOR_UMC] = "UMC",
96 [X86_VENDOR_NEXGEN] = "NexGen",
97 [X86_VENDOR_CENTAUR] = "Centaur",
98 [X86_VENDOR_RISE] = "Rise",
99 [X86_VENDOR_TRANSMETA] = "Transmeta",
100 [X86_VENDOR_NSC] = "NSC",
101 [X86_VENDOR_SIS] = "SiS",
104 static void load_ds(u32 segment)
106 asm volatile("movl %0, %%ds" : : "r" (segment * X86_GDT_ENTRY_SIZE));
109 static void load_es(u32 segment)
111 asm volatile("movl %0, %%es" : : "r" (segment * X86_GDT_ENTRY_SIZE));
114 static void load_fs(u32 segment)
116 asm volatile("movl %0, %%fs" : : "r" (segment * X86_GDT_ENTRY_SIZE));
119 static void load_gs(u32 segment)
121 asm volatile("movl %0, %%gs" : : "r" (segment * X86_GDT_ENTRY_SIZE));
124 static void load_ss(u32 segment)
126 asm volatile("movl %0, %%ss" : : "r" (segment * X86_GDT_ENTRY_SIZE));
129 static void load_gdt(const u64 *boot_gdt, u16 num_entries)
133 gdt.len = (num_entries * X86_GDT_ENTRY_SIZE) - 1;
134 gdt.ptr = (u32)boot_gdt;
136 asm volatile("lgdtl %0\n" : : "m" (gdt));
139 void setup_gdt(gd_t *id, u64 *gdt_addr)
141 id->arch.gdt = gdt_addr;
142 /* CS: code, read/execute, 4 GB, base 0 */
143 gdt_addr[X86_GDT_ENTRY_32BIT_CS] = GDT_ENTRY(0xc09b, 0, 0xfffff);
145 /* DS: data, read/write, 4 GB, base 0 */
146 gdt_addr[X86_GDT_ENTRY_32BIT_DS] = GDT_ENTRY(0xc093, 0, 0xfffff);
148 /* FS: data, read/write, 4 GB, base (Global Data Pointer) */
149 id->arch.gd_addr = id;
150 gdt_addr[X86_GDT_ENTRY_32BIT_FS] = GDT_ENTRY(0xc093,
151 (ulong)&id->arch.gd_addr, 0xfffff);
153 /* 16-bit CS: code, read/execute, 64 kB, base 0 */
154 gdt_addr[X86_GDT_ENTRY_16BIT_CS] = GDT_ENTRY(0x009b, 0, 0x0ffff);
156 /* 16-bit DS: data, read/write, 64 kB, base 0 */
157 gdt_addr[X86_GDT_ENTRY_16BIT_DS] = GDT_ENTRY(0x0093, 0, 0x0ffff);
159 gdt_addr[X86_GDT_ENTRY_16BIT_FLAT_CS] = GDT_ENTRY(0x809b, 0, 0xfffff);
160 gdt_addr[X86_GDT_ENTRY_16BIT_FLAT_DS] = GDT_ENTRY(0x8093, 0, 0xfffff);
162 load_gdt(gdt_addr, X86_GDT_NUM_ENTRIES);
163 load_ds(X86_GDT_ENTRY_32BIT_DS);
164 load_es(X86_GDT_ENTRY_32BIT_DS);
165 load_gs(X86_GDT_ENTRY_32BIT_DS);
166 load_ss(X86_GDT_ENTRY_32BIT_DS);
167 load_fs(X86_GDT_ENTRY_32BIT_FS);
170 #ifdef CONFIG_HAVE_FSP
172 * Setup FSP execution environment GDT
174 * Per Intel FSP external architecture specification, before calling any FSP
175 * APIs, we need make sure the system is in flat 32-bit mode and both the code
176 * and data selectors should have full 4GB access range. Here we reuse the one
177 * we used in arch/x86/cpu/start16.S, and reload the segement registers.
179 void setup_fsp_gdt(void)
181 load_gdt((const u64 *)(gdt_rom + CONFIG_RESET_SEG_START), 4);
182 load_ds(X86_GDT_ENTRY_32BIT_DS);
183 load_ss(X86_GDT_ENTRY_32BIT_DS);
184 load_es(X86_GDT_ENTRY_32BIT_DS);
185 load_fs(X86_GDT_ENTRY_32BIT_DS);
186 load_gs(X86_GDT_ENTRY_32BIT_DS);
190 int __weak x86_cleanup_before_linux(void)
192 #ifdef CONFIG_BOOTSTAGE_STASH
193 bootstage_stash((void *)CONFIG_BOOTSTAGE_STASH_ADDR,
194 CONFIG_BOOTSTAGE_STASH_SIZE);
201 * Cyrix CPUs without cpuid or with cpuid not yet enabled can be detected
202 * by the fact that they preserve the flags across the division of 5/2.
203 * PII and PPro exhibit this behavior too, but they have cpuid available.
207 * Perform the Cyrix 5/2 test. A Cyrix won't change
208 * the flags, while other 486 chips will.
210 static inline int test_cyrix_52div(void)
214 __asm__ __volatile__(
215 "sahf\n\t" /* clear flags (%eax = 0x0005) */
216 "div %b2\n\t" /* divide 5 by 2 */
217 "lahf" /* store flags into %ah */
222 /* AH is 0x02 on Cyrix after the divide.. */
223 return (unsigned char) (test >> 8) == 0x02;
227 * Detect a NexGen CPU running without BIOS hypercode new enough
228 * to have CPUID. (Thanks to Herbert Oppmann)
231 static int deep_magic_nexgen_probe(void)
235 __asm__ __volatile__ (
236 " movw $0x5555, %%ax\n"
244 : "=a" (ret) : : "cx", "dx");
248 static bool has_cpuid(void)
250 return flag_is_changeable_p(X86_EFLAGS_ID);
253 static bool has_mtrr(void)
255 return cpuid_edx(0x00000001) & (1 << 12) ? true : false;
258 static int build_vendor_name(char *vendor_name)
260 struct cpuid_result result;
261 result = cpuid(0x00000000);
262 unsigned int *name_as_ints = (unsigned int *)vendor_name;
264 name_as_ints[0] = result.ebx;
265 name_as_ints[1] = result.edx;
266 name_as_ints[2] = result.ecx;
271 static void identify_cpu(struct cpu_device_id *cpu)
273 char vendor_name[16];
276 vendor_name[0] = '\0'; /* Unset */
277 cpu->device = 0; /* fix gcc 4.4.4 warning */
279 /* Find the id and vendor_name */
281 /* Its a 486 if we can modify the AC flag */
282 if (flag_is_changeable_p(X86_EFLAGS_AC))
283 cpu->device = 0x00000400; /* 486 */
285 cpu->device = 0x00000300; /* 386 */
286 if ((cpu->device == 0x00000400) && test_cyrix_52div()) {
287 memcpy(vendor_name, "CyrixInstead", 13);
288 /* If we ever care we can enable cpuid here */
290 /* Detect NexGen with old hypercode */
291 else if (deep_magic_nexgen_probe())
292 memcpy(vendor_name, "NexGenDriven", 13);
297 cpuid_level = build_vendor_name(vendor_name);
298 vendor_name[12] = '\0';
300 /* Intel-defined flags: level 0x00000001 */
301 if (cpuid_level >= 0x00000001) {
302 cpu->device = cpuid_eax(0x00000001);
304 /* Have CPUID level 0 only unheard of */
305 cpu->device = 0x00000400;
308 cpu->vendor = X86_VENDOR_UNKNOWN;
309 for (i = 0; i < ARRAY_SIZE(x86_vendors); i++) {
310 if (memcmp(vendor_name, x86_vendors[i].name, 12) == 0) {
311 cpu->vendor = x86_vendors[i].vendor;
317 static inline void get_fms(struct cpuinfo_x86 *c, uint32_t tfms)
319 c->x86 = (tfms >> 8) & 0xf;
320 c->x86_model = (tfms >> 4) & 0xf;
321 c->x86_mask = tfms & 0xf;
323 c->x86 += (tfms >> 20) & 0xff;
325 c->x86_model += ((tfms >> 16) & 0xF) << 4;
328 int x86_cpu_init_f(void)
330 const u32 em_rst = ~X86_CR0_EM;
331 const u32 mp_ne_set = X86_CR0_MP | X86_CR0_NE;
333 /* initialize FPU, reset EM, set MP and NE */
335 "movl %%cr0, %%eax\n" \
338 "movl %%eax, %%cr0\n" \
339 : : "i" (em_rst), "i" (mp_ne_set) : "eax");
341 /* identify CPU via cpuid and store the decoded info into gd->arch */
343 struct cpu_device_id cpu;
344 struct cpuinfo_x86 c;
347 get_fms(&c, cpu.device);
348 gd->arch.x86 = c.x86;
349 gd->arch.x86_vendor = cpu.vendor;
350 gd->arch.x86_model = c.x86_model;
351 gd->arch.x86_mask = c.x86_mask;
352 gd->arch.x86_device = cpu.device;
354 gd->arch.has_mtrr = has_mtrr();
356 /* Don't allow PCI region 3 to use memory in the 2-4GB memory hole */
357 gd->pci_ram_top = 0x80000000U;
359 /* Configure fixed range MTRRs for some legacy regions */
360 if (gd->arch.has_mtrr) {
363 mtrr_cap = native_read_msr(MTRR_CAP_MSR);
364 if (mtrr_cap & MTRR_CAP_FIX) {
365 /* Mark the VGA RAM area as uncacheable */
366 native_write_msr(MTRR_FIX_16K_A0000_MSR,
367 MTRR_FIX_TYPE(MTRR_TYPE_UNCACHEABLE),
368 MTRR_FIX_TYPE(MTRR_TYPE_UNCACHEABLE));
371 * Mark the PCI ROM area as cacheable to improve ROM
372 * execution performance.
374 native_write_msr(MTRR_FIX_4K_C0000_MSR,
375 MTRR_FIX_TYPE(MTRR_TYPE_WRBACK),
376 MTRR_FIX_TYPE(MTRR_TYPE_WRBACK));
377 native_write_msr(MTRR_FIX_4K_C8000_MSR,
378 MTRR_FIX_TYPE(MTRR_TYPE_WRBACK),
379 MTRR_FIX_TYPE(MTRR_TYPE_WRBACK));
380 native_write_msr(MTRR_FIX_4K_D0000_MSR,
381 MTRR_FIX_TYPE(MTRR_TYPE_WRBACK),
382 MTRR_FIX_TYPE(MTRR_TYPE_WRBACK));
383 native_write_msr(MTRR_FIX_4K_D8000_MSR,
384 MTRR_FIX_TYPE(MTRR_TYPE_WRBACK),
385 MTRR_FIX_TYPE(MTRR_TYPE_WRBACK));
387 /* Enable the fixed range MTRRs */
388 msr_setbits_64(MTRR_DEF_TYPE_MSR, MTRR_DEF_TYPE_FIX_EN);
395 void x86_enable_caches(void)
400 cr0 &= ~(X86_CR0_NW | X86_CR0_CD);
404 void enable_caches(void) __attribute__((weak, alias("x86_enable_caches")));
406 void x86_disable_caches(void)
411 cr0 |= X86_CR0_NW | X86_CR0_CD;
416 void disable_caches(void) __attribute__((weak, alias("x86_disable_caches")));
418 int x86_init_cache(void)
424 int init_cache(void) __attribute__((weak, alias("x86_init_cache")));
426 int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
428 printf("resetting ...\n");
432 disable_interrupts();
439 void flush_cache(unsigned long dummy1, unsigned long dummy2)
444 __weak void reset_cpu(ulong addr)
446 /* Do a hard reset through the chipset's reset control register */
447 outb(SYS_RST | RST_CPU, PORT_RESET);
452 void x86_full_reset(void)
454 outb(FULL_RST | SYS_RST | RST_CPU, PORT_RESET);
457 int dcache_status(void)
459 return !(read_cr0() & 0x40000000);
462 /* Define these functions to allow ehch-hcd to function */
463 void flush_dcache_range(unsigned long start, unsigned long stop)
467 void invalidate_dcache_range(unsigned long start, unsigned long stop)
471 void dcache_enable(void)
476 void dcache_disable(void)
481 void icache_enable(void)
485 void icache_disable(void)
489 int icache_status(void)
494 void cpu_enable_paging_pae(ulong cr3)
496 __asm__ __volatile__(
497 /* Load the page table address */
500 "movl %%cr4, %%eax\n"
501 "orl $0x00000020, %%eax\n"
502 "movl %%eax, %%cr4\n"
504 "movl %%cr0, %%eax\n"
505 "orl $0x80000000, %%eax\n"
506 "movl %%eax, %%cr0\n"
512 void cpu_disable_paging_pae(void)
514 /* Turn off paging */
515 __asm__ __volatile__ (
517 "movl %%cr0, %%eax\n"
518 "andl $0x7fffffff, %%eax\n"
519 "movl %%eax, %%cr0\n"
521 "movl %%cr4, %%eax\n"
522 "andl $0xffffffdf, %%eax\n"
523 "movl %%eax, %%cr4\n"
529 static bool can_detect_long_mode(void)
531 return cpuid_eax(0x80000000) > 0x80000000UL;
534 static bool has_long_mode(void)
536 return cpuid_edx(0x80000001) & (1 << 29) ? true : false;
539 int cpu_has_64bit(void)
541 return has_cpuid() && can_detect_long_mode() &&
545 const char *cpu_vendor_name(int vendor)
548 name = "<invalid cpu vendor>";
549 if ((vendor < (ARRAY_SIZE(x86_vendor_name))) &&
550 (x86_vendor_name[vendor] != 0))
551 name = x86_vendor_name[vendor];
556 char *cpu_get_name(char *name)
558 unsigned int *name_as_ints = (unsigned int *)name;
559 struct cpuid_result regs;
563 /* This bit adds up to 48 bytes */
564 for (i = 0; i < 3; i++) {
565 regs = cpuid(0x80000002 + i);
566 name_as_ints[i * 4 + 0] = regs.eax;
567 name_as_ints[i * 4 + 1] = regs.ebx;
568 name_as_ints[i * 4 + 2] = regs.ecx;
569 name_as_ints[i * 4 + 3] = regs.edx;
571 name[CPU_MAX_NAME_LEN - 1] = '\0';
573 /* Skip leading spaces. */
581 int default_print_cpuinfo(void)
583 printf("CPU: %s, vendor %s, device %xh\n",
584 cpu_has_64bit() ? "x86_64" : "x86",
585 cpu_vendor_name(gd->arch.x86_vendor), gd->arch.x86_device);
590 #define PAGETABLE_SIZE (6 * 4096)
593 * build_pagetable() - build a flat 4GiB page table structure for 64-bti mode
595 * @pgtable: Pointer to a 24iKB block of memory
597 static void build_pagetable(uint32_t *pgtable)
601 memset(pgtable, '\0', PAGETABLE_SIZE);
603 /* Level 4 needs a single entry */
604 pgtable[0] = (uint32_t)&pgtable[1024] + 7;
606 /* Level 3 has one 64-bit entry for each GiB of memory */
607 for (i = 0; i < 4; i++) {
608 pgtable[1024 + i * 2] = (uint32_t)&pgtable[2048] +
612 /* Level 2 has 2048 64-bit entries, each repesenting 2MiB */
613 for (i = 0; i < 2048; i++)
614 pgtable[2048 + i * 2] = 0x183 + (i << 21UL);
617 int cpu_jump_to_64bit(ulong setup_base, ulong target)
621 pgtable = memalign(4096, PAGETABLE_SIZE);
625 build_pagetable(pgtable);
626 cpu_call64((ulong)pgtable, setup_base, target);
632 void show_boot_progress(int val)
634 #if MIN_PORT80_KCLOCKS_DELAY
636 * Scale the time counter reading to avoid using 64 bit arithmetics.
637 * Can't use get_timer() here becuase it could be not yet
638 * initialized or even implemented.
640 if (!gd->arch.tsc_prev) {
641 gd->arch.tsc_base_kclocks = rdtsc() / 1000;
642 gd->arch.tsc_prev = 0;
647 now = rdtsc() / 1000 - gd->arch.tsc_base_kclocks;
648 } while (now < (gd->arch.tsc_prev + MIN_PORT80_KCLOCKS_DELAY));
649 gd->arch.tsc_prev = now;
652 outb(val, POST_PORT);
655 #ifndef CONFIG_SYS_COREBOOT
656 int last_stage_init(void)
665 static int enable_smis(struct udevice *cpu, void *unused)
670 static struct mp_flight_record mp_steps[] = {
671 MP_FR_BLOCK_APS(mp_init_cpu, NULL, mp_init_cpu, NULL),
672 /* Wait for APs to finish initialization before proceeding */
673 MP_FR_BLOCK_APS(NULL, NULL, enable_smis, NULL),
676 static int x86_mp_init(void)
678 struct mp_params mp_params;
680 mp_params.parallel_microcode_load = 0,
681 mp_params.flight_plan = &mp_steps[0];
682 mp_params.num_records = ARRAY_SIZE(mp_steps);
683 mp_params.microcode_pointer = 0;
685 if (mp_init(&mp_params)) {
686 printf("Warning: MP init failure\n");
694 __weak int x86_init_cpus(void)
697 debug("Init additional CPUs\n");
706 return x86_init_cpus();