2 * (C) Copyright 2008-2011
3 * Graeme Russ, <graeme.russ@gmail.com>
6 * Daniel Engström, Omicron Ceti AB, <daniel@omicron.se>
9 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
10 * Marius Groeger <mgroeger@sysgo.de>
13 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
14 * Alex Zuepke <azu@sysgo.de>
16 * Part of this file is adapted from coreboot
17 * src/arch/x86/lib/cpu.c
19 * SPDX-License-Identifier: GPL-2.0+
28 #include <asm/control_regs.h>
31 #include <asm/processor.h>
32 #include <asm/processor-flags.h>
33 #include <asm/interrupt.h>
34 #include <asm/tables.h>
35 #include <linux/compiler.h>
37 DECLARE_GLOBAL_DATA_PTR;
40 * Constructor for a conventional segment GDT (or LDT) entry
41 * This is a macro so it can be used in initialisers
43 #define GDT_ENTRY(flags, base, limit) \
44 ((((base) & 0xff000000ULL) << (56-24)) | \
45 (((flags) & 0x0000f0ffULL) << 40) | \
46 (((limit) & 0x000f0000ULL) << (48-16)) | \
47 (((base) & 0x00ffffffULL) << 16) | \
48 (((limit) & 0x0000ffffULL)))
55 struct cpu_device_id {
61 uint8_t x86; /* CPU family */
62 uint8_t x86_vendor; /* CPU vendor */
68 * List of cpu vendor strings along with their normalized
75 { X86_VENDOR_INTEL, "GenuineIntel", },
76 { X86_VENDOR_CYRIX, "CyrixInstead", },
77 { X86_VENDOR_AMD, "AuthenticAMD", },
78 { X86_VENDOR_UMC, "UMC UMC UMC ", },
79 { X86_VENDOR_NEXGEN, "NexGenDriven", },
80 { X86_VENDOR_CENTAUR, "CentaurHauls", },
81 { X86_VENDOR_RISE, "RiseRiseRise", },
82 { X86_VENDOR_TRANSMETA, "GenuineTMx86", },
83 { X86_VENDOR_TRANSMETA, "TransmetaCPU", },
84 { X86_VENDOR_NSC, "Geode by NSC", },
85 { X86_VENDOR_SIS, "SiS SiS SiS ", },
88 static const char *const x86_vendor_name[] = {
89 [X86_VENDOR_INTEL] = "Intel",
90 [X86_VENDOR_CYRIX] = "Cyrix",
91 [X86_VENDOR_AMD] = "AMD",
92 [X86_VENDOR_UMC] = "UMC",
93 [X86_VENDOR_NEXGEN] = "NexGen",
94 [X86_VENDOR_CENTAUR] = "Centaur",
95 [X86_VENDOR_RISE] = "Rise",
96 [X86_VENDOR_TRANSMETA] = "Transmeta",
97 [X86_VENDOR_NSC] = "NSC",
98 [X86_VENDOR_SIS] = "SiS",
101 static void load_ds(u32 segment)
103 asm volatile("movl %0, %%ds" : : "r" (segment * X86_GDT_ENTRY_SIZE));
106 static void load_es(u32 segment)
108 asm volatile("movl %0, %%es" : : "r" (segment * X86_GDT_ENTRY_SIZE));
111 static void load_fs(u32 segment)
113 asm volatile("movl %0, %%fs" : : "r" (segment * X86_GDT_ENTRY_SIZE));
116 static void load_gs(u32 segment)
118 asm volatile("movl %0, %%gs" : : "r" (segment * X86_GDT_ENTRY_SIZE));
121 static void load_ss(u32 segment)
123 asm volatile("movl %0, %%ss" : : "r" (segment * X86_GDT_ENTRY_SIZE));
126 static void load_gdt(const u64 *boot_gdt, u16 num_entries)
130 gdt.len = (num_entries * X86_GDT_ENTRY_SIZE) - 1;
131 gdt.ptr = (u32)boot_gdt;
133 asm volatile("lgdtl %0\n" : : "m" (gdt));
136 void setup_gdt(gd_t *id, u64 *gdt_addr)
138 id->arch.gdt = gdt_addr;
139 /* CS: code, read/execute, 4 GB, base 0 */
140 gdt_addr[X86_GDT_ENTRY_32BIT_CS] = GDT_ENTRY(0xc09b, 0, 0xfffff);
142 /* DS: data, read/write, 4 GB, base 0 */
143 gdt_addr[X86_GDT_ENTRY_32BIT_DS] = GDT_ENTRY(0xc093, 0, 0xfffff);
145 /* FS: data, read/write, 4 GB, base (Global Data Pointer) */
146 id->arch.gd_addr = id;
147 gdt_addr[X86_GDT_ENTRY_32BIT_FS] = GDT_ENTRY(0xc093,
148 (ulong)&id->arch.gd_addr, 0xfffff);
150 /* 16-bit CS: code, read/execute, 64 kB, base 0 */
151 gdt_addr[X86_GDT_ENTRY_16BIT_CS] = GDT_ENTRY(0x009b, 0, 0x0ffff);
153 /* 16-bit DS: data, read/write, 64 kB, base 0 */
154 gdt_addr[X86_GDT_ENTRY_16BIT_DS] = GDT_ENTRY(0x0093, 0, 0x0ffff);
156 gdt_addr[X86_GDT_ENTRY_16BIT_FLAT_CS] = GDT_ENTRY(0x809b, 0, 0xfffff);
157 gdt_addr[X86_GDT_ENTRY_16BIT_FLAT_DS] = GDT_ENTRY(0x8093, 0, 0xfffff);
159 load_gdt(gdt_addr, X86_GDT_NUM_ENTRIES);
160 load_ds(X86_GDT_ENTRY_32BIT_DS);
161 load_es(X86_GDT_ENTRY_32BIT_DS);
162 load_gs(X86_GDT_ENTRY_32BIT_DS);
163 load_ss(X86_GDT_ENTRY_32BIT_DS);
164 load_fs(X86_GDT_ENTRY_32BIT_FS);
167 #ifdef CONFIG_HAVE_FSP
169 * Setup FSP execution environment GDT
171 * Per Intel FSP external architecture specification, before calling any FSP
172 * APIs, we need make sure the system is in flat 32-bit mode and both the code
173 * and data selectors should have full 4GB access range. Here we reuse the one
174 * we used in arch/x86/cpu/start16.S, and reload the segement registers.
176 void setup_fsp_gdt(void)
178 load_gdt((const u64 *)(gdt_rom + CONFIG_RESET_SEG_START), 4);
179 load_ds(X86_GDT_ENTRY_32BIT_DS);
180 load_ss(X86_GDT_ENTRY_32BIT_DS);
181 load_es(X86_GDT_ENTRY_32BIT_DS);
182 load_fs(X86_GDT_ENTRY_32BIT_DS);
183 load_gs(X86_GDT_ENTRY_32BIT_DS);
187 int __weak x86_cleanup_before_linux(void)
189 #ifdef CONFIG_BOOTSTAGE_STASH
190 bootstage_stash((void *)CONFIG_BOOTSTAGE_STASH_ADDR,
191 CONFIG_BOOTSTAGE_STASH_SIZE);
198 * Cyrix CPUs without cpuid or with cpuid not yet enabled can be detected
199 * by the fact that they preserve the flags across the division of 5/2.
200 * PII and PPro exhibit this behavior too, but they have cpuid available.
204 * Perform the Cyrix 5/2 test. A Cyrix won't change
205 * the flags, while other 486 chips will.
207 static inline int test_cyrix_52div(void)
211 __asm__ __volatile__(
212 "sahf\n\t" /* clear flags (%eax = 0x0005) */
213 "div %b2\n\t" /* divide 5 by 2 */
214 "lahf" /* store flags into %ah */
219 /* AH is 0x02 on Cyrix after the divide.. */
220 return (unsigned char) (test >> 8) == 0x02;
224 * Detect a NexGen CPU running without BIOS hypercode new enough
225 * to have CPUID. (Thanks to Herbert Oppmann)
228 static int deep_magic_nexgen_probe(void)
232 __asm__ __volatile__ (
233 " movw $0x5555, %%ax\n"
241 : "=a" (ret) : : "cx", "dx");
245 static bool has_cpuid(void)
247 return flag_is_changeable_p(X86_EFLAGS_ID);
250 static bool has_mtrr(void)
252 return cpuid_edx(0x00000001) & (1 << 12) ? true : false;
255 static int build_vendor_name(char *vendor_name)
257 struct cpuid_result result;
258 result = cpuid(0x00000000);
259 unsigned int *name_as_ints = (unsigned int *)vendor_name;
261 name_as_ints[0] = result.ebx;
262 name_as_ints[1] = result.edx;
263 name_as_ints[2] = result.ecx;
268 static void identify_cpu(struct cpu_device_id *cpu)
270 char vendor_name[16];
273 vendor_name[0] = '\0'; /* Unset */
274 cpu->device = 0; /* fix gcc 4.4.4 warning */
276 /* Find the id and vendor_name */
278 /* Its a 486 if we can modify the AC flag */
279 if (flag_is_changeable_p(X86_EFLAGS_AC))
280 cpu->device = 0x00000400; /* 486 */
282 cpu->device = 0x00000300; /* 386 */
283 if ((cpu->device == 0x00000400) && test_cyrix_52div()) {
284 memcpy(vendor_name, "CyrixInstead", 13);
285 /* If we ever care we can enable cpuid here */
287 /* Detect NexGen with old hypercode */
288 else if (deep_magic_nexgen_probe())
289 memcpy(vendor_name, "NexGenDriven", 13);
294 cpuid_level = build_vendor_name(vendor_name);
295 vendor_name[12] = '\0';
297 /* Intel-defined flags: level 0x00000001 */
298 if (cpuid_level >= 0x00000001) {
299 cpu->device = cpuid_eax(0x00000001);
301 /* Have CPUID level 0 only unheard of */
302 cpu->device = 0x00000400;
305 cpu->vendor = X86_VENDOR_UNKNOWN;
306 for (i = 0; i < ARRAY_SIZE(x86_vendors); i++) {
307 if (memcmp(vendor_name, x86_vendors[i].name, 12) == 0) {
308 cpu->vendor = x86_vendors[i].vendor;
314 static inline void get_fms(struct cpuinfo_x86 *c, uint32_t tfms)
316 c->x86 = (tfms >> 8) & 0xf;
317 c->x86_model = (tfms >> 4) & 0xf;
318 c->x86_mask = tfms & 0xf;
320 c->x86 += (tfms >> 20) & 0xff;
322 c->x86_model += ((tfms >> 16) & 0xF) << 4;
325 int x86_cpu_init_f(void)
327 const u32 em_rst = ~X86_CR0_EM;
328 const u32 mp_ne_set = X86_CR0_MP | X86_CR0_NE;
330 /* initialize FPU, reset EM, set MP and NE */
332 "movl %%cr0, %%eax\n" \
335 "movl %%eax, %%cr0\n" \
336 : : "i" (em_rst), "i" (mp_ne_set) : "eax");
338 /* identify CPU via cpuid and store the decoded info into gd->arch */
340 struct cpu_device_id cpu;
341 struct cpuinfo_x86 c;
344 get_fms(&c, cpu.device);
345 gd->arch.x86 = c.x86;
346 gd->arch.x86_vendor = cpu.vendor;
347 gd->arch.x86_model = c.x86_model;
348 gd->arch.x86_mask = c.x86_mask;
349 gd->arch.x86_device = cpu.device;
351 gd->arch.has_mtrr = has_mtrr();
357 void x86_enable_caches(void)
362 cr0 &= ~(X86_CR0_NW | X86_CR0_CD);
366 void enable_caches(void) __attribute__((weak, alias("x86_enable_caches")));
368 void x86_disable_caches(void)
373 cr0 |= X86_CR0_NW | X86_CR0_CD;
378 void disable_caches(void) __attribute__((weak, alias("x86_disable_caches")));
380 int x86_init_cache(void)
386 int init_cache(void) __attribute__((weak, alias("x86_init_cache")));
388 int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
390 printf("resetting ...\n");
394 disable_interrupts();
401 void flush_cache(unsigned long dummy1, unsigned long dummy2)
406 __weak void reset_cpu(ulong addr)
408 /* Do a hard reset through the chipset's reset control register */
409 outb(SYS_RST | RST_CPU, PORT_RESET);
414 void x86_full_reset(void)
416 outb(FULL_RST | SYS_RST | RST_CPU, PORT_RESET);
419 int dcache_status(void)
421 return !(read_cr0() & 0x40000000);
424 /* Define these functions to allow ehch-hcd to function */
425 void flush_dcache_range(unsigned long start, unsigned long stop)
429 void invalidate_dcache_range(unsigned long start, unsigned long stop)
433 void dcache_enable(void)
438 void dcache_disable(void)
443 void icache_enable(void)
447 void icache_disable(void)
451 int icache_status(void)
456 void cpu_enable_paging_pae(ulong cr3)
458 __asm__ __volatile__(
459 /* Load the page table address */
462 "movl %%cr4, %%eax\n"
463 "orl $0x00000020, %%eax\n"
464 "movl %%eax, %%cr4\n"
466 "movl %%cr0, %%eax\n"
467 "orl $0x80000000, %%eax\n"
468 "movl %%eax, %%cr0\n"
474 void cpu_disable_paging_pae(void)
476 /* Turn off paging */
477 __asm__ __volatile__ (
479 "movl %%cr0, %%eax\n"
480 "andl $0x7fffffff, %%eax\n"
481 "movl %%eax, %%cr0\n"
483 "movl %%cr4, %%eax\n"
484 "andl $0xffffffdf, %%eax\n"
485 "movl %%eax, %%cr4\n"
491 static bool can_detect_long_mode(void)
493 return cpuid_eax(0x80000000) > 0x80000000UL;
496 static bool has_long_mode(void)
498 return cpuid_edx(0x80000001) & (1 << 29) ? true : false;
501 int cpu_has_64bit(void)
503 return has_cpuid() && can_detect_long_mode() &&
507 const char *cpu_vendor_name(int vendor)
510 name = "<invalid cpu vendor>";
511 if ((vendor < (ARRAY_SIZE(x86_vendor_name))) &&
512 (x86_vendor_name[vendor] != 0))
513 name = x86_vendor_name[vendor];
518 char *cpu_get_name(char *name)
520 unsigned int *name_as_ints = (unsigned int *)name;
521 struct cpuid_result regs;
525 /* This bit adds up to 48 bytes */
526 for (i = 0; i < 3; i++) {
527 regs = cpuid(0x80000002 + i);
528 name_as_ints[i * 4 + 0] = regs.eax;
529 name_as_ints[i * 4 + 1] = regs.ebx;
530 name_as_ints[i * 4 + 2] = regs.ecx;
531 name_as_ints[i * 4 + 3] = regs.edx;
533 name[CPU_MAX_NAME_LEN - 1] = '\0';
535 /* Skip leading spaces. */
543 int x86_cpu_get_desc(struct udevice *dev, char *buf, int size)
545 if (size < CPU_MAX_NAME_LEN)
553 int default_print_cpuinfo(void)
555 printf("CPU: %s, vendor %s, device %xh\n",
556 cpu_has_64bit() ? "x86_64" : "x86",
557 cpu_vendor_name(gd->arch.x86_vendor), gd->arch.x86_device);
562 #define PAGETABLE_SIZE (6 * 4096)
565 * build_pagetable() - build a flat 4GiB page table structure for 64-bti mode
567 * @pgtable: Pointer to a 24iKB block of memory
569 static void build_pagetable(uint32_t *pgtable)
573 memset(pgtable, '\0', PAGETABLE_SIZE);
575 /* Level 4 needs a single entry */
576 pgtable[0] = (uint32_t)&pgtable[1024] + 7;
578 /* Level 3 has one 64-bit entry for each GiB of memory */
579 for (i = 0; i < 4; i++) {
580 pgtable[1024 + i * 2] = (uint32_t)&pgtable[2048] +
584 /* Level 2 has 2048 64-bit entries, each repesenting 2MiB */
585 for (i = 0; i < 2048; i++)
586 pgtable[2048 + i * 2] = 0x183 + (i << 21UL);
589 int cpu_jump_to_64bit(ulong setup_base, ulong target)
593 pgtable = memalign(4096, PAGETABLE_SIZE);
597 build_pagetable(pgtable);
598 cpu_call64((ulong)pgtable, setup_base, target);
604 void show_boot_progress(int val)
606 #if MIN_PORT80_KCLOCKS_DELAY
608 * Scale the time counter reading to avoid using 64 bit arithmetics.
609 * Can't use get_timer() here becuase it could be not yet
610 * initialized or even implemented.
612 if (!gd->arch.tsc_prev) {
613 gd->arch.tsc_base_kclocks = rdtsc() / 1000;
614 gd->arch.tsc_prev = 0;
619 now = rdtsc() / 1000 - gd->arch.tsc_base_kclocks;
620 } while (now < (gd->arch.tsc_prev + MIN_PORT80_KCLOCKS_DELAY));
621 gd->arch.tsc_prev = now;
624 outb(val, POST_PORT);
627 #ifndef CONFIG_SYS_COREBOOT
628 int last_stage_init(void)
636 __weak int x86_init_cpus(void)
643 return x86_init_cpus();
646 static const struct cpu_ops cpu_x86_ops = {
647 .get_desc = x86_cpu_get_desc,
650 static const struct udevice_id cpu_x86_ids[] = {
651 { .compatible = "cpu-x86" },
655 U_BOOT_DRIVER(cpu_x86_drv) = {
658 .of_match = cpu_x86_ids,