2 * From Coreboot file of same name
4 * Copyright (C) 2007-2009 coresystems GmbH
5 * Copyright (C) 2011 The Chromium Authors
7 * SPDX-License-Identifier: GPL-2.0
17 #include <asm/cpu_x86.h>
18 #include <asm/lapic.h>
21 #include <asm/processor.h>
22 #include <asm/speedstep.h>
23 #include <asm/turbo.h>
24 #include <asm/arch/bd82x6x.h>
25 #include <asm/arch/model_206ax.h>
27 static void enable_vmx(void)
29 struct cpuid_result regs;
30 #ifdef CONFIG_ENABLE_VMX
38 /* Check that the VMX is supported before reading or writing the MSR. */
39 if (!((regs.ecx & CPUID_VMX) || (regs.ecx & CPUID_SMX)))
42 msr = msr_read(MSR_IA32_FEATURE_CONTROL);
44 if (msr.lo & (1 << 0)) {
45 debug("VMX is locked, so %s will do nothing\n", __func__);
46 /* VMX locked. If we set it again we get an illegal
52 /* The IA32_FEATURE_CONTROL MSR may initialize with random values.
53 * It must be cleared regardless of VMX config setting.
58 debug("%s VMX\n", enable ? "Enabling" : "Disabling");
61 * Even though the Intel manual says you must set the lock bit in
62 * addition to the VMX bit in order for VMX to work, it is incorrect.
63 * Thus we leave it unlocked for the OS to manage things itself.
64 * This is good for a few reasons:
65 * - No need to reflash the bios just to toggle the lock bit.
66 * - The VMX bits really really should match each other across cores,
67 * so hard locking it on one while another has the opposite setting
68 * can easily lead to crashes as code using VMX migrates between
70 * - Vendors that want to "upsell" from a bios that disables+locks to
71 * one that doesn't is sleazy.
72 * By leaving this to the OS (e.g. Linux), people can do exactly what
73 * they want on the fly, and do it correctly (e.g. across multiple
78 if (regs.ecx & CPUID_SMX)
82 msr_write(MSR_IA32_FEATURE_CONTROL, msr);
85 /* Convert time in seconds to POWER_LIMIT_1_TIME MSR value */
86 static const u8 power_limit_time_sec_to_msr[] = {
114 /* Convert POWER_LIMIT_1_TIME MSR value to seconds */
115 static const u8 power_limit_time_msr_to_sec[] = {
143 int cpu_config_tdp_levels(void)
145 struct cpuid_result result;
148 /* Minimum CPU revision */
150 if (result.eax < IVB_CONFIG_TDP_MIN_CPUID)
153 /* Bits 34:33 indicate how many levels supported */
154 platform_info = msr_read(MSR_PLATFORM_INFO);
155 return (platform_info.hi >> 1) & 3;
159 * Configure processor power limits if possible
160 * This must be done AFTER set of BIOS_RESET_CPL
162 void set_power_limits(u8 power_limit_1_time)
164 msr_t msr = msr_read(MSR_PLATFORM_INFO);
167 unsigned tdp, min_power, max_power, max_time;
168 u8 power_limit_1_val;
170 if (power_limit_1_time > ARRAY_SIZE(power_limit_time_sec_to_msr))
173 if (!(msr.lo & PLATFORM_INFO_SET_TDP))
177 msr = msr_read(MSR_PKG_POWER_SKU_UNIT);
178 power_unit = 2 << ((msr.lo & 0xf) - 1);
180 /* Get power defaults for this SKU */
181 msr = msr_read(MSR_PKG_POWER_SKU);
182 tdp = msr.lo & 0x7fff;
183 min_power = (msr.lo >> 16) & 0x7fff;
184 max_power = msr.hi & 0x7fff;
185 max_time = (msr.hi >> 16) & 0x7f;
187 debug("CPU TDP: %u Watts\n", tdp / power_unit);
189 if (power_limit_time_msr_to_sec[max_time] > power_limit_1_time)
190 power_limit_1_time = power_limit_time_msr_to_sec[max_time];
192 if (min_power > 0 && tdp < min_power)
195 if (max_power > 0 && tdp > max_power)
198 power_limit_1_val = power_limit_time_sec_to_msr[power_limit_1_time];
200 /* Set long term power limit to TDP */
202 limit.lo |= tdp & PKG_POWER_LIMIT_MASK;
203 limit.lo |= PKG_POWER_LIMIT_EN;
204 limit.lo |= (power_limit_1_val & PKG_POWER_LIMIT_TIME_MASK) <<
205 PKG_POWER_LIMIT_TIME_SHIFT;
207 /* Set short term power limit to 1.25 * TDP */
209 limit.hi |= ((tdp * 125) / 100) & PKG_POWER_LIMIT_MASK;
210 limit.hi |= PKG_POWER_LIMIT_EN;
211 /* Power limit 2 time is only programmable on SNB EP/EX */
213 msr_write(MSR_PKG_POWER_LIMIT, limit);
215 /* Use nominal TDP values for CPUs with configurable TDP */
216 if (cpu_config_tdp_levels()) {
217 msr = msr_read(MSR_CONFIG_TDP_NOMINAL);
219 limit.lo = msr.lo & 0xff;
220 msr_write(MSR_TURBO_ACTIVATION_RATIO, limit);
224 static void configure_c_states(void)
226 struct cpuid_result result;
229 msr = msr_read(MSR_PMG_CST_CONFIG_CTL);
230 msr.lo |= (1 << 28); /* C1 Auto Undemotion Enable */
231 msr.lo |= (1 << 27); /* C3 Auto Undemotion Enable */
232 msr.lo |= (1 << 26); /* C1 Auto Demotion Enable */
233 msr.lo |= (1 << 25); /* C3 Auto Demotion Enable */
234 msr.lo &= ~(1 << 10); /* Disable IO MWAIT redirection */
235 msr.lo |= 7; /* No package C-state limit */
236 msr_write(MSR_PMG_CST_CONFIG_CTL, msr);
238 msr = msr_read(MSR_PMG_IO_CAPTURE_ADR);
240 msr.lo |= (PMB0_BASE + 4); /* LVL_2 base address */
241 msr.lo |= (2 << 16); /* CST Range: C7 is max C-state */
242 msr_write(MSR_PMG_IO_CAPTURE_ADR, msr);
244 msr = msr_read(MSR_MISC_PWR_MGMT);
245 msr.lo &= ~(1 << 0); /* Enable P-state HW_ALL coordination */
246 msr_write(MSR_MISC_PWR_MGMT, msr);
248 msr = msr_read(MSR_POWER_CTL);
249 msr.lo |= (1 << 18); /* Enable Energy Perf Bias MSR 0x1b0 */
250 msr.lo |= (1 << 1); /* C1E Enable */
251 msr.lo |= (1 << 0); /* Bi-directional PROCHOT# */
252 msr_write(MSR_POWER_CTL, msr);
254 /* C3 Interrupt Response Time Limit */
256 msr.lo = IRTL_VALID | IRTL_1024_NS | 0x50;
257 msr_write(MSR_PKGC3_IRTL, msr);
259 /* C6 Interrupt Response Time Limit */
261 msr.lo = IRTL_VALID | IRTL_1024_NS | 0x68;
262 msr_write(MSR_PKGC6_IRTL, msr);
264 /* C7 Interrupt Response Time Limit */
266 msr.lo = IRTL_VALID | IRTL_1024_NS | 0x6D;
267 msr_write(MSR_PKGC7_IRTL, msr);
269 /* Primary Plane Current Limit */
270 msr = msr_read(MSR_PP0_CURRENT_CONFIG);
272 msr.lo |= PP0_CURRENT_LIMIT;
273 msr_write(MSR_PP0_CURRENT_CONFIG, msr);
275 /* Secondary Plane Current Limit */
276 msr = msr_read(MSR_PP1_CURRENT_CONFIG);
279 if (result.eax >= 0x30600)
280 msr.lo |= PP1_CURRENT_LIMIT_IVB;
282 msr.lo |= PP1_CURRENT_LIMIT_SNB;
283 msr_write(MSR_PP1_CURRENT_CONFIG, msr);
286 static int configure_thermal_target(void)
292 /* Find pointer to CPU configuration */
293 node = fdtdec_next_compatible(gd->fdt_blob, 0,
294 COMPAT_INTEL_MODEL_206AX);
297 tcc_offset = fdtdec_get_int(gd->fdt_blob, node, "tcc-offset", 0);
299 /* Set TCC activaiton offset if supported */
300 msr = msr_read(MSR_PLATFORM_INFO);
301 if ((msr.lo & (1 << 30)) && tcc_offset) {
302 msr = msr_read(MSR_TEMPERATURE_TARGET);
303 msr.lo &= ~(0xf << 24); /* Bits 27:24 */
304 msr.lo |= (tcc_offset & 0xf) << 24;
305 msr_write(MSR_TEMPERATURE_TARGET, msr);
311 static void configure_misc(void)
315 msr = msr_read(IA32_MISC_ENABLE);
316 msr.lo |= (1 << 0); /* Fast String enable */
317 msr.lo |= (1 << 3); /* TM1/TM2/EMTTM enable */
318 msr.lo |= (1 << 16); /* Enhanced SpeedStep Enable */
319 msr_write(IA32_MISC_ENABLE, msr);
321 /* Disable Thermal interrupts */
324 msr_write(IA32_THERM_INTERRUPT, msr);
326 /* Enable package critical interrupt only */
329 msr_write(IA32_PACKAGE_THERM_INTERRUPT, msr);
332 static void enable_lapic_tpr(void)
336 msr = msr_read(MSR_PIC_MSG_CONTROL);
337 msr.lo &= ~(1 << 10); /* Enable APIC TPR updates */
338 msr_write(MSR_PIC_MSG_CONTROL, msr);
341 static void configure_dca_cap(void)
343 struct cpuid_result cpuid_regs;
346 /* Check feature flag in CPUID.(EAX=1):ECX[18]==1 */
347 cpuid_regs = cpuid(1);
348 if (cpuid_regs.ecx & (1 << 18)) {
349 msr = msr_read(IA32_PLATFORM_DCA_CAP);
351 msr_write(IA32_PLATFORM_DCA_CAP, msr);
355 static void set_max_ratio(void)
361 /* Check for configurable TDP option */
362 if (cpu_config_tdp_levels()) {
363 /* Set to nominal TDP ratio */
364 msr = msr_read(MSR_CONFIG_TDP_NOMINAL);
365 perf_ctl.lo = (msr.lo & 0xff) << 8;
367 /* Platform Info bits 15:8 give max ratio */
368 msr = msr_read(MSR_PLATFORM_INFO);
369 perf_ctl.lo = msr.lo & 0xff00;
371 msr_write(IA32_PERF_CTL, perf_ctl);
373 debug("model_x06ax: frequency set to %d\n",
374 ((perf_ctl.lo >> 8) & 0xff) * SANDYBRIDGE_BCLK);
377 static void set_energy_perf_bias(u8 policy)
381 /* Energy Policy is bits 3:0 */
382 msr = msr_read(IA32_ENERGY_PERFORMANCE_BIAS);
384 msr.lo |= policy & 0xf;
385 msr_write(IA32_ENERGY_PERFORMANCE_BIAS, msr);
387 debug("model_x06ax: energy policy set to %u\n", policy);
390 static void configure_mca(void)
397 /* This should only be done on a cold boot */
398 for (i = 0; i < 7; i++)
399 msr_write(IA32_MC0_STATUS + (i * 4), msr);
403 static unsigned ehci_debug_addr;
406 int model_206ax_init(struct x86_cpu_priv *cpu)
410 /* Clear out pending MCEs */
414 /* Is this caution really needed? */
415 if (!ehci_debug_addr)
416 ehci_debug_addr = get_ehci_debug();
420 /* Setup MTRRs based on physical address size */
421 #if 0 /* TODO: Implement this */
422 struct cpuid_result cpuid_regs;
424 cpuid_regs = cpuid(0x80000008);
425 x86_setup_fixed_mtrrs();
426 x86_setup_var_mtrrs(cpuid_regs.eax & 0xff, 2);
431 set_ehci_debug(ehci_debug_addr);
434 /* Enable the local cpu apics */
438 /* Enable virtualization if enabled in CMOS */
441 /* Configure C States */
442 configure_c_states();
444 /* Configure Enhanced SpeedStep and Thermal Sensors */
447 /* Thermal throttle activation offset */
448 ret = configure_thermal_target();
450 debug("Cannot set thermal target\n");
454 /* Enable Direct Cache Access */
457 /* Set energy policy */
458 set_energy_perf_bias(ENERGY_POLICY_NORMAL);
469 static int model_206ax_get_info(struct udevice *dev, struct cpu_info *info)
471 info->features = 1 << CPU_FEAT_L1_CACHE | 1 << CPU_FEAT_MMU;
476 static int model_206ax_get_count(struct udevice *dev)
481 static int cpu_x86_model_206ax_probe(struct udevice *dev)
486 static const struct cpu_ops cpu_x86_model_206ax_ops = {
487 .get_desc = cpu_x86_get_desc,
488 .get_info = model_206ax_get_info,
489 .get_count = model_206ax_get_count,
492 static const struct udevice_id cpu_x86_model_206ax_ids[] = {
493 { .compatible = "intel,core-gen3" },
497 U_BOOT_DRIVER(cpu_x86_model_206ax_drv) = {
498 .name = "cpu_x86_model_206ax",
500 .of_match = cpu_x86_model_206ax_ids,
501 .bind = cpu_x86_bind,
502 .probe = cpu_x86_model_206ax_probe,
503 .ops = &cpu_x86_model_206ax_ops,