2 * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
4 * SPDX-License-Identifier: GPL-2.0+
9 /include/ "skeleton.dtsi"
10 /include/ "serial.dtsi"
13 model = "Intel Crown Bay";
14 compatible = "intel,crownbay", "intel,queensbay";
21 compatible = "intel,ich6-gpio";
28 compatible = "intel,ich6-gpio";
36 * By default the legacy superio serial port is used as the
37 * U-Boot serial console. If we want to use UART from Topcliff
38 * PCH as the console, change this property to &pciuart#.
40 * For example, stdout-path = &pciuart0 will use the first
41 * UART on Topcliff PCH.
43 stdout-path = "/serial";
49 compatible = "intel,ich7";
52 compatible = "sst,25vf016b", "spi-flash";
53 memory-map = <0xffe00000 0x00200000>;
59 #include "microcode/m0220661105_cv.dtsi"
66 compatible = "intel,pci";
72 compatible = "intel,pci";
78 compatible = "intel,pci";
82 compatible = "pci8086,8811.00",
87 reg = <0x00025100 0x0 0x0 0x0 0x0
88 0x01025110 0x0 0x0 0x0 0x0>;
90 clock-frequency = <1843200>;
91 current-speed = <115200>;
95 compatible = "pci8086,8812.00",
100 reg = <0x00025200 0x0 0x0 0x0 0x0
101 0x01025210 0x0 0x0 0x0 0x0>;
103 clock-frequency = <1843200>;
104 current-speed = <115200>;
108 compatible = "pci8086,8813.00",
113 reg = <0x00025300 0x0 0x0 0x0 0x0
114 0x01025310 0x0 0x0 0x0 0x0>;
116 clock-frequency = <1843200>;
117 current-speed = <115200>;
121 compatible = "pci8086,8814.00",
126 reg = <0x00025400 0x0 0x0 0x0 0x0
127 0x01025410 0x0 0x0 0x0 0x0>;
129 clock-frequency = <1843200>;
130 current-speed = <115200>;