2 * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
4 * SPDX-License-Identifier: GPL-2.0+
9 /include/ "skeleton.dtsi"
10 /include/ "serial.dtsi"
13 model = "Intel Crown Bay";
14 compatible = "intel,crownbay", "intel,queensbay";
25 compatible = "intel,ich6-gpio";
32 compatible = "intel,ich6-gpio";
40 * By default the legacy superio serial port is used as the
41 * U-Boot serial console. If we want to use UART from Topcliff
42 * PCH as the console, change this property to &pciuart#.
44 * For example, stdout-path = &pciuart0 will use the first
45 * UART on Topcliff PCH.
47 stdout-path = "/serial";
53 compatible = "intel,ich-spi";
56 compatible = "sst,25vf016b", "spi-flash";
57 memory-map = <0xffe00000 0x00200000>;
63 #include "microcode/m0220661105_cv.dtsi"
70 compatible = "intel,pci";
76 compatible = "intel,pci";
82 compatible = "intel,pci";
86 compatible = "pci8086,8811.00",
91 reg = <0x00025100 0x0 0x0 0x0 0x0
92 0x01025110 0x0 0x0 0x0 0x0>;
94 clock-frequency = <1843200>;
95 current-speed = <115200>;
99 compatible = "pci8086,8812.00",
104 reg = <0x00025200 0x0 0x0 0x0 0x0
105 0x01025210 0x0 0x0 0x0 0x0>;
107 clock-frequency = <1843200>;
108 current-speed = <115200>;
112 compatible = "pci8086,8813.00",
117 reg = <0x00025300 0x0 0x0 0x0 0x0
118 0x01025310 0x0 0x0 0x0 0x0>;
120 clock-frequency = <1843200>;
121 current-speed = <115200>;
125 compatible = "pci8086,8814.00",
130 reg = <0x00025400 0x0 0x0 0x0 0x0
131 0x01025410 0x0 0x0 0x0 0x0>;
133 clock-frequency = <1843200>;
134 current-speed = <115200>;