git.sur5r.net Git - u-boot/blob - arch/x86/dts/galileo.dts

   1 /*
   2  * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 /dts-v1/;
   8
   9 #include <dt-bindings/mrc/quark.h>
  10
  11 /include/ "skeleton.dtsi"
  12
  13 / {
  14         model = "Intel Galileo";
  15         compatible = "intel,galileo", "intel,quark";
  16
  17         config {
  18                 silent_console = <0>;
  19         };
  20
  21         chosen {
  22                 stdout-path = &pciuart0;
  23         };
  24
  25         mrc {
  26                 compatible = "intel,quark-mrc";
  27                 flags = <MRC_FLAG_SCRAMBLE_EN>;
  28                 dram-width = <DRAM_WIDTH_X8>;
  29                 dram-speed = <DRAM_FREQ_800>;
  30                 dram-type = <DRAM_TYPE_DDR3>;
  31                 rank-mask = <DRAM_RANK(0)>;
  32                 chan-mask = <DRAM_CHANNEL(0)>;
  33                 chan-width = <DRAM_CHANNEL_WIDTH_X16>;
  34                 addr-mode = <DRAM_ADDR_MODE0>;
  35                 refresh-rate = <DRAM_REFRESH_RATE_785US>;
  36                 sr-temp-range = <DRAM_SRT_RANGE_NORMAL>;
  37                 ron-value = <DRAM_RON_34OHM>;
  38                 rtt-nom-value = <DRAM_RTT_NOM_120OHM>;
  39                 rd-odt-value = <DRAM_RD_ODT_OFF>;
  40                 dram-density = <DRAM_DENSITY_1G>;
  41                 dram-cl = <6>;
  42                 dram-ras = <0x0000927c>;
  43                 dram-wtr = <0x00002710>;
  44                 dram-rrd = <0x00002710>;
  45                 dram-faw = <0x00009c40>;
  46         };
  47
  48         pci {
  49                 #address-cells = <3>;
  50                 #size-cells = <2>;
  51                 compatible = "intel,pci";
  52                 device_type = "pci";
  53
  54                 pciuart0: uart@14,5 {
  55                         compatible = "pci8086,0936.00",
  56                                         "pci8086,0936",
  57                                         "pciclass,070002",
  58                                         "pciclass,0700",
  59                                         "x86-uart";
  60                         reg = <0x0000a500 0x0 0x0 0x0 0x0
  61                                0x0200a510 0x0 0x0 0x0 0x0>;
  62                         reg-shift = <2>;
  63                         clock-frequency = <44236800>;
  64                         current-speed = <115200>;
  65                 };
  66         };
  67
  68         gpioa {
  69                 compatible = "intel,ich6-gpio";
  70                 u-boot,dm-pre-reloc;
  71                 reg = <0 0x20>;
  72                 bank-name = "A";
  73         };
  74
  75         gpiob {
  76                 compatible = "intel,ich6-gpio";
  77                 u-boot,dm-pre-reloc;
  78                 reg = <0x20 0x20>;
  79                 bank-name = "B";
  80         };
  81
  82         spi {
  83                 #address-cells = <1>;
  84                 #size-cells = <0>;
  85                 compatible = "intel,ich-spi";
  86                 spi-flash@0 {
  87                         #size-cells = <1>;
  88                         #address-cells = <1>;
  89                         reg = <0>;
  90                         compatible = "winbond,w25q64", "spi-flash";
  91                         memory-map = <0xff800000 0x00800000>;
  92                 };
  93         };
  94
  95 };