2 * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
4 * SPDX-License-Identifier: GPL-2.0+
9 #include <asm/arch-baytrail/fsp/fsp_configs.h>
10 #include <dt-bindings/gpio/x86-gpio.h>
11 #include <dt-bindings/interrupt-router/intel-irq.h>
13 /include/ "skeleton.dtsi"
14 /include/ "serial.dtsi"
16 /include/ "tsc_timer.dtsi"
17 /include/ "coreboot_fb.dtsi"
20 model = "Intel Minnowboard Max";
21 compatible = "intel,minnowmax", "intel,baytrail";
33 compatible = "intel,x86-pinctrl";
38 gpio-offset = <0x80 0>;
41 direction = <PIN_OUTPUT>;
46 gpio-offset = <0x80 1>;
49 direction = <PIN_OUTPUT>;
54 gpio-offset = <0x80 2>;
57 direction = <PIN_OUTPUT>;
61 gpio-offset = <0x80 8>;
64 direction = <PIN_OUTPUT>;
68 gpio-offset = <0x80 9>;
71 direction = <PIN_OUTPUT>;
75 * As of today, the latest version FSP (gold4) for BayTrail
76 * misses the PAD configuration of the SD controller's Card
77 * Detect signal. The default PAD value for the CD pin sets
78 * the pin to work in GPIO mode, which causes card detect
79 * status cannot be reflected by the Present State register
80 * in the SD controller (bit 16 & bit 18 are always zero).
82 * Configure this pin to function 1 (SD controller).
91 stdout-path = "/serial";
100 compatible = "intel,baytrail-cpu";
107 compatible = "intel,baytrail-cpu";
115 compatible = "intel,pci-baytrail", "pci-x86";
116 #address-cells = <3>;
119 ranges = <0x02000000 0x0 0x80000000 0x80000000 0 0x40000000
120 0x42000000 0x0 0xc0000000 0xc0000000 0 0x20000000
121 0x01000000 0x0 0x2000 0x2000 0 0xe000>;
124 reg = <0x0000f800 0 0 0 0>;
125 compatible = "pci8086,0f1c", "intel,pch9";
126 #address-cells = <1>;
130 compatible = "intel,irq-router";
131 intel,pirq-config = "ibase";
132 intel,ibase-offset = <0x50>;
133 intel,actl-addr = <0>;
134 intel,pirq-link = <8 8>;
135 intel,pirq-mask = <0xdee0>;
136 intel,pirq-routing = <
137 /* BayTrail PCI devices */
138 PCI_BDF(0, 2, 0) INTA PIRQA
139 PCI_BDF(0, 3, 0) INTA PIRQA
140 PCI_BDF(0, 16, 0) INTA PIRQA
141 PCI_BDF(0, 17, 0) INTA PIRQA
142 PCI_BDF(0, 18, 0) INTA PIRQA
143 PCI_BDF(0, 19, 0) INTA PIRQA
144 PCI_BDF(0, 20, 0) INTA PIRQA
145 PCI_BDF(0, 21, 0) INTA PIRQA
146 PCI_BDF(0, 22, 0) INTA PIRQA
147 PCI_BDF(0, 23, 0) INTA PIRQA
148 PCI_BDF(0, 24, 0) INTA PIRQA
149 PCI_BDF(0, 24, 1) INTC PIRQC
150 PCI_BDF(0, 24, 2) INTD PIRQD
151 PCI_BDF(0, 24, 3) INTB PIRQB
152 PCI_BDF(0, 24, 4) INTA PIRQA
153 PCI_BDF(0, 24, 5) INTC PIRQC
154 PCI_BDF(0, 24, 6) INTD PIRQD
155 PCI_BDF(0, 24, 7) INTB PIRQB
156 PCI_BDF(0, 26, 0) INTA PIRQA
157 PCI_BDF(0, 27, 0) INTA PIRQA
158 PCI_BDF(0, 28, 0) INTA PIRQA
159 PCI_BDF(0, 28, 1) INTB PIRQB
160 PCI_BDF(0, 28, 2) INTC PIRQC
161 PCI_BDF(0, 28, 3) INTD PIRQD
162 PCI_BDF(0, 29, 0) INTA PIRQA
163 PCI_BDF(0, 30, 0) INTA PIRQA
164 PCI_BDF(0, 30, 1) INTD PIRQD
165 PCI_BDF(0, 30, 2) INTB PIRQB
166 PCI_BDF(0, 30, 3) INTC PIRQC
167 PCI_BDF(0, 30, 4) INTD PIRQD
168 PCI_BDF(0, 30, 5) INTB PIRQB
169 PCI_BDF(0, 31, 3) INTB PIRQB
172 * PCIe root ports downstream
175 PCI_BDF(1, 0, 0) INTA PIRQA
176 PCI_BDF(1, 0, 0) INTB PIRQB
177 PCI_BDF(1, 0, 0) INTC PIRQC
178 PCI_BDF(1, 0, 0) INTD PIRQD
179 PCI_BDF(2, 0, 0) INTA PIRQB
180 PCI_BDF(2, 0, 0) INTB PIRQC
181 PCI_BDF(2, 0, 0) INTC PIRQD
182 PCI_BDF(2, 0, 0) INTD PIRQA
183 PCI_BDF(3, 0, 0) INTA PIRQC
184 PCI_BDF(3, 0, 0) INTB PIRQD
185 PCI_BDF(3, 0, 0) INTC PIRQA
186 PCI_BDF(3, 0, 0) INTD PIRQB
187 PCI_BDF(4, 0, 0) INTA PIRQD
188 PCI_BDF(4, 0, 0) INTB PIRQA
189 PCI_BDF(4, 0, 0) INTC PIRQB
190 PCI_BDF(4, 0, 0) INTD PIRQC
195 #address-cells = <1>;
197 compatible = "intel,ich9-spi";
199 #address-cells = <1>;
202 compatible = "stmicro,n25q064a",
204 memory-map = <0xff800000 0x00800000>;
206 label = "rw-mrc-cache";
207 reg = <0x006f0000 0x00010000>;
213 compatible = "intel,ich6-gpio";
221 compatible = "intel,ich6-gpio";
229 compatible = "intel,ich6-gpio";
237 compatible = "intel,ich6-gpio";
245 compatible = "intel,ich6-gpio";
253 compatible = "intel,ich6-gpio";
263 compatible = "intel,baytrail-fsp";
264 fsp,mrc-init-tseg-size = <MRC_INIT_TSEG_SIZE_1MB>;
265 fsp,mrc-init-mmio-size = <MRC_INIT_MMIO_SIZE_2048MB>;
266 fsp,mrc-init-spd-addr1 = <0xa0>;
267 fsp,mrc-init-spd-addr2 = <0xa2>;
268 fsp,emmc-boot-mode = <EMMC_BOOT_MODE_AUTO>;
274 fsp,sata-mode = <SATA_MODE_AHCI>;
275 fsp,lpe-mode = <LPE_MODE_PCI>;
276 fsp,lpss-sio-mode = <LPSS_SIO_MODE_PCI>;
288 fsp,igd-dvmt50-pre-alloc = <IGD_DVMT50_PRE_ALLOC_64MB>;
289 fsp,aperture-size = <APERTURE_SIZE_256MB>;
290 fsp,gtt-size = <GTT_SIZE_2MB>;
291 fsp,scc-mode = <SCC_MODE_PCI>;
292 fsp,os-selection = <OS_SELECTION_LINUX>;
293 fsp,emmc45-ddr50-enabled;
294 fsp,emmc45-retune-timer-value = <8>;
296 fsp,enable-memory-down;
297 fsp,memory-down-params {
298 compatible = "intel,baytrail-fsp-mdp";
299 fsp,dram-speed = <DRAM_SPEED_1066MTS>;
300 fsp,dram-type = <DRAM_TYPE_DDR3L>;
302 fsp,dimm-width = <DIMM_WIDTH_X16>;
303 fsp,dimm-density = <DIMM_DENSITY_4GBIT>;
304 fsp,dimm-bus-width = <DIMM_BUS_WIDTH_64BITS>;
305 fsp,dimm-sides = <DIMM_SIDES_1RANKS>;
306 fsp,dimm-tcl = <0xb>;
307 fsp,dimm-trpt-rcd = <0xb>;
308 fsp,dimm-twr = <0xc>;
312 fsp,dimm-tfaw = <0x14>;
318 #include "microcode/m0130673325.dtsi"
321 #include "microcode/m0130679907.dtsi"