2 * Copyright (C) 2017, Bin Meng <bmeng.cn@gmail.com>
4 * SPDX-License-Identifier: GPL-2.0+
6 * From coreboot src/soc/intel/braswell/include/soc/gpio.h
9 #ifndef _BRASWELL_GPIO_H_
10 #define _BRASWELL_GPIO_H_
12 #include <asm/arch/iomap.h>
52 GPIO = 0, /* Native, no need to set PAD_VALUE */
53 GPO = 1, /* GPO, output only in PAD_VALUE */
54 GPI = 2, /* GPI, input only in PAD_VALUE */
65 DISABLE, /* Disable */
99 VOLT_3_3, /* Working on 3.3 Volts */
100 VOLT_1_8, /* Working on 1.8 Volts */
104 DISABLE_HS, /* Disable high speed mode */
105 ENABLE_HS, /* Enable high speed mode */
109 PULL_UP, /* On Die Termination Up */
110 PULL_DOWN, /* On Die Termination Down */
114 DISABLE_OD, /* On Die Termination Disable */
115 ENABLE_OD, /* On Die Termination Enable */
119 P_NONE = 0, /* Pull None */
120 P_20K_L = 1, /* Pull Down 20K */
121 P_5K_L = 2, /* Pull Down 5K */
122 P_1K_L = 4, /* Pull Down 1K */
123 P_20K_H = 9, /* Pull Up 20K */
124 P_5K_H = 10, /* Pull Up 5K */
125 P_1K_H = 12 /* Pull Up 1K */
154 #define TERMINATOR 0xffffffff
156 #define GPIO_FAMILY_CONF(family_name, park_mode, hysctl, vp18_mode, hs_mode, \
157 odt_up_dn, odt_en, curr_src_str, rcomp, family_no, community_offset) { \
158 .confg = ((((park_mode) != NA) ? park_mode << 26 : 0) | \
159 (((hysctl) != NA) ? hysctl << 24 : 0) | \
160 (((vp18_mode) != NA) ? vp18_mode << 21 : 0) | \
161 (((hs_mode) != NA) ? hs_mode << 19 : 0) | \
162 (((odt_up_dn) != NA) ? odt_up_dn << 18 : 0) | \
163 (((odt_en) != NA) ? odt_en << 17 : 0) | \
165 .confg_changes = ((((park_mode) != NA) ? ONE_BIT << 26 : 0) | \
166 (((hysctl) != NA) ? TWO_BIT << 24 : 0) | \
167 (((vp18_mode) != NA) ? ONE_BIT << 21 : 0) | \
168 (((hs_mode) != NA) ? ONE_BIT << 19 : 0) | \
169 (((odt_up_dn) != NA) ? ONE_BIT << 18 : 0) | \
170 (((odt_en) != NA) ? ONE_BIT << 17 : 0) | \
172 .misc = ((rcomp == ENABLE) ? 1 : 0) , \
173 .mmio_addr = (community_offset == TERMINATOR) ? TERMINATOR : \
174 ((family_no != NA) ? (IO_BASE_ADDRESS + community_offset +\
175 (0x80 * family_no) + 0x1080) : 0) , \
179 #define GPIO_PAD_CONF(pad_name, mode_select, mode, gpio_config, gpio_state, \
180 gpio_light_mode, int_type, int_sel, term, open_drain, current_source,\
181 int_mask, glitch, inv_rx_tx, wake_mask, wake_mask_bit, gpe, \
182 mmio_offset, community_offset) { \
183 .confg0 = ((((int_sel) != NA) ? (int_sel << 28) : 0) | \
184 (((glitch) != NA) ? (glitch << 26) : 0) | \
185 (((term) != NA) ? (term << 20) : 0) | \
186 (((mode_select) == GPIO) ? ((mode << 16) | (1 << 15)) : \
188 (((gpio_config) != NA) ? (gpio_config << 8) : 0) | \
189 (((gpio_light_mode) != NA) ? (gpio_light_mode << 7) : 0) | \
190 (((gpio_state) == HIGH) ? 2 : 0)), \
191 .confg0_changes = ((((int_sel) != NA) ? (FOUR_BIT << 28) : 0) | \
192 (((glitch) != NA) ? (TWO_BIT << 26) : 0) | \
193 (((term) != NA) ? (FOUR_BIT << 20) : 0) | \
195 (((gpio_config) != NA) ? (THREE_BIT << 8) : 0) | \
196 (((gpio_light_mode) != NA) ? (ONE_BIT << 7) : 0) | \
197 (((gpio_state) != NA) ? ONE_BIT << 1 : 0)), \
198 .confg1 = ((((current_source) != NA) ? (current_source << 27) : 0) | \
199 (((inv_rx_tx) != NA) ? inv_rx_tx << 4 : 0) | \
200 (((open_drain) != NA) ? open_drain << 3 : 0) | \
201 (((int_type) != NA) ? int_type : 0)), \
202 .confg1_changes = ((((current_source) != NA) ? (ONE_BIT << 27) : 0) | \
203 (((inv_rx_tx) != NA) ? FOUR_BIT << 4 : 0) | \
204 (((open_drain) != NA) ? ONE_BIT << 3 : 0) | \
205 (((int_type) != NA) ? THREE_BIT : 0)), \
206 .community = community_offset, \
207 .mmio_addr = (community_offset == TERMINATOR) ? TERMINATOR : \
208 ((mmio_offset != NA) ? (IO_BASE_ADDRESS + \
209 community_offset + mmio_offset) : 0), \
211 .misc = ((((gpe) != NA) ? (gpe << 0) : 0) | \
212 (((wake_mask) != NA) ? (wake_mask << 2) : 0) | \
213 (((int_mask) != NA) ? (int_mask << 3) : 0)) | \
214 (((wake_mask_bit) != NA) ? (wake_mask_bit << 4) : (NA << 4)) \
217 #endif /* _BRASWELL_GPIO_H_ */