2 ; PCE definitions. By Groepaz/Hitmem.
5 ;; FIXME: optimize zeropage usage
22 ; huc6270 - Video Display Controller (vdc)
24 VDC_MAWR = 0 ; Memory Address Write Register
25 VDC_MARR = 1 ; Memory Address Read Register
26 VDC_VWR = 2 ; VRAM Write Register
27 VDC_VRR = 3 ; VRAM Read Register
28 VDC_CR = 4 ; Control Register
29 VDC_RCR = 5 ; Raster Counter Register
30 VDC_BXR = 6 ; Background X-Scroll Register
31 VDC_BYR = 7 ; Background Y-Scroll Register
32 VDC_MWR = 8 ; Memory-access Width Register
33 VDC_HSR = 9 ; Horizontal Sync Register (?)
34 VDC_HDR =10 ; Horizontal Display Register (?)
35 VDC_VPR =11 ; (unknown)
36 VDC_VDW =12 ; (unknown use)
37 VDC_VCR =13 ; (unknown use)
38 VDC_DCR =14 ; (DMA) Control Register
39 VDC_SOUR =15 ; (DMA) Source Register
40 VDC_DESR =16 ; (DMA) Destination Register
41 VDC_LENR =17 ; (DMA) Length Register
42 VDC_SATB =18 ; Sprite Attribute Table
45 ; Note: absolute addressing mode must be used when writing to this port
51 ; huc6260 - Video Color Encoder (vce)
53 ; The DAC has a palette of 512 colours.
54 ; bitmap of the palette data is this: 0000000gggrrrbbb.
55 ; You can read and write the DAC-registers.
59 VCE_CTRL = $0400 ; write$00 to reset
60 VCE_ADDR_LO = $0402 ; LSB of byte offset into palette
61 VCE_ADDR_HI = $0403 ; MSB of byte offset into palette
62 VCE_DATA_LO = $0404 ; LSB of 16-bit palette data
63 VCE_DATA_HI = $0405 ; MSB of 16-bit palette data
65 ; programmable sound generator (PSG)
81 CDR_MEM_DISABLE = $1803
82 CDR_MEM_ENABLE = $1807