4 * Board functions for B&R LEIT Board
6 * Copyright (C) 2013 Hannes Petermaier <oe5hpm@oevsv.at>
7 * Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com
9 * SPDX-License-Identifier: GPL-2.0+
16 #include <asm/arch/cpu.h>
17 #include <asm/arch/hardware.h>
18 #include <asm/arch/omap.h>
19 #include <asm/arch/ddr_defs.h>
20 #include <asm/arch/clock.h>
21 #include <asm/arch/gpio.h>
22 #include <asm/arch/sys_proto.h>
23 #include <asm/arch/mem.h>
28 #include <power/tps65217.h>
29 #include "../common/bur_common.h"
32 DECLARE_GLOBAL_DATA_PTR;
34 /* --------------------------------------------------------------------------*/
35 /* -- defines for GPIO -- */
36 #define ETHLED_ORANGE (96+16) /* GPIO3_16 */
37 #define REPSWITCH (0+20) /* GPIO0_20 */
40 #if defined(CONFIG_SPL_BUILD)
41 /* TODO: check ram-timing ! */
42 static const struct ddr_data ddr3_data = {
43 .datardsratio0 = MT41K256M16HA125E_RD_DQS,
44 .datawdsratio0 = MT41K256M16HA125E_WR_DQS,
45 .datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE,
46 .datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA,
49 static const struct cmd_control ddr3_cmd_ctrl_data = {
50 .cmd0csratio = MT41K256M16HA125E_RATIO,
51 .cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
53 .cmd1csratio = MT41K256M16HA125E_RATIO,
54 .cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
56 .cmd2csratio = MT41K256M16HA125E_RATIO,
57 .cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
60 static struct emif_regs ddr3_emif_reg_data = {
61 .sdram_config = MT41K256M16HA125E_EMIF_SDCFG,
62 .ref_ctrl = MT41K256M16HA125E_EMIF_SDREF,
63 .sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1,
64 .sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2,
65 .sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3,
66 .zq_config = MT41K256M16HA125E_ZQ_CFG,
67 .emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY,
70 static const struct ctrl_ioregs ddr3_ioregs = {
71 .cm0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
72 .cm1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
73 .cm2ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
74 .dt0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
75 .dt1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
78 #ifdef CONFIG_SPL_OS_BOOT
80 * called from spl_nand.c
81 * return 0 for loading linux, return 1 for loading u-boot
83 int spl_start_uboot(void)
85 if (0 == gpio_get_value(REPSWITCH)) {
87 printf("SPL: entering u-boot instead kernel image.\n");
92 #endif /* CONFIG_SPL_OS_BOOT */
94 #define OSC (V_OSCK/1000000)
95 static const struct dpll_params dpll_ddr3 = { 400, OSC-1, 1, -1, -1, -1, -1};
97 void am33xx_spl_board_init(void)
99 struct cm_perpll *const cmper = (struct cm_perpll *)CM_PER;
100 /*struct cm_wkuppll *const cmwkup = (struct cm_wkuppll *)CM_WKUP;*/
101 struct cm_dpll *const cmdpll = (struct cm_dpll *)CM_DPLL;
104 * in TRM they write a reset value of 1 (=CLK_M_OSC) for the
105 * CLKSEL_TIMER6_CLK Register, in fact reset value is 0, so we need set
106 * the source of timer6 clk to CLK_M_OSC
108 writel(0x01, &cmdpll->clktimer6clk);
110 /* enable additional clocks of modules which are accessed later */
111 u32 *const clk_domains[] = {
112 &cmper->lcdcclkstctrl,
116 u32 *const clk_modules_tsspecific[] = {
118 &cmper->timer5clkctrl,
119 &cmper->timer6clkctrl,
122 do_enable_clocks(clk_domains, clk_modules_tsspecific, 1);
124 /* setup LCD-Pixel Clock */
125 writel(0x2, &cmdpll->clklcdcpixelclk); /* clock comes from perPLL M2 */
130 const struct dpll_params *get_dpll_ddr_params(void)
135 void sdram_init(void)
137 config_ddr(400, &ddr3_ioregs,
140 &ddr3_emif_reg_data, 0);
142 #endif /* CONFIG_SPL_BUILD */
144 /* Basic board specific setup. Pinmux has been handled already. */
147 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
154 #ifdef CONFIG_BOARD_LATE_INIT
155 int board_late_init(void)
157 if (0 == gpio_get_value(REPSWITCH)) {
158 lcd_position_cursor(1, 8);
160 "switching to network-console ... ");
161 setenv("bootcmd", "run netconsole");
165 #endif /* CONFIG_BOARD_LATE_INIT */