3 * Ingo Assmus <ingo.assmus@keymile.com>
5 * based on - Driver for MV64460X ethernet ports
6 * Copyright (C) 2002 rabeeh@galileo.co.il
8 * See file CREDITS for list of people who contributed to this
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 * mv_eth.c - header file for the polled mode GT ethernet driver
36 /* enable Debug outputs */
47 #undef MV64460_CHECKSUM_OFFLOAD
48 /*************************************************************************
49 **************************************************************************
50 **************************************************************************
51 * The first part is the high level driver of the gigE ethernet ports. *
52 **************************************************************************
53 **************************************************************************
54 *************************************************************************/
56 /* Definition for configuring driver */
57 /* #define UPDATE_STATS_BY_SOFTWARE */
58 #undef MV64460_RX_QUEUE_FILL_ON_TASK
62 #define MAGIC_ETH_RUNNING 8031971
63 #define MV64460_INTERNAL_SRAM_SIZE _256K
64 #define EXTRA_BYTES 32
65 #define WRAP ETH_HLEN + 2 + 4 + 16
66 #define BUFFER_MTU dev->mtu + WRAP
67 #define INT_CAUSE_UNMASK_ALL 0x0007ffff
68 #define INT_CAUSE_UNMASK_ALL_EXT 0x0011ffff
69 #ifdef MV64460_RX_FILL_ON_TASK
70 #define INT_CAUSE_MASK_ALL 0x00000000
71 #define INT_CAUSE_CHECK_BITS INT_CAUSE_UNMASK_ALL
72 #define INT_CAUSE_CHECK_BITS_EXT INT_CAUSE_UNMASK_ALL_EXT
75 /* Read/Write to/from MV64460 internal registers */
76 #define MV_REG_READ(offset) my_le32_to_cpu(* (volatile unsigned int *) (INTERNAL_REG_BASE_ADDR + offset))
77 #define MV_REG_WRITE(offset,data) *(volatile unsigned int *) (INTERNAL_REG_BASE_ADDR + offset) = my_cpu_to_le32 (data)
78 #define MV_SET_REG_BITS(regOffset,bits) ((*((volatile unsigned int*)((INTERNAL_REG_BASE_ADDR) + (regOffset)))) |= ((unsigned int)my_cpu_to_le32(bits)))
79 #define MV_RESET_REG_BITS(regOffset,bits) ((*((volatile unsigned int*)((INTERNAL_REG_BASE_ADDR) + (regOffset)))) &= ~((unsigned int)my_cpu_to_le32(bits)))
81 /* Static function declarations */
82 static int mv64460_eth_real_open (struct eth_device *eth);
83 static int mv64460_eth_real_stop (struct eth_device *eth);
84 static struct net_device_stats *mv64460_eth_get_stats (struct eth_device
86 static void eth_port_init_mac_tables (ETH_PORT eth_port_num);
87 static void mv64460_eth_update_stat (struct eth_device *dev);
88 bool db64460_eth_start (struct eth_device *eth);
89 unsigned int eth_read_mib_counter (ETH_PORT eth_port_num,
90 unsigned int mib_offset);
91 int mv64460_eth_receive (struct eth_device *dev);
93 int mv64460_eth_xmit (struct eth_device *, volatile void *packet, int length);
95 #ifndef UPDATE_STATS_BY_SOFTWARE
96 static void mv64460_eth_print_stat (struct eth_device *dev);
99 extern unsigned int INTERNAL_REG_BASE_ADDR;
101 /*************************************************
102 *Helper functions - used inside the driver only *
103 *************************************************/
105 void print_globals (struct eth_device *dev)
107 printf ("Ethernet PRINT_Globals-Debug function\n");
108 printf ("Base Address for ETH_PORT_INFO: %08x\n",
109 (unsigned int) dev->priv);
110 printf ("Base Address for mv64460_eth_priv: %08x\n",
111 (unsigned int) &(((ETH_PORT_INFO *) dev->priv)->
114 printf ("GT Internal Base Address: %08x\n",
115 INTERNAL_REG_BASE_ADDR);
116 printf ("Base Address for TX-DESCs: %08x Number of allocated Buffers %d\n", (unsigned int) ((ETH_PORT_INFO *) dev->priv)->p_tx_desc_area_base[0], MV64460_TX_QUEUE_SIZE);
117 printf ("Base Address for RX-DESCs: %08x Number of allocated Buffers %d\n", (unsigned int) ((ETH_PORT_INFO *) dev->priv)->p_rx_desc_area_base[0], MV64460_RX_QUEUE_SIZE);
118 printf ("Base Address for RX-Buffer: %08x allocated Bytes %d\n",
119 (unsigned int) ((ETH_PORT_INFO *) dev->priv)->
121 (MV64460_RX_QUEUE_SIZE * MV64460_RX_BUFFER_SIZE) + 32);
122 printf ("Base Address for TX-Buffer: %08x allocated Bytes %d\n",
123 (unsigned int) ((ETH_PORT_INFO *) dev->priv)->
125 (MV64460_TX_QUEUE_SIZE * MV64460_TX_BUFFER_SIZE) + 32);
129 #define my_cpu_to_le32(x) my_le32_to_cpu((x))
131 unsigned long my_le32_to_cpu (unsigned long x)
133 return (((x & 0x000000ffU) << 24) |
134 ((x & 0x0000ff00U) << 8) |
135 ((x & 0x00ff0000U) >> 8) | ((x & 0xff000000U) >> 24));
139 /**********************************************************************
140 * mv64460_eth_print_phy_status
142 * Prints gigabit ethenret phy status
144 * Input : pointer to ethernet interface network device structure
146 **********************************************************************/
148 static void mv64460_eth_print_phy_status (struct eth_device *dev)
150 struct mv64460_eth_priv *port_private;
151 unsigned int port_num;
152 ETH_PORT_INFO *ethernet_private = (ETH_PORT_INFO *) dev->priv;
153 unsigned int port_status, phy_reg_data;
156 (struct mv64460_eth_priv *) ethernet_private->port_private;
157 port_num = port_private->port_num;
159 /* Check Link status on phy */
160 eth_port_read_smi_reg (port_num, 1, &phy_reg_data);
161 if (!(phy_reg_data & 0x20)) {
162 printf ("Ethernet port changed link status to DOWN\n");
165 MV_REG_READ (MV64460_ETH_PORT_STATUS_REG (port_num));
166 printf ("Ethernet status port %d: Link up", port_num);
168 (port_status & BIT2) ? "Full Duplex" : "Half Duplex");
169 if (port_status & BIT4)
170 printf (", Speed 1 Gbps");
173 (port_status & BIT5) ? "Speed 100 Mbps" :
179 /**********************************************************************
180 * u-boot entry functions for mv64460_eth
182 **********************************************************************/
183 int db64460_eth_probe (struct eth_device *dev)
185 return ((int) db64460_eth_start (dev));
188 int db64460_eth_poll (struct eth_device *dev)
190 return mv64460_eth_receive (dev);
193 int db64460_eth_transmit(struct eth_device *dev, void *packet, int length)
195 mv64460_eth_xmit (dev, packet, length);
199 void db64460_eth_disable (struct eth_device *dev)
201 mv64460_eth_stop (dev);
205 void mv6446x_eth_initialize (bd_t * bis)
207 struct eth_device *dev;
208 ETH_PORT_INFO *ethernet_private;
209 struct mv64460_eth_priv *port_private;
211 char *s, *e, buf[64];
213 for (devnum = 0; devnum < MV_ETH_DEVS; devnum++) {
214 dev = calloc (sizeof (*dev), 1);
216 printf ("%s: mv_enet%d allocation failure, %s\n",
217 __FUNCTION__, devnum, "eth_device structure");
221 /* must be less than sizeof(dev->name) */
222 sprintf (dev->name, "mv_enet%d", devnum);
225 printf ("Initializing %s\n", dev->name);
228 /* Extract the MAC address from the environment */
242 default: /* this should never happen */
243 printf ("%s: Invalid device number %d\n",
244 __FUNCTION__, devnum);
248 temp = getenv_f(s, buf, sizeof (buf));
249 s = (temp > 0) ? buf : NULL;
252 printf ("Setting MAC %d to %s\n", devnum, s);
254 for (x = 0; x < 6; ++x) {
255 dev->enetaddr[x] = s ? simple_strtoul (s, &e, 16) : 0;
257 s = (*e) ? e + 1 : e;
259 /* ronen - set the MAC addr in the HW */
260 eth_port_uc_addr_set (devnum, dev->enetaddr, 0);
262 dev->init = (void *) db64460_eth_probe;
263 dev->halt = (void *) ethernet_phy_reset;
264 dev->send = (void *) db64460_eth_transmit;
265 dev->recv = (void *) db64460_eth_poll;
267 ethernet_private = calloc (sizeof (*ethernet_private), 1);
268 dev->priv = (void *)ethernet_private;
269 if (!ethernet_private) {
270 printf ("%s: %s allocation failure, %s\n",
271 __FUNCTION__, dev->name,
272 "Private Device Structure");
276 /* start with an zeroed ETH_PORT_INFO */
277 memset (ethernet_private, 0, sizeof (ETH_PORT_INFO));
278 memcpy (ethernet_private->port_mac_addr, dev->enetaddr, 6);
280 /* set pointer to memory for stats data structure etc... */
281 port_private = calloc (sizeof (*ethernet_private), 1);
282 ethernet_private->port_private = (void *)port_private;
284 printf ("%s: %s allocation failure, %s\n",
285 __FUNCTION__, dev->name,
286 "Port Private Device Structure");
288 free (ethernet_private);
293 port_private->stats =
294 calloc (sizeof (struct net_device_stats), 1);
295 if (!port_private->stats) {
296 printf ("%s: %s allocation failure, %s\n",
297 __FUNCTION__, dev->name,
298 "Net stat Structure");
301 free (ethernet_private);
305 memset (ethernet_private->port_private, 0,
306 sizeof (struct mv64460_eth_priv));
309 ethernet_private->port_num = ETH_0;
312 ethernet_private->port_num = ETH_1;
315 ethernet_private->port_num = ETH_2;
318 printf ("Invalid device number %d\n", devnum);
322 port_private->port_num = devnum;
324 * Read MIB counter on the GT in order to reset them,
325 * then zero all the stats fields in memory
327 mv64460_eth_update_stat (dev);
328 memset (port_private->stats, 0,
329 sizeof (struct net_device_stats));
330 /* Extract the MAC address from the environment */
344 default: /* this should never happen */
345 printf ("%s: Invalid device number %d\n",
346 __FUNCTION__, devnum);
350 temp = getenv_f(s, buf, sizeof (buf));
351 s = (temp > 0) ? buf : NULL;
354 printf ("Setting MAC %d to %s\n", devnum, s);
356 for (x = 0; x < 6; ++x) {
357 dev->enetaddr[x] = s ? simple_strtoul (s, &e, 16) : 0;
359 s = (*e) ? e + 1 : e;
362 DP (printf ("Allocating descriptor and buffer rings\n"));
364 ethernet_private->p_rx_desc_area_base[0] =
365 (ETH_RX_DESC *) memalign (16,
366 RX_DESC_ALIGNED_SIZE *
367 MV64460_RX_QUEUE_SIZE + 1);
368 ethernet_private->p_tx_desc_area_base[0] =
369 (ETH_TX_DESC *) memalign (16,
370 TX_DESC_ALIGNED_SIZE *
371 MV64460_TX_QUEUE_SIZE + 1);
373 ethernet_private->p_rx_buffer_base[0] =
374 (char *) memalign (16,
375 MV64460_RX_QUEUE_SIZE *
376 MV64460_TX_BUFFER_SIZE + 1);
377 ethernet_private->p_tx_buffer_base[0] =
378 (char *) memalign (16,
379 MV64460_RX_QUEUE_SIZE *
380 MV64460_TX_BUFFER_SIZE + 1);
383 /* DEBUG OUTPUT prints adresses of globals */
389 DP (printf ("%s: exit\n", __FUNCTION__));
393 /**********************************************************************
396 * This function is called when openning the network device. The function
397 * should initialize all the hardware, initialize cyclic Rx/Tx
398 * descriptors chain and buffers and allocate an IRQ to the network
401 * Input : a pointer to the network device structure
402 * / / ronen - changed the output to match net/eth.c needs
403 * Output : nonzero of success , zero if fails.
405 **********************************************************************/
407 int mv64460_eth_open (struct eth_device *dev)
409 return (mv64460_eth_real_open (dev));
412 /* Helper function for mv64460_eth_open */
413 static int mv64460_eth_real_open (struct eth_device *dev)
417 ETH_PORT_INFO *ethernet_private;
418 struct mv64460_eth_priv *port_private;
419 unsigned int port_num;
422 ethernet_private = (ETH_PORT_INFO *) dev->priv;
423 /* ronen - when we update the MAC env params we only update dev->enetaddr
424 see ./net/eth.c eth_set_enetaddr() */
425 memcpy (ethernet_private->port_mac_addr, dev->enetaddr, 6);
428 (struct mv64460_eth_priv *) ethernet_private->port_private;
429 port_num = port_private->port_num;
432 MV_REG_WRITE (MV64460_ETH_RECEIVE_QUEUE_COMMAND_REG (port_num),
435 /* Clear the ethernet port interrupts */
436 MV_REG_WRITE (MV64460_ETH_INTERRUPT_CAUSE_REG (port_num), 0);
437 MV_REG_WRITE (MV64460_ETH_INTERRUPT_CAUSE_EXTEND_REG (port_num), 0);
439 /* Unmask RX buffer and TX end interrupt */
440 MV_REG_WRITE (MV64460_ETH_INTERRUPT_MASK_REG (port_num),
441 INT_CAUSE_UNMASK_ALL);
443 /* Unmask phy and link status changes interrupts */
444 MV_REG_WRITE (MV64460_ETH_INTERRUPT_EXTEND_MASK_REG (port_num),
445 INT_CAUSE_UNMASK_ALL_EXT);
447 /* Set phy address of the port */
448 ethernet_private->port_phy_addr = 0x8 + port_num;
450 /* Activate the DMA channels etc */
451 eth_port_init (ethernet_private);
454 /* "Allocate" setup TX rings */
456 for (queue = 0; queue < MV64460_TX_QUEUE_NUM; queue++) {
459 port_private->tx_ring_size[queue] = MV64460_TX_QUEUE_SIZE;
460 size = (port_private->tx_ring_size[queue] * TX_DESC_ALIGNED_SIZE); /*size = no of DESCs times DESC-size */
461 ethernet_private->tx_desc_area_size[queue] = size;
463 /* first clear desc area completely */
464 memset ((void *) ethernet_private->p_tx_desc_area_base[queue],
465 0, ethernet_private->tx_desc_area_size[queue]);
467 /* initialize tx desc ring with low level driver */
468 if (ether_init_tx_desc_ring
469 (ethernet_private, ETH_Q0,
470 port_private->tx_ring_size[queue],
471 MV64460_TX_BUFFER_SIZE /* Each Buffer is 1600 Byte */ ,
472 (unsigned int) ethernet_private->
473 p_tx_desc_area_base[queue],
474 (unsigned int) ethernet_private->
475 p_tx_buffer_base[queue]) == false)
476 printf ("### Error initializing TX Ring\n");
479 /* "Allocate" setup RX rings */
480 for (queue = 0; queue < MV64460_RX_QUEUE_NUM; queue++) {
483 /* Meantime RX Ring are fixed - but must be configurable by user */
484 port_private->rx_ring_size[queue] = MV64460_RX_QUEUE_SIZE;
485 size = (port_private->rx_ring_size[queue] *
486 RX_DESC_ALIGNED_SIZE);
487 ethernet_private->rx_desc_area_size[queue] = size;
489 /* first clear desc area completely */
490 memset ((void *) ethernet_private->p_rx_desc_area_base[queue],
491 0, ethernet_private->rx_desc_area_size[queue]);
492 if ((ether_init_rx_desc_ring
493 (ethernet_private, ETH_Q0,
494 port_private->rx_ring_size[queue],
495 MV64460_RX_BUFFER_SIZE /* Each Buffer is 1600 Byte */ ,
496 (unsigned int) ethernet_private->
497 p_rx_desc_area_base[queue],
498 (unsigned int) ethernet_private->
499 p_rx_buffer_base[queue])) == false)
500 printf ("### Error initializing RX Ring\n");
503 eth_port_start (ethernet_private);
505 /* Set maximum receive buffer to 9700 bytes */
506 MV_REG_WRITE (MV64460_ETH_PORT_SERIAL_CONTROL_REG (port_num),
509 (MV64460_ETH_PORT_SERIAL_CONTROL_REG (port_num))
513 * Set ethernet MTU for leaky bucket mechanism to 0 - this will
514 * disable the leaky bucket mechanism .
517 MV_REG_WRITE (MV64460_ETH_MAXIMUM_TRANSMIT_UNIT (port_num), 0);
518 MV_REG_READ (MV64460_ETH_PORT_STATUS_REG (port_num));
520 /* Check Link status on phy */
521 eth_port_read_smi_reg (port_num, 1, &phy_reg_data);
522 if (!(phy_reg_data & 0x20)) {
524 if ((ethernet_phy_reset (port_num)) != true) {
525 printf ("$$ Warnning: No link on port %d \n",
529 eth_port_read_smi_reg (port_num, 1, &phy_reg_data);
530 if (!(phy_reg_data & 0x20)) {
531 printf ("### Error: Phy is not active\n");
536 mv64460_eth_print_phy_status (dev);
538 port_private->eth_running = MAGIC_ETH_RUNNING;
543 static int mv64460_eth_free_tx_rings (struct eth_device *dev)
546 ETH_PORT_INFO *ethernet_private;
547 struct mv64460_eth_priv *port_private;
548 unsigned int port_num;
549 volatile ETH_TX_DESC *p_tx_curr_desc;
551 ethernet_private = (ETH_PORT_INFO *) dev->priv;
553 (struct mv64460_eth_priv *) ethernet_private->port_private;
554 port_num = port_private->port_num;
557 MV_REG_WRITE (MV64460_ETH_TRANSMIT_QUEUE_COMMAND_REG (port_num),
561 DP (printf ("Clearing previously allocated TX queues... "));
562 for (queue = 0; queue < MV64460_TX_QUEUE_NUM; queue++) {
563 /* Free on TX rings */
564 for (p_tx_curr_desc =
565 ethernet_private->p_tx_desc_area_base[queue];
566 ((unsigned int) p_tx_curr_desc <= (unsigned int)
567 ethernet_private->p_tx_desc_area_base[queue] +
568 ethernet_private->tx_desc_area_size[queue]);
570 (ETH_TX_DESC *) ((unsigned int) p_tx_curr_desc +
571 TX_DESC_ALIGNED_SIZE)) {
572 /* this is inside for loop */
573 if (p_tx_curr_desc->return_info != 0) {
574 p_tx_curr_desc->return_info = 0;
575 DP (printf ("freed\n"));
578 DP (printf ("Done\n"));
583 static int mv64460_eth_free_rx_rings (struct eth_device *dev)
586 ETH_PORT_INFO *ethernet_private;
587 struct mv64460_eth_priv *port_private;
588 unsigned int port_num;
589 volatile ETH_RX_DESC *p_rx_curr_desc;
591 ethernet_private = (ETH_PORT_INFO *) dev->priv;
593 (struct mv64460_eth_priv *) ethernet_private->port_private;
594 port_num = port_private->port_num;
598 MV_REG_WRITE (MV64460_ETH_RECEIVE_QUEUE_COMMAND_REG (port_num),
602 DP (printf ("Clearing previously allocated RX queues... "));
603 for (queue = 0; queue < MV64460_RX_QUEUE_NUM; queue++) {
604 /* Free preallocated skb's on RX rings */
605 for (p_rx_curr_desc =
606 ethernet_private->p_rx_desc_area_base[queue];
607 (((unsigned int) p_rx_curr_desc <
608 ((unsigned int) ethernet_private->
609 p_rx_desc_area_base[queue] +
610 ethernet_private->rx_desc_area_size[queue])));
612 (ETH_RX_DESC *) ((unsigned int) p_rx_curr_desc +
613 RX_DESC_ALIGNED_SIZE)) {
614 if (p_rx_curr_desc->return_info != 0) {
615 p_rx_curr_desc->return_info = 0;
616 DP (printf ("freed\n"));
619 DP (printf ("Done\n"));
624 /**********************************************************************
627 * This function is used when closing the network device.
628 * It updates the hardware,
629 * release all memory that holds buffers and descriptors and release the IRQ.
630 * Input : a pointer to the device structure
631 * Output : zero if success , nonzero if fails
632 *********************************************************************/
634 int mv64460_eth_stop (struct eth_device *dev)
636 /* Disable all gigE address decoder */
637 MV_REG_WRITE (MV64460_ETH_BASE_ADDR_ENABLE_REG, 0x3f);
638 DP (printf ("%s Ethernet stop called ... \n", __FUNCTION__));
639 mv64460_eth_real_stop (dev);
644 /* Helper function for mv64460_eth_stop */
646 static int mv64460_eth_real_stop (struct eth_device *dev)
648 ETH_PORT_INFO *ethernet_private;
649 struct mv64460_eth_priv *port_private;
650 unsigned int port_num;
652 ethernet_private = (ETH_PORT_INFO *) dev->priv;
654 (struct mv64460_eth_priv *) ethernet_private->port_private;
655 port_num = port_private->port_num;
658 mv64460_eth_free_tx_rings (dev);
659 mv64460_eth_free_rx_rings (dev);
661 eth_port_reset (ethernet_private->port_num);
662 /* Disable ethernet port interrupts */
663 MV_REG_WRITE (MV64460_ETH_INTERRUPT_CAUSE_REG (port_num), 0);
664 MV_REG_WRITE (MV64460_ETH_INTERRUPT_CAUSE_EXTEND_REG (port_num), 0);
665 /* Mask RX buffer and TX end interrupt */
666 MV_REG_WRITE (MV64460_ETH_INTERRUPT_MASK_REG (port_num), 0);
667 /* Mask phy and link status changes interrupts */
668 MV_REG_WRITE (MV64460_ETH_INTERRUPT_EXTEND_MASK_REG (port_num), 0);
669 MV_RESET_REG_BITS (MV64460_CPU_INTERRUPT0_MASK_HIGH,
671 /* Print Network statistics */
672 #ifndef UPDATE_STATS_BY_SOFTWARE
674 * Print statistics (only if ethernet is running),
675 * then zero all the stats fields in memory
677 if (port_private->eth_running == MAGIC_ETH_RUNNING) {
678 port_private->eth_running = 0;
679 mv64460_eth_print_stat (dev);
681 memset (port_private->stats, 0, sizeof (struct net_device_stats));
683 DP (printf ("\nEthernet stopped ... \n"));
688 /**********************************************************************
689 * mv64460_eth_start_xmit
691 * This function is queues a packet in the Tx descriptor for
694 * Input : skb - a pointer to socket buffer
695 * dev - a pointer to the required port
697 * Output : zero upon success
698 **********************************************************************/
700 int mv64460_eth_xmit (struct eth_device *dev, volatile void *dataPtr,
703 ETH_PORT_INFO *ethernet_private;
704 struct mv64460_eth_priv *port_private;
706 ETH_FUNC_RET_STATUS status;
707 struct net_device_stats *stats;
708 ETH_FUNC_RET_STATUS release_result;
710 ethernet_private = (ETH_PORT_INFO *) dev->priv;
712 (struct mv64460_eth_priv *) ethernet_private->port_private;
714 stats = port_private->stats;
716 /* Update packet info data structure */
717 pkt_info.cmd_sts = ETH_TX_FIRST_DESC | ETH_TX_LAST_DESC; /* DMA owned, first last */
718 pkt_info.byte_cnt = dataSize;
719 pkt_info.buf_ptr = (unsigned int) dataPtr;
720 pkt_info.return_info = 0;
722 status = eth_port_send (ethernet_private, ETH_Q0, &pkt_info);
723 if ((status == ETH_ERROR) || (status == ETH_QUEUE_FULL)) {
724 printf ("Error on transmitting packet ..");
725 if (status == ETH_QUEUE_FULL)
726 printf ("ETH Queue is full. \n");
727 if (status == ETH_QUEUE_LAST_RESOURCE)
728 printf ("ETH Queue: using last available resource. \n");
732 /* Update statistics and start of transmittion time */
733 stats->tx_bytes += dataSize;
736 /* Check if packet(s) is(are) transmitted correctly (release everything) */
739 eth_tx_return_desc (ethernet_private, ETH_Q0,
741 switch (release_result) {
743 DP (printf ("descriptor released\n"));
744 if (pkt_info.cmd_sts & BIT0) {
745 printf ("Error in TX\n");
751 DP (printf ("transmission still in process\n"));
755 printf ("routine can not access Tx desc ring\n");
759 DP (printf ("the routine has nothing to release\n"));
761 default: /* should not happen */
764 } while (release_result == ETH_OK);
767 return 0; /* success */
769 return 1; /* Failed - higher layers will free the skb */
772 /**********************************************************************
773 * mv64460_eth_receive
775 * This function is forward packets that are received from the port's
776 * queues toward kernel core or FastRoute them to another interface.
778 * Input : dev - a pointer to the required interface
779 * max - maximum number to receive (0 means unlimted)
781 * Output : number of served packets
782 **********************************************************************/
784 int mv64460_eth_receive (struct eth_device *dev)
786 ETH_PORT_INFO *ethernet_private;
787 struct mv64460_eth_priv *port_private;
789 struct net_device_stats *stats;
791 ethernet_private = (ETH_PORT_INFO *) dev->priv;
793 (struct mv64460_eth_priv *) ethernet_private->port_private;
794 stats = port_private->stats;
796 while ((eth_port_receive (ethernet_private, ETH_Q0, &pkt_info) ==
800 if (pkt_info.byte_cnt != 0) {
801 printf ("%s: Received %d byte Packet @ 0x%x\n",
802 __FUNCTION__, pkt_info.byte_cnt,
806 /* Update statistics. Note byte count includes 4 byte CRC count */
808 stats->rx_bytes += pkt_info.byte_cnt;
811 * In case received a packet without first / last bits on OR the error
812 * summary bit is on, the packets needs to be dropeed.
815 cmd_sts & (ETH_RX_FIRST_DESC | ETH_RX_LAST_DESC)) !=
816 (ETH_RX_FIRST_DESC | ETH_RX_LAST_DESC))
817 || (pkt_info.cmd_sts & ETH_ERROR_SUMMARY)) {
820 printf ("Received packet spread on multiple descriptors\n");
822 /* Is this caused by an error ? */
823 if (pkt_info.cmd_sts & ETH_ERROR_SUMMARY) {
827 /* free these descriptors again without forwarding them to the higher layers */
828 pkt_info.buf_ptr &= ~0x7; /* realign buffer again */
829 pkt_info.byte_cnt = 0x0000; /* Reset Byte count */
831 if (eth_rx_return_buff
832 (ethernet_private, ETH_Q0, &pkt_info) != ETH_OK) {
833 printf ("Error while returning the RX Desc to Ring\n");
835 DP (printf ("RX Desc returned to Ring\n"));
837 /* /free these descriptors again */
840 /* !!! call higher layer processing */
842 printf ("\nNow send it to upper layer protocols (NetReceive) ...\n");
844 /* let the upper layer handle the packet */
845 NetReceive ((uchar *) pkt_info.buf_ptr,
846 (int) pkt_info.byte_cnt);
848 /* **************************************************************** */
849 /* free descriptor */
850 pkt_info.buf_ptr &= ~0x7; /* realign buffer again */
851 pkt_info.byte_cnt = 0x0000; /* Reset Byte count */
853 ("RX: pkt_info.buf_ptr = %x\n",
855 if (eth_rx_return_buff
856 (ethernet_private, ETH_Q0, &pkt_info) != ETH_OK) {
857 printf ("Error while returning the RX Desc to Ring\n");
859 DP (printf ("RX Desc returned to Ring\n"));
862 /* **************************************************************** */
866 mv64460_eth_get_stats (dev); /* update statistics */
870 /**********************************************************************
871 * mv64460_eth_get_stats
873 * Returns a pointer to the interface statistics.
875 * Input : dev - a pointer to the required interface
877 * Output : a pointer to the interface's statistics
878 **********************************************************************/
880 static struct net_device_stats *mv64460_eth_get_stats (struct eth_device *dev)
882 ETH_PORT_INFO *ethernet_private;
883 struct mv64460_eth_priv *port_private;
885 ethernet_private = (ETH_PORT_INFO *) dev->priv;
887 (struct mv64460_eth_priv *) ethernet_private->port_private;
889 mv64460_eth_update_stat (dev);
891 return port_private->stats;
895 /**********************************************************************
896 * mv64460_eth_update_stat
898 * Update the statistics structure in the private data structure
900 * Input : pointer to ethernet interface network device structure
902 **********************************************************************/
904 static void mv64460_eth_update_stat (struct eth_device *dev)
906 ETH_PORT_INFO *ethernet_private;
907 struct mv64460_eth_priv *port_private;
908 struct net_device_stats *stats;
910 ethernet_private = (ETH_PORT_INFO *) dev->priv;
912 (struct mv64460_eth_priv *) ethernet_private->port_private;
913 stats = port_private->stats;
915 /* These are false updates */
916 stats->rx_packets += (unsigned long)
917 eth_read_mib_counter (ethernet_private->port_num,
918 ETH_MIB_GOOD_FRAMES_RECEIVED);
919 stats->tx_packets += (unsigned long)
920 eth_read_mib_counter (ethernet_private->port_num,
921 ETH_MIB_GOOD_FRAMES_SENT);
922 stats->rx_bytes += (unsigned long)
923 eth_read_mib_counter (ethernet_private->port_num,
924 ETH_MIB_GOOD_OCTETS_RECEIVED_LOW);
926 * Ideally this should be as follows -
928 * stats->rx_bytes += stats->rx_bytes +
929 * ((unsigned long) ethReadMibCounter (ethernet_private->port_num ,
930 * ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH) << 32);
932 * But the unsigned long in PowerPC and MIPS are 32bit. So the next read
933 * is just a dummy read for proper work of the GigE port
935 eth_read_mib_counter (ethernet_private->port_num,
936 ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH);
937 stats->tx_bytes += (unsigned long)
938 eth_read_mib_counter (ethernet_private->port_num,
939 ETH_MIB_GOOD_OCTETS_SENT_LOW);
940 eth_read_mib_counter (ethernet_private->port_num,
941 ETH_MIB_GOOD_OCTETS_SENT_HIGH);
942 stats->rx_errors += (unsigned long)
943 eth_read_mib_counter (ethernet_private->port_num,
944 ETH_MIB_MAC_RECEIVE_ERROR);
946 /* Rx dropped is for received packet with CRC error */
948 (unsigned long) eth_read_mib_counter (ethernet_private->
950 ETH_MIB_BAD_CRC_EVENT);
951 stats->multicast += (unsigned long)
952 eth_read_mib_counter (ethernet_private->port_num,
953 ETH_MIB_MULTICAST_FRAMES_RECEIVED);
955 (unsigned long) eth_read_mib_counter (ethernet_private->
958 (unsigned long) eth_read_mib_counter (ethernet_private->
960 ETH_MIB_LATE_COLLISION);
961 /* detailed rx errors */
962 stats->rx_length_errors +=
963 (unsigned long) eth_read_mib_counter (ethernet_private->
965 ETH_MIB_UNDERSIZE_RECEIVED)
967 (unsigned long) eth_read_mib_counter (ethernet_private->
969 ETH_MIB_OVERSIZE_RECEIVED);
970 /* detailed tx errors */
973 #ifndef UPDATE_STATS_BY_SOFTWARE
974 /**********************************************************************
975 * mv64460_eth_print_stat
977 * Update the statistics structure in the private data structure
979 * Input : pointer to ethernet interface network device structure
981 **********************************************************************/
983 static void mv64460_eth_print_stat (struct eth_device *dev)
985 ETH_PORT_INFO *ethernet_private;
986 struct mv64460_eth_priv *port_private;
987 struct net_device_stats *stats;
989 ethernet_private = (ETH_PORT_INFO *) dev->priv;
991 (struct mv64460_eth_priv *) ethernet_private->port_private;
992 stats = port_private->stats;
994 /* These are false updates */
995 printf ("\n### Network statistics: ###\n");
996 printf ("--------------------------\n");
997 printf (" Packets received: %ld\n", stats->rx_packets);
998 printf (" Packets send: %ld\n", stats->tx_packets);
999 printf (" Received bytes: %ld\n", stats->rx_bytes);
1000 printf (" Send bytes: %ld\n", stats->tx_bytes);
1001 if (stats->rx_errors != 0)
1002 printf (" Rx Errors: %ld\n",
1004 if (stats->rx_dropped != 0)
1005 printf (" Rx dropped (CRC Errors): %ld\n",
1007 if (stats->multicast != 0)
1008 printf (" Rx mulicast frames: %ld\n",
1010 if (stats->collisions != 0)
1011 printf (" No. of collisions: %ld\n",
1013 if (stats->rx_length_errors != 0)
1014 printf (" Rx length errors: %ld\n",
1015 stats->rx_length_errors);
1019 /**************************************************************************
1020 *network_start - Network Kick Off Routine UBoot
1023 **************************************************************************/
1025 bool db64460_eth_start (struct eth_device *dev)
1027 return (mv64460_eth_open (dev)); /* calls real open */
1030 /*************************************************************************
1031 **************************************************************************
1032 **************************************************************************
1033 * The second part is the low level driver of the gigE ethernet ports. *
1034 **************************************************************************
1035 **************************************************************************
1036 *************************************************************************/
1038 * based on Linux code
1039 * arch/powerpc/galileo/EVB64460/mv64460_eth.c - Driver for MV64460X ethernet ports
1040 * Copyright (C) 2002 rabeeh@galileo.co.il
1042 * This program is free software; you can redistribute it and/or
1043 * modify it under the terms of the GNU General Public License
1044 * as published by the Free Software Foundation; either version 2
1045 * of the License, or (at your option) any later version.
1047 * This program is distributed in the hope that it will be useful,
1048 * but WITHOUT ANY WARRANTY; without even the implied warranty of
1049 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
1050 * GNU General Public License for more details.
1052 * You should have received a copy of the GNU General Public License
1053 * along with this program; if not, write to the Free Software
1054 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
1058 /********************************************************************************
1059 * Marvell's Gigabit Ethernet controller low level driver
1062 * This file introduce low level API to Marvell's Gigabit Ethernet
1063 * controller. This Gigabit Ethernet Controller driver API controls
1064 * 1) Operations (i.e. port init, start, reset etc').
1065 * 2) Data flow (i.e. port send, receive etc').
1066 * Each Gigabit Ethernet port is controlled via ETH_PORT_INFO
1068 * This struct includes user configuration information as well as
1069 * driver internal data needed for its operations.
1071 * Supported Features:
1072 * - This low level driver is OS independent. Allocating memory for
1073 * the descriptor rings and buffers are not within the scope of
1075 * - The user is free from Rx/Tx queue managing.
1076 * - This low level driver introduce functionality API that enable
1077 * the to operate Marvell's Gigabit Ethernet Controller in a
1079 * - Simple Gigabit Ethernet port operation API.
1080 * - Simple Gigabit Ethernet port data flow API.
1081 * - Data flow and operation API support per queue functionality.
1082 * - Support cached descriptors for better performance.
1083 * - Enable access to all four DRAM banks and internal SRAM memory
1085 * - PHY access and control API.
1086 * - Port control register configuration API.
1087 * - Full control over Unicast and Multicast MAC configurations.
1091 * Initialization phase
1092 * This phase complete the initialization of the ETH_PORT_INFO
1094 * User information regarding port configuration has to be set
1095 * prior to calling the port initialization routine. For example,
1096 * the user has to assign the port_phy_addr field which is board
1097 * depended parameter.
1098 * In this phase any port Tx/Rx activity is halted, MIB counters
1099 * are cleared, PHY address is set according to user parameter and
1100 * access to DRAM and internal SRAM memory spaces.
1102 * Driver ring initialization
1103 * Allocating memory for the descriptor rings and buffers is not
1104 * within the scope of this driver. Thus, the user is required to
1105 * allocate memory for the descriptors ring and buffers. Those
1106 * memory parameters are used by the Rx and Tx ring initialization
1107 * routines in order to curve the descriptor linked list in a form
1109 * Note: Pay special attention to alignment issues when using
1110 * cached descriptors/buffers. In this phase the driver store
1111 * information in the ETH_PORT_INFO struct regarding each queue
1115 * This phase prepares the Ethernet port for Rx and Tx activity.
1116 * It uses the information stored in the ETH_PORT_INFO struct to
1117 * initialize the various port registers.
1120 * All packet references to/from the driver are done using PKT_INFO
1122 * This struct is a unified struct used with Rx and Tx operations.
1123 * This way the user is not required to be familiar with neither
1124 * Tx nor Rx descriptors structures.
1125 * The driver's descriptors rings are management by indexes.
1126 * Those indexes controls the ring resources and used to indicate
1127 * a SW resource error:
1129 * This index points to the current available resource for use. For
1130 * example in Rx process this index will point to the descriptor
1131 * that will be passed to the user upon calling the receive routine.
1132 * In Tx process, this index will point to the descriptor
1133 * that will be assigned with the user packet info and transmitted.
1135 * This index points to the descriptor that need to restore its
1136 * resources. For example in Rx process, using the Rx buffer return
1137 * API will attach the buffer returned in packet info to the
1138 * descriptor pointed by 'used'. In Tx process, using the Tx
1139 * descriptor return will merely return the user packet info with
1140 * the command status of the transmitted buffer pointed by the
1141 * 'used' index. Nevertheless, it is essential to use this routine
1142 * to update the 'used' index.
1144 * This index supports Tx Scatter-Gather. It points to the first
1145 * descriptor of a packet assembled of multiple buffers. For example
1146 * when in middle of Such packet we have a Tx resource error the
1147 * 'curr' index get the value of 'first' to indicate that the ring
1148 * returned to its state before trying to transmit this packet.
1150 * Receive operation:
1151 * The eth_port_receive API set the packet information struct,
1152 * passed by the caller, with received information from the
1153 * 'current' SDMA descriptor.
1154 * It is the user responsibility to return this resource back
1155 * to the Rx descriptor ring to enable the reuse of this source.
1156 * Return Rx resource is done using the eth_rx_return_buff API.
1158 * Transmit operation:
1159 * The eth_port_send API supports Scatter-Gather which enables to
1160 * send a packet spanned over multiple buffers. This means that
1161 * for each packet info structure given by the user and put into
1162 * the Tx descriptors ring, will be transmitted only if the 'LAST'
1163 * bit will be set in the packet info command status field. This
1164 * API also consider restriction regarding buffer alignments and
1166 * The user must return a Tx resource after ensuring the buffer
1167 * has been transmitted to enable the Tx ring indexes to update.
1170 * This device is on-board. No jumper diagram is necessary.
1172 * EXTERNAL INTERFACE
1174 * Prior to calling the initialization routine eth_port_init() the user
1175 * must set the following fields under ETH_PORT_INFO struct:
1176 * port_num User Ethernet port number.
1177 * port_phy_addr User PHY address of Ethernet port.
1178 * port_mac_addr[6] User defined port MAC address.
1179 * port_config User port configuration value.
1180 * port_config_extend User port config extend value.
1181 * port_sdma_config User port SDMA config value.
1182 * port_serial_control User port serial control value.
1183 * *port_virt_to_phys () User function to cast virtual addr to CPU bus addr.
1184 * *port_private User scratch pad for user specific data structures.
1186 * This driver introduce a set of default values:
1187 * PORT_CONFIG_VALUE Default port configuration value
1188 * PORT_CONFIG_EXTEND_VALUE Default port extend configuration value
1189 * PORT_SDMA_CONFIG_VALUE Default sdma control value
1190 * PORT_SERIAL_CONTROL_VALUE Default port serial control value
1192 * This driver data flow is done using the PKT_INFO struct which is
1193 * a unified struct for Rx and Tx operations:
1194 * byte_cnt Tx/Rx descriptor buffer byte count.
1195 * l4i_chk CPU provided TCP Checksum. For Tx operation only.
1196 * cmd_sts Tx/Rx descriptor command status.
1197 * buf_ptr Tx/Rx descriptor buffer pointer.
1198 * return_info Tx/Rx user resource return information.
1201 * EXTERNAL SUPPORT REQUIREMENTS
1203 * This driver requires the following external support:
1205 * D_CACHE_FLUSH_LINE (address, address offset)
1207 * This macro applies assembly code to flush and invalidate cache
1209 * address - address base.
1210 * address offset - address offset
1215 * This macro applies assembly code to flush the CPU pipeline.
1217 *******************************************************************************/
1221 /* SDMA command macros */
1222 #define ETH_ENABLE_TX_QUEUE(tx_queue, eth_port) \
1223 MV_REG_WRITE(MV64460_ETH_TRANSMIT_QUEUE_COMMAND_REG(eth_port), (1 << tx_queue))
1225 #define ETH_DISABLE_TX_QUEUE(tx_queue, eth_port) \
1226 MV_REG_WRITE(MV64460_ETH_TRANSMIT_QUEUE_COMMAND_REG(eth_port),\
1227 (1 << (8 + tx_queue)))
1229 #define ETH_ENABLE_RX_QUEUE(rx_queue, eth_port) \
1230 MV_REG_WRITE(MV64460_ETH_RECEIVE_QUEUE_COMMAND_REG(eth_port), (1 << rx_queue))
1232 #define ETH_DISABLE_RX_QUEUE(rx_queue, eth_port) \
1233 MV_REG_WRITE(MV64460_ETH_RECEIVE_QUEUE_COMMAND_REG(eth_port), (1 << (8 + rx_queue)))
1235 #define CURR_RFD_GET(p_curr_desc, queue) \
1236 ((p_curr_desc) = p_eth_port_ctrl->p_rx_curr_desc_q[queue])
1238 #define CURR_RFD_SET(p_curr_desc, queue) \
1239 (p_eth_port_ctrl->p_rx_curr_desc_q[queue] = (p_curr_desc))
1241 #define USED_RFD_GET(p_used_desc, queue) \
1242 ((p_used_desc) = p_eth_port_ctrl->p_rx_used_desc_q[queue])
1244 #define USED_RFD_SET(p_used_desc, queue)\
1245 (p_eth_port_ctrl->p_rx_used_desc_q[queue] = (p_used_desc))
1248 #define CURR_TFD_GET(p_curr_desc, queue) \
1249 ((p_curr_desc) = p_eth_port_ctrl->p_tx_curr_desc_q[queue])
1251 #define CURR_TFD_SET(p_curr_desc, queue) \
1252 (p_eth_port_ctrl->p_tx_curr_desc_q[queue] = (p_curr_desc))
1254 #define USED_TFD_GET(p_used_desc, queue) \
1255 ((p_used_desc) = p_eth_port_ctrl->p_tx_used_desc_q[queue])
1257 #define USED_TFD_SET(p_used_desc, queue) \
1258 (p_eth_port_ctrl->p_tx_used_desc_q[queue] = (p_used_desc))
1260 #define FIRST_TFD_GET(p_first_desc, queue) \
1261 ((p_first_desc) = p_eth_port_ctrl->p_tx_first_desc_q[queue])
1263 #define FIRST_TFD_SET(p_first_desc, queue) \
1264 (p_eth_port_ctrl->p_tx_first_desc_q[queue] = (p_first_desc))
1267 /* Macros that save access to desc in order to find next desc pointer */
1268 #define RX_NEXT_DESC_PTR(p_rx_desc, queue) (ETH_RX_DESC*)(((((unsigned int)p_rx_desc - (unsigned int)p_eth_port_ctrl->p_rx_desc_area_base[queue]) + RX_DESC_ALIGNED_SIZE) % p_eth_port_ctrl->rx_desc_area_size[queue]) + (unsigned int)p_eth_port_ctrl->p_rx_desc_area_base[queue])
1270 #define TX_NEXT_DESC_PTR(p_tx_desc, queue) (ETH_TX_DESC*)(((((unsigned int)p_tx_desc - (unsigned int)p_eth_port_ctrl->p_tx_desc_area_base[queue]) + TX_DESC_ALIGNED_SIZE) % p_eth_port_ctrl->tx_desc_area_size[queue]) + (unsigned int)p_eth_port_ctrl->p_tx_desc_area_base[queue])
1272 #define LINK_UP_TIMEOUT 100000
1273 #define PHY_BUSY_TIMEOUT 10000000
1278 static void ethernet_phy_set (ETH_PORT eth_port_num, int phy_addr);
1279 static int ethernet_phy_get (ETH_PORT eth_port_num);
1281 /* Ethernet Port routines */
1282 static void eth_set_access_control (ETH_PORT eth_port_num,
1283 ETH_WIN_PARAM * param);
1284 static bool eth_port_uc_addr (ETH_PORT eth_port_num, unsigned char uc_nibble,
1285 ETH_QUEUE queue, int option);
1287 static bool eth_port_smc_addr (ETH_PORT eth_port_num,
1288 unsigned char mc_byte,
1289 ETH_QUEUE queue, int option);
1290 static bool eth_port_omc_addr (ETH_PORT eth_port_num,
1292 ETH_QUEUE queue, int option);
1295 static void eth_b_copy (unsigned int src_addr, unsigned int dst_addr,
1298 void eth_dbg (ETH_PORT_INFO * p_eth_port_ctrl);
1301 typedef enum _memory_bank { BANK0, BANK1, BANK2, BANK3 } MEMORY_BANK;
1302 u32 mv_get_dram_bank_base_addr (MEMORY_BANK bank)
1305 u32 enable = MV_REG_READ (MV64460_BASE_ADDR_ENABLE);
1307 if (enable & (1 << bank))
1310 result = MV_REG_READ (MV64460_CS_0_BASE_ADDR);
1312 result = MV_REG_READ (MV64460_CS_1_BASE_ADDR);
1314 result = MV_REG_READ (MV64460_CS_2_BASE_ADDR);
1316 result = MV_REG_READ (MV64460_CS_3_BASE_ADDR);
1317 result &= 0x0000ffff;
1318 result = result << 16;
1322 u32 mv_get_dram_bank_size (MEMORY_BANK bank)
1325 u32 enable = MV_REG_READ (MV64460_BASE_ADDR_ENABLE);
1327 if (enable & (1 << bank))
1330 result = MV_REG_READ (MV64460_CS_0_SIZE);
1332 result = MV_REG_READ (MV64460_CS_1_SIZE);
1334 result = MV_REG_READ (MV64460_CS_2_SIZE);
1336 result = MV_REG_READ (MV64460_CS_3_SIZE);
1338 result &= 0x0000ffff;
1339 result = result << 16;
1343 u32 mv_get_internal_sram_base (void)
1347 result = MV_REG_READ (MV64460_INTEGRATED_SRAM_BASE_ADDR);
1348 result &= 0x0000ffff;
1349 result = result << 16;
1353 /*******************************************************************************
1354 * eth_port_init - Initialize the Ethernet port driver
1357 * This function prepares the ethernet port to start its activity:
1358 * 1) Completes the ethernet port driver struct initialization toward port
1360 * 2) Resets the device to a quiescent state in case of warm reboot.
1361 * 3) Enable SDMA access to all four DRAM banks as well as internal SRAM.
1362 * 4) Clean MAC tables. The reset status of those tables is unknown.
1363 * 5) Set PHY address.
1364 * Note: Call this routine prior to eth_port_start routine and after setting
1365 * user values in the user fields of Ethernet port control struct (i.e.
1369 * ETH_PORT_INFO *p_eth_port_ctrl Ethernet port control struct
1377 *******************************************************************************/
1378 static void eth_port_init (ETH_PORT_INFO * p_eth_port_ctrl)
1381 ETH_WIN_PARAM win_param;
1383 p_eth_port_ctrl->port_config = PORT_CONFIG_VALUE;
1384 p_eth_port_ctrl->port_config_extend = PORT_CONFIG_EXTEND_VALUE;
1385 p_eth_port_ctrl->port_sdma_config = PORT_SDMA_CONFIG_VALUE;
1386 p_eth_port_ctrl->port_serial_control = PORT_SERIAL_CONTROL_VALUE;
1388 p_eth_port_ctrl->port_rx_queue_command = 0;
1389 p_eth_port_ctrl->port_tx_queue_command = 0;
1391 /* Zero out SW structs */
1392 for (queue = 0; queue < MAX_RX_QUEUE_NUM; queue++) {
1393 CURR_RFD_SET ((ETH_RX_DESC *) 0x00000000, queue);
1394 USED_RFD_SET ((ETH_RX_DESC *) 0x00000000, queue);
1395 p_eth_port_ctrl->rx_resource_err[queue] = false;
1398 for (queue = 0; queue < MAX_TX_QUEUE_NUM; queue++) {
1399 CURR_TFD_SET ((ETH_TX_DESC *) 0x00000000, queue);
1400 USED_TFD_SET ((ETH_TX_DESC *) 0x00000000, queue);
1401 FIRST_TFD_SET ((ETH_TX_DESC *) 0x00000000, queue);
1402 p_eth_port_ctrl->tx_resource_err[queue] = false;
1405 eth_port_reset (p_eth_port_ctrl->port_num);
1407 /* Set access parameters for DRAM bank 0 */
1408 win_param.win = ETH_WIN0; /* Use Ethernet window 0 */
1409 win_param.target = ETH_TARGET_DRAM; /* Window target - DDR */
1410 win_param.attributes = EBAR_ATTR_DRAM_CS0; /* Enable DRAM bank */
1411 #ifndef CONFIG_NOT_COHERENT_CACHE
1412 win_param.attributes |= EBAR_ATTR_DRAM_CACHE_COHERENCY_WB;
1414 win_param.high_addr = 0;
1416 win_param.base_addr = mv_get_dram_bank_base_addr (BANK0);
1417 win_param.size = mv_get_dram_bank_size (BANK0); /* Get bank size */
1418 if (win_param.size == 0)
1419 win_param.enable = 0;
1421 win_param.enable = 1; /* Enable the access */
1422 win_param.access_ctrl = EWIN_ACCESS_FULL; /* Enable full access */
1424 /* Set the access control for address window (EPAPR) READ & WRITE */
1425 eth_set_access_control (p_eth_port_ctrl->port_num, &win_param);
1427 /* Set access parameters for DRAM bank 1 */
1428 win_param.win = ETH_WIN1; /* Use Ethernet window 1 */
1429 win_param.target = ETH_TARGET_DRAM; /* Window target - DDR */
1430 win_param.attributes = EBAR_ATTR_DRAM_CS1; /* Enable DRAM bank */
1431 #ifndef CONFIG_NOT_COHERENT_CACHE
1432 win_param.attributes |= EBAR_ATTR_DRAM_CACHE_COHERENCY_WB;
1434 win_param.high_addr = 0;
1436 win_param.base_addr = mv_get_dram_bank_base_addr (BANK1);
1437 win_param.size = mv_get_dram_bank_size (BANK1); /* Get bank size */
1438 if (win_param.size == 0)
1439 win_param.enable = 0;
1441 win_param.enable = 1; /* Enable the access */
1442 win_param.access_ctrl = EWIN_ACCESS_FULL; /* Enable full access */
1444 /* Set the access control for address window (EPAPR) READ & WRITE */
1445 eth_set_access_control (p_eth_port_ctrl->port_num, &win_param);
1447 /* Set access parameters for DRAM bank 2 */
1448 win_param.win = ETH_WIN2; /* Use Ethernet window 2 */
1449 win_param.target = ETH_TARGET_DRAM; /* Window target - DDR */
1450 win_param.attributes = EBAR_ATTR_DRAM_CS2; /* Enable DRAM bank */
1451 #ifndef CONFIG_NOT_COHERENT_CACHE
1452 win_param.attributes |= EBAR_ATTR_DRAM_CACHE_COHERENCY_WB;
1454 win_param.high_addr = 0;
1456 win_param.base_addr = mv_get_dram_bank_base_addr (BANK2);
1457 win_param.size = mv_get_dram_bank_size (BANK2); /* Get bank size */
1458 if (win_param.size == 0)
1459 win_param.enable = 0;
1461 win_param.enable = 1; /* Enable the access */
1462 win_param.access_ctrl = EWIN_ACCESS_FULL; /* Enable full access */
1464 /* Set the access control for address window (EPAPR) READ & WRITE */
1465 eth_set_access_control (p_eth_port_ctrl->port_num, &win_param);
1467 /* Set access parameters for DRAM bank 3 */
1468 win_param.win = ETH_WIN3; /* Use Ethernet window 3 */
1469 win_param.target = ETH_TARGET_DRAM; /* Window target - DDR */
1470 win_param.attributes = EBAR_ATTR_DRAM_CS3; /* Enable DRAM bank */
1471 #ifndef CONFIG_NOT_COHERENT_CACHE
1472 win_param.attributes |= EBAR_ATTR_DRAM_CACHE_COHERENCY_WB;
1474 win_param.high_addr = 0;
1476 win_param.base_addr = mv_get_dram_bank_base_addr (BANK3);
1477 win_param.size = mv_get_dram_bank_size (BANK3); /* Get bank size */
1478 if (win_param.size == 0)
1479 win_param.enable = 0;
1481 win_param.enable = 1; /* Enable the access */
1482 win_param.access_ctrl = EWIN_ACCESS_FULL; /* Enable full access */
1484 /* Set the access control for address window (EPAPR) READ & WRITE */
1485 eth_set_access_control (p_eth_port_ctrl->port_num, &win_param);
1487 /* Set access parameters for Internal SRAM */
1488 win_param.win = ETH_WIN4; /* Use Ethernet window 0 */
1489 win_param.target = EBAR_TARGET_CBS; /* Target - Internal SRAM */
1490 win_param.attributes = EBAR_ATTR_CBS_SRAM | EBAR_ATTR_CBS_SRAM_BLOCK0;
1491 win_param.high_addr = 0;
1492 win_param.base_addr = mv_get_internal_sram_base (); /* Get base addr */
1493 win_param.size = MV64460_INTERNAL_SRAM_SIZE; /* Get bank size */
1494 win_param.enable = 1; /* Enable the access */
1495 win_param.access_ctrl = EWIN_ACCESS_FULL; /* Enable full access */
1497 /* Set the access control for address window (EPAPR) READ & WRITE */
1498 eth_set_access_control (p_eth_port_ctrl->port_num, &win_param);
1500 eth_port_init_mac_tables (p_eth_port_ctrl->port_num);
1502 ethernet_phy_set (p_eth_port_ctrl->port_num,
1503 p_eth_port_ctrl->port_phy_addr);
1509 /*******************************************************************************
1510 * eth_port_start - Start the Ethernet port activity.
1513 * This routine prepares the Ethernet port for Rx and Tx activity:
1514 * 1. Initialize Tx and Rx Current Descriptor Pointer for each queue that
1515 * has been initialized a descriptor's ring (using ether_init_tx_desc_ring
1516 * for Tx and ether_init_rx_desc_ring for Rx)
1517 * 2. Initialize and enable the Ethernet configuration port by writing to
1518 * the port's configuration and command registers.
1519 * 3. Initialize and enable the SDMA by writing to the SDMA's
1520 * configuration and command registers.
1521 * After completing these steps, the ethernet port SDMA can starts to
1522 * perform Rx and Tx activities.
1524 * Note: Each Rx and Tx queue descriptor's list must be initialized prior
1525 * to calling this function (use ether_init_tx_desc_ring for Tx queues and
1526 * ether_init_rx_desc_ring for Rx queues).
1529 * ETH_PORT_INFO *p_eth_port_ctrl Ethernet port control struct
1532 * Ethernet port is ready to receive and transmit.
1535 * false if the port PHY is not up.
1538 *******************************************************************************/
1539 static bool eth_port_start (ETH_PORT_INFO * p_eth_port_ctrl)
1542 volatile ETH_TX_DESC *p_tx_curr_desc;
1543 volatile ETH_RX_DESC *p_rx_curr_desc;
1544 unsigned int phy_reg_data;
1545 ETH_PORT eth_port_num = p_eth_port_ctrl->port_num;
1548 /* Assignment of Tx CTRP of given queue */
1549 for (queue = 0; queue < MAX_TX_QUEUE_NUM; queue++) {
1550 CURR_TFD_GET (p_tx_curr_desc, queue);
1551 MV_REG_WRITE ((MV64460_ETH_TX_CURRENT_QUEUE_DESC_PTR_0
1554 ((unsigned int) p_tx_curr_desc));
1558 /* Assignment of Rx CRDP of given queue */
1559 for (queue = 0; queue < MAX_RX_QUEUE_NUM; queue++) {
1560 CURR_RFD_GET (p_rx_curr_desc, queue);
1561 MV_REG_WRITE ((MV64460_ETH_RX_CURRENT_QUEUE_DESC_PTR_0
1564 ((unsigned int) p_rx_curr_desc));
1566 if (p_rx_curr_desc != NULL)
1567 /* Add the assigned Ethernet address to the port's address table */
1568 eth_port_uc_addr_set (p_eth_port_ctrl->port_num,
1569 p_eth_port_ctrl->port_mac_addr,
1573 /* Assign port configuration and command. */
1574 MV_REG_WRITE (MV64460_ETH_PORT_CONFIG_REG (eth_port_num),
1575 p_eth_port_ctrl->port_config);
1577 MV_REG_WRITE (MV64460_ETH_PORT_CONFIG_EXTEND_REG (eth_port_num),
1578 p_eth_port_ctrl->port_config_extend);
1580 MV_REG_WRITE (MV64460_ETH_PORT_SERIAL_CONTROL_REG (eth_port_num),
1581 p_eth_port_ctrl->port_serial_control);
1583 MV_SET_REG_BITS (MV64460_ETH_PORT_SERIAL_CONTROL_REG (eth_port_num),
1584 ETH_SERIAL_PORT_ENABLE);
1586 /* Assign port SDMA configuration */
1587 MV_REG_WRITE (MV64460_ETH_SDMA_CONFIG_REG (eth_port_num),
1588 p_eth_port_ctrl->port_sdma_config);
1590 MV_REG_WRITE (MV64460_ETH_TX_QUEUE_0_TOKEN_BUCKET_COUNT
1591 (eth_port_num), 0x3fffffff);
1592 MV_REG_WRITE (MV64460_ETH_TX_QUEUE_0_TOKEN_BUCKET_CONFIG
1593 (eth_port_num), 0x03fffcff);
1594 /* Turn off the port/queue bandwidth limitation */
1595 MV_REG_WRITE (MV64460_ETH_MAXIMUM_TRANSMIT_UNIT (eth_port_num), 0x0);
1597 /* Enable port Rx. */
1598 MV_REG_WRITE (MV64460_ETH_RECEIVE_QUEUE_COMMAND_REG (eth_port_num),
1599 p_eth_port_ctrl->port_rx_queue_command);
1601 /* Check if link is up */
1602 eth_port_read_smi_reg (eth_port_num, 1, &phy_reg_data);
1604 if (!(phy_reg_data & 0x20))
1610 /*******************************************************************************
1611 * eth_port_uc_addr_set - This function Set the port Unicast address.
1614 * This function Set the port Ethernet MAC address.
1617 * ETH_PORT eth_port_num Port number.
1618 * char * p_addr Address to be set
1619 * ETH_QUEUE queue Rx queue number for this MAC address.
1622 * Set MAC address low and high registers. also calls eth_port_uc_addr()
1623 * To set the unicast table with the proper information.
1628 *******************************************************************************/
1629 static void eth_port_uc_addr_set (ETH_PORT eth_port_num,
1630 unsigned char *p_addr, ETH_QUEUE queue)
1635 mac_l = (p_addr[4] << 8) | (p_addr[5]);
1636 mac_h = (p_addr[0] << 24) | (p_addr[1] << 16) |
1637 (p_addr[2] << 8) | (p_addr[3] << 0);
1639 MV_REG_WRITE (MV64460_ETH_MAC_ADDR_LOW (eth_port_num), mac_l);
1640 MV_REG_WRITE (MV64460_ETH_MAC_ADDR_HIGH (eth_port_num), mac_h);
1642 /* Accept frames of this address */
1643 eth_port_uc_addr (eth_port_num, p_addr[5], queue, ACCEPT_MAC_ADDR);
1648 /*******************************************************************************
1649 * eth_port_uc_addr - This function Set the port unicast address table
1652 * This function locates the proper entry in the Unicast table for the
1653 * specified MAC nibble and sets its properties according to function
1657 * ETH_PORT eth_port_num Port number.
1658 * unsigned char uc_nibble Unicast MAC Address last nibble.
1659 * ETH_QUEUE queue Rx queue number for this MAC address.
1660 * int option 0 = Add, 1 = remove address.
1663 * This function add/removes MAC addresses from the port unicast address
1667 * true is output succeeded.
1668 * false if option parameter is invalid.
1670 *******************************************************************************/
1671 static bool eth_port_uc_addr (ETH_PORT eth_port_num,
1672 unsigned char uc_nibble,
1673 ETH_QUEUE queue, int option)
1675 unsigned int unicast_reg;
1676 unsigned int tbl_offset;
1677 unsigned int reg_offset;
1679 /* Locate the Unicast table entry */
1680 uc_nibble = (0xf & uc_nibble);
1681 tbl_offset = (uc_nibble / 4) * 4; /* Register offset from unicast table base */
1682 reg_offset = uc_nibble % 4; /* Entry offset within the above register */
1685 case REJECT_MAC_ADDR:
1686 /* Clear accepts frame bit at specified unicast DA table entry */
1688 MV_REG_READ ((MV64460_ETH_DA_FILTER_UNICAST_TABLE_BASE
1692 unicast_reg &= (0x0E << (8 * reg_offset));
1694 MV_REG_WRITE ((MV64460_ETH_DA_FILTER_UNICAST_TABLE_BASE
1696 + tbl_offset), unicast_reg);
1699 case ACCEPT_MAC_ADDR:
1700 /* Set accepts frame bit at unicast DA filter table entry */
1702 MV_REG_READ ((MV64460_ETH_DA_FILTER_UNICAST_TABLE_BASE
1706 unicast_reg |= ((0x01 | queue) << (8 * reg_offset));
1708 MV_REG_WRITE ((MV64460_ETH_DA_FILTER_UNICAST_TABLE_BASE
1710 + tbl_offset), unicast_reg);
1721 /*******************************************************************************
1722 * eth_port_mc_addr - Multicast address settings.
1725 * This API controls the MV device MAC multicast support.
1726 * The MV device supports multicast using two tables:
1727 * 1) Special Multicast Table for MAC addresses of the form
1728 * 0x01-00-5E-00-00-XX (where XX is between 0x00 and 0x_fF).
1729 * The MAC DA[7:0] bits are used as a pointer to the Special Multicast
1730 * Table entries in the DA-Filter table.
1731 * In this case, the function calls eth_port_smc_addr() routine to set the
1732 * Special Multicast Table.
1733 * 2) Other Multicast Table for multicast of another type. A CRC-8bit
1734 * is used as an index to the Other Multicast Table entries in the
1736 * In this case, the function calculates the CRC-8bit value and calls
1737 * eth_port_omc_addr() routine to set the Other Multicast Table.
1739 * ETH_PORT eth_port_num Port number.
1740 * unsigned char *p_addr Unicast MAC Address.
1741 * ETH_QUEUE queue Rx queue number for this MAC address.
1742 * int option 0 = Add, 1 = remove address.
1748 * true is output succeeded.
1749 * false if add_address_table_entry( ) failed.
1751 *******************************************************************************/
1752 static void eth_port_mc_addr (ETH_PORT eth_port_num,
1753 unsigned char *p_addr,
1754 ETH_QUEUE queue, int option)
1758 unsigned char crc_result = 0;
1764 if ((p_addr[0] == 0x01) &&
1765 (p_addr[1] == 0x00) &&
1766 (p_addr[2] == 0x5E) && (p_addr[3] == 0x00) && (p_addr[4] == 0x00))
1768 eth_port_smc_addr (eth_port_num, p_addr[5], queue, option);
1770 /* Calculate CRC-8 out of the given address */
1771 mac_h = (p_addr[0] << 8) | (p_addr[1]);
1772 mac_l = (p_addr[2] << 24) | (p_addr[3] << 16) |
1773 (p_addr[4] << 8) | (p_addr[5] << 0);
1775 for (i = 0; i < 32; i++)
1776 mac_array[i] = (mac_l >> i) & 0x1;
1777 for (i = 32; i < 48; i++)
1778 mac_array[i] = (mac_h >> (i - 32)) & 0x1;
1781 crc[0] = mac_array[45] ^ mac_array[43] ^ mac_array[40] ^
1782 mac_array[39] ^ mac_array[35] ^ mac_array[34] ^
1783 mac_array[31] ^ mac_array[30] ^ mac_array[28] ^
1784 mac_array[23] ^ mac_array[21] ^ mac_array[19] ^
1785 mac_array[18] ^ mac_array[16] ^ mac_array[14] ^
1786 mac_array[12] ^ mac_array[8] ^ mac_array[7] ^
1787 mac_array[6] ^ mac_array[0];
1789 crc[1] = mac_array[46] ^ mac_array[45] ^ mac_array[44] ^
1790 mac_array[43] ^ mac_array[41] ^ mac_array[39] ^
1791 mac_array[36] ^ mac_array[34] ^ mac_array[32] ^
1792 mac_array[30] ^ mac_array[29] ^ mac_array[28] ^
1793 mac_array[24] ^ mac_array[23] ^ mac_array[22] ^
1794 mac_array[21] ^ mac_array[20] ^ mac_array[18] ^
1795 mac_array[17] ^ mac_array[16] ^ mac_array[15] ^
1796 mac_array[14] ^ mac_array[13] ^ mac_array[12] ^
1797 mac_array[9] ^ mac_array[6] ^ mac_array[1] ^
1800 crc[2] = mac_array[47] ^ mac_array[46] ^ mac_array[44] ^
1801 mac_array[43] ^ mac_array[42] ^ mac_array[39] ^
1802 mac_array[37] ^ mac_array[34] ^ mac_array[33] ^
1803 mac_array[29] ^ mac_array[28] ^ mac_array[25] ^
1804 mac_array[24] ^ mac_array[22] ^ mac_array[17] ^
1805 mac_array[15] ^ mac_array[13] ^ mac_array[12] ^
1806 mac_array[10] ^ mac_array[8] ^ mac_array[6] ^
1807 mac_array[2] ^ mac_array[1] ^ mac_array[0];
1809 crc[3] = mac_array[47] ^ mac_array[45] ^ mac_array[44] ^
1810 mac_array[43] ^ mac_array[40] ^ mac_array[38] ^
1811 mac_array[35] ^ mac_array[34] ^ mac_array[30] ^
1812 mac_array[29] ^ mac_array[26] ^ mac_array[25] ^
1813 mac_array[23] ^ mac_array[18] ^ mac_array[16] ^
1814 mac_array[14] ^ mac_array[13] ^ mac_array[11] ^
1815 mac_array[9] ^ mac_array[7] ^ mac_array[3] ^
1816 mac_array[2] ^ mac_array[1];
1818 crc[4] = mac_array[46] ^ mac_array[45] ^ mac_array[44] ^
1819 mac_array[41] ^ mac_array[39] ^ mac_array[36] ^
1820 mac_array[35] ^ mac_array[31] ^ mac_array[30] ^
1821 mac_array[27] ^ mac_array[26] ^ mac_array[24] ^
1822 mac_array[19] ^ mac_array[17] ^ mac_array[15] ^
1823 mac_array[14] ^ mac_array[12] ^ mac_array[10] ^
1824 mac_array[8] ^ mac_array[4] ^ mac_array[3] ^
1827 crc[5] = mac_array[47] ^ mac_array[46] ^ mac_array[45] ^
1828 mac_array[42] ^ mac_array[40] ^ mac_array[37] ^
1829 mac_array[36] ^ mac_array[32] ^ mac_array[31] ^
1830 mac_array[28] ^ mac_array[27] ^ mac_array[25] ^
1831 mac_array[20] ^ mac_array[18] ^ mac_array[16] ^
1832 mac_array[15] ^ mac_array[13] ^ mac_array[11] ^
1833 mac_array[9] ^ mac_array[5] ^ mac_array[4] ^
1836 crc[6] = mac_array[47] ^ mac_array[46] ^ mac_array[43] ^
1837 mac_array[41] ^ mac_array[38] ^ mac_array[37] ^
1838 mac_array[33] ^ mac_array[32] ^ mac_array[29] ^
1839 mac_array[28] ^ mac_array[26] ^ mac_array[21] ^
1840 mac_array[19] ^ mac_array[17] ^ mac_array[16] ^
1841 mac_array[14] ^ mac_array[12] ^ mac_array[10] ^
1842 mac_array[6] ^ mac_array[5] ^ mac_array[4];
1844 crc[7] = mac_array[47] ^ mac_array[44] ^ mac_array[42] ^
1845 mac_array[39] ^ mac_array[38] ^ mac_array[34] ^
1846 mac_array[33] ^ mac_array[30] ^ mac_array[29] ^
1847 mac_array[27] ^ mac_array[22] ^ mac_array[20] ^
1848 mac_array[18] ^ mac_array[17] ^ mac_array[15] ^
1849 mac_array[13] ^ mac_array[11] ^ mac_array[7] ^
1850 mac_array[6] ^ mac_array[5];
1852 for (i = 0; i < 8; i++)
1853 crc_result = crc_result | (crc[i] << i);
1855 eth_port_omc_addr (eth_port_num, crc_result, queue, option);
1860 /*******************************************************************************
1861 * eth_port_smc_addr - Special Multicast address settings.
1864 * This routine controls the MV device special MAC multicast support.
1865 * The Special Multicast Table for MAC addresses supports MAC of the form
1866 * 0x01-00-5E-00-00-XX (where XX is between 0x00 and 0x_fF).
1867 * The MAC DA[7:0] bits are used as a pointer to the Special Multicast
1868 * Table entries in the DA-Filter table.
1869 * This function set the Special Multicast Table appropriate entry
1870 * according to the argument given.
1873 * ETH_PORT eth_port_num Port number.
1874 * unsigned char mc_byte Multicast addr last byte (MAC DA[7:0] bits).
1875 * ETH_QUEUE queue Rx queue number for this MAC address.
1876 * int option 0 = Add, 1 = remove address.
1882 * true is output succeeded.
1883 * false if option parameter is invalid.
1885 *******************************************************************************/
1886 static bool eth_port_smc_addr (ETH_PORT eth_port_num,
1887 unsigned char mc_byte,
1888 ETH_QUEUE queue, int option)
1890 unsigned int smc_table_reg;
1891 unsigned int tbl_offset;
1892 unsigned int reg_offset;
1894 /* Locate the SMC table entry */
1895 tbl_offset = (mc_byte / 4) * 4; /* Register offset from SMC table base */
1896 reg_offset = mc_byte % 4; /* Entry offset within the above register */
1900 case REJECT_MAC_ADDR:
1901 /* Clear accepts frame bit at specified Special DA table entry */
1903 MV_REG_READ ((MV64460_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset));
1904 smc_table_reg &= (0x0E << (8 * reg_offset));
1906 MV_REG_WRITE ((MV64460_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset), smc_table_reg);
1909 case ACCEPT_MAC_ADDR:
1910 /* Set accepts frame bit at specified Special DA table entry */
1912 MV_REG_READ ((MV64460_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset));
1913 smc_table_reg |= ((0x01 | queue) << (8 * reg_offset));
1915 MV_REG_WRITE ((MV64460_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset), smc_table_reg);
1924 /*******************************************************************************
1925 * eth_port_omc_addr - Multicast address settings.
1928 * This routine controls the MV device Other MAC multicast support.
1929 * The Other Multicast Table is used for multicast of another type.
1930 * A CRC-8bit is used as an index to the Other Multicast Table entries
1931 * in the DA-Filter table.
1932 * The function gets the CRC-8bit value from the calling routine and
1933 * set the Other Multicast Table appropriate entry according to the
1934 * CRC-8 argument given.
1937 * ETH_PORT eth_port_num Port number.
1938 * unsigned char crc8 A CRC-8bit (Polynomial: x^8+x^2+x^1+1).
1939 * ETH_QUEUE queue Rx queue number for this MAC address.
1940 * int option 0 = Add, 1 = remove address.
1946 * true is output succeeded.
1947 * false if option parameter is invalid.
1949 *******************************************************************************/
1950 static bool eth_port_omc_addr (ETH_PORT eth_port_num,
1952 ETH_QUEUE queue, int option)
1954 unsigned int omc_table_reg;
1955 unsigned int tbl_offset;
1956 unsigned int reg_offset;
1958 /* Locate the OMC table entry */
1959 tbl_offset = (crc8 / 4) * 4; /* Register offset from OMC table base */
1960 reg_offset = crc8 % 4; /* Entry offset within the above register */
1964 case REJECT_MAC_ADDR:
1965 /* Clear accepts frame bit at specified Other DA table entry */
1967 MV_REG_READ ((MV64460_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset));
1968 omc_table_reg &= (0x0E << (8 * reg_offset));
1970 MV_REG_WRITE ((MV64460_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset), omc_table_reg);
1973 case ACCEPT_MAC_ADDR:
1974 /* Set accepts frame bit at specified Other DA table entry */
1976 MV_REG_READ ((MV64460_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset));
1977 omc_table_reg |= ((0x01 | queue) << (8 * reg_offset));
1979 MV_REG_WRITE ((MV64460_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset), omc_table_reg);
1989 /*******************************************************************************
1990 * eth_port_init_mac_tables - Clear all entrance in the UC, SMC and OMC tables
1993 * Go through all the DA filter tables (Unicast, Special Multicast & Other
1994 * Multicast) and set each entry to 0.
1997 * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum.
2000 * Multicast and Unicast packets are rejected.
2005 *******************************************************************************/
2006 static void eth_port_init_mac_tables (ETH_PORT eth_port_num)
2010 /* Clear DA filter unicast table (Ex_dFUT) */
2011 for (table_index = 0; table_index <= 0xC; table_index += 4)
2012 MV_REG_WRITE ((MV64460_ETH_DA_FILTER_UNICAST_TABLE_BASE
2013 (eth_port_num) + table_index), 0);
2015 for (table_index = 0; table_index <= 0xFC; table_index += 4) {
2016 /* Clear DA filter special multicast table (Ex_dFSMT) */
2017 MV_REG_WRITE ((MV64460_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE (eth_port_num) + table_index), 0);
2018 /* Clear DA filter other multicast table (Ex_dFOMT) */
2019 MV_REG_WRITE ((MV64460_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE (eth_port_num) + table_index), 0);
2023 /*******************************************************************************
2024 * eth_clear_mib_counters - Clear all MIB counters
2027 * This function clears all MIB counters of a specific ethernet port.
2028 * A read from the MIB counter will reset the counter.
2031 * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum.
2034 * After reading all MIB counters, the counters resets.
2037 * MIB counter value.
2039 *******************************************************************************/
2040 static void eth_clear_mib_counters (ETH_PORT eth_port_num)
2044 /* Perform dummy reads from MIB counters */
2045 for (i = ETH_MIB_GOOD_OCTETS_RECEIVED_LOW; i < ETH_MIB_LATE_COLLISION;
2047 MV_REG_READ((MV64460_ETH_MIB_COUNTERS_BASE(eth_port_num) + i));
2052 /*******************************************************************************
2053 * eth_read_mib_counter - Read a MIB counter
2056 * This function reads a MIB counter of a specific ethernet port.
2057 * NOTE - If read from ETH_MIB_GOOD_OCTETS_RECEIVED_LOW, then the
2058 * following read must be from ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH
2059 * register. The same applies for ETH_MIB_GOOD_OCTETS_SENT_LOW and
2060 * ETH_MIB_GOOD_OCTETS_SENT_HIGH
2063 * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum.
2064 * unsigned int mib_offset MIB counter offset (use ETH_MIB_... macros).
2067 * After reading the MIB counter, the counter resets.
2070 * MIB counter value.
2072 *******************************************************************************/
2073 unsigned int eth_read_mib_counter (ETH_PORT eth_port_num,
2074 unsigned int mib_offset)
2076 return (MV_REG_READ (MV64460_ETH_MIB_COUNTERS_BASE (eth_port_num)
2080 /*******************************************************************************
2081 * ethernet_phy_set - Set the ethernet port PHY address.
2084 * This routine set the ethernet port PHY address according to given
2088 * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum.
2091 * Set PHY Address Register with given PHY address parameter.
2096 *******************************************************************************/
2097 static void ethernet_phy_set (ETH_PORT eth_port_num, int phy_addr)
2099 unsigned int reg_data;
2101 reg_data = MV_REG_READ (MV64460_ETH_PHY_ADDR_REG);
2103 reg_data &= ~(0x1F << (5 * eth_port_num));
2104 reg_data |= (phy_addr << (5 * eth_port_num));
2106 MV_REG_WRITE (MV64460_ETH_PHY_ADDR_REG, reg_data);
2111 /*******************************************************************************
2112 * ethernet_phy_get - Get the ethernet port PHY address.
2115 * This routine returns the given ethernet port PHY address.
2118 * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum.
2126 *******************************************************************************/
2127 static int ethernet_phy_get (ETH_PORT eth_port_num)
2129 unsigned int reg_data;
2131 reg_data = MV_REG_READ (MV64460_ETH_PHY_ADDR_REG);
2133 return ((reg_data >> (5 * eth_port_num)) & 0x1f);
2136 /*******************************************************************************
2137 * ethernet_phy_reset - Reset Ethernet port PHY.
2140 * This routine utilize the SMI interface to reset the ethernet port PHY.
2141 * The routine waits until the link is up again or link up is timeout.
2144 * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum.
2147 * The ethernet port PHY renew its link.
2152 *******************************************************************************/
2153 static bool ethernet_phy_reset (ETH_PORT eth_port_num)
2155 unsigned int time_out = 50;
2156 unsigned int phy_reg_data;
2159 eth_port_read_smi_reg (eth_port_num, 0, &phy_reg_data);
2160 phy_reg_data |= 0x8000; /* Set bit 15 to reset the PHY */
2161 eth_port_write_smi_reg (eth_port_num, 0, phy_reg_data);
2163 /* Poll on the PHY LINK */
2165 eth_port_read_smi_reg (eth_port_num, 1, &phy_reg_data);
2167 if (time_out-- == 0)
2170 while (!(phy_reg_data & 0x20));
2175 /*******************************************************************************
2176 * eth_port_reset - Reset Ethernet port
2179 * This routine resets the chip by aborting any SDMA engine activity and
2180 * clearing the MIB counters. The Receiver and the Transmit unit are in
2181 * idle state after this command is performed and the port is disabled.
2184 * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum.
2187 * Channel activity is halted.
2192 *******************************************************************************/
2193 static void eth_port_reset (ETH_PORT eth_port_num)
2195 unsigned int reg_data;
2197 /* Stop Tx port activity. Check port Tx activity. */
2199 MV_REG_READ (MV64460_ETH_TRANSMIT_QUEUE_COMMAND_REG
2202 if (reg_data & 0xFF) {
2203 /* Issue stop command for active channels only */
2204 MV_REG_WRITE (MV64460_ETH_TRANSMIT_QUEUE_COMMAND_REG
2205 (eth_port_num), (reg_data << 8));
2207 /* Wait for all Tx activity to terminate. */
2209 /* Check port cause register that all Tx queues are stopped */
2212 (MV64460_ETH_TRANSMIT_QUEUE_COMMAND_REG
2215 while (reg_data & 0xFF);
2218 /* Stop Rx port activity. Check port Rx activity. */
2220 MV_REG_READ (MV64460_ETH_RECEIVE_QUEUE_COMMAND_REG
2223 if (reg_data & 0xFF) {
2224 /* Issue stop command for active channels only */
2225 MV_REG_WRITE (MV64460_ETH_RECEIVE_QUEUE_COMMAND_REG
2226 (eth_port_num), (reg_data << 8));
2228 /* Wait for all Rx activity to terminate. */
2230 /* Check port cause register that all Rx queues are stopped */
2233 (MV64460_ETH_RECEIVE_QUEUE_COMMAND_REG
2236 while (reg_data & 0xFF);
2240 /* Clear all MIB counters */
2241 eth_clear_mib_counters (eth_port_num);
2243 /* Reset the Enable bit in the Configuration Register */
2245 MV_REG_READ (MV64460_ETH_PORT_SERIAL_CONTROL_REG
2247 reg_data &= ~ETH_SERIAL_PORT_ENABLE;
2248 MV_REG_WRITE (MV64460_ETH_PORT_SERIAL_CONTROL_REG (eth_port_num),
2254 #if 0 /* Not needed here */
2255 /*******************************************************************************
2256 * ethernet_set_config_reg - Set specified bits in configuration register.
2259 * This function sets specified bits in the given ethernet
2260 * configuration register.
2263 * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum.
2264 * unsigned int value 32 bit value.
2267 * The set bits in the value parameter are set in the configuration
2273 *******************************************************************************/
2274 static void ethernet_set_config_reg (ETH_PORT eth_port_num,
2277 unsigned int eth_config_reg;
2280 MV_REG_READ (MV64460_ETH_PORT_CONFIG_REG (eth_port_num));
2281 eth_config_reg |= value;
2282 MV_REG_WRITE (MV64460_ETH_PORT_CONFIG_REG (eth_port_num),
2290 /*******************************************************************************
2291 * ethernet_reset_config_reg - Reset specified bits in configuration register.
2294 * This function resets specified bits in the given Ethernet
2295 * configuration register.
2298 * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum.
2299 * unsigned int value 32 bit value.
2302 * The set bits in the value parameter are reset in the configuration
2308 *******************************************************************************/
2309 static void ethernet_reset_config_reg (ETH_PORT eth_port_num,
2312 unsigned int eth_config_reg;
2314 eth_config_reg = MV_REG_READ (MV64460_ETH_PORT_CONFIG_EXTEND_REG
2316 eth_config_reg &= ~value;
2317 MV_REG_WRITE (MV64460_ETH_PORT_CONFIG_EXTEND_REG (eth_port_num),
2324 #if 0 /* Not needed here */
2325 /*******************************************************************************
2326 * ethernet_get_config_reg - Get the port configuration register
2329 * This function returns the configuration register value of the given
2333 * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum.
2339 * Port configuration register value.
2341 *******************************************************************************/
2342 static unsigned int ethernet_get_config_reg (ETH_PORT eth_port_num)
2344 unsigned int eth_config_reg;
2346 eth_config_reg = MV_REG_READ (MV64460_ETH_PORT_CONFIG_EXTEND_REG
2348 return eth_config_reg;
2353 /*******************************************************************************
2354 * eth_port_read_smi_reg - Read PHY registers
2357 * This routine utilize the SMI interface to interact with the PHY in
2358 * order to perform PHY register read.
2361 * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum.
2362 * unsigned int phy_reg PHY register address offset.
2363 * unsigned int *value Register value buffer.
2366 * Write the value of a specified PHY register into given buffer.
2369 * false if the PHY is busy or read data is not in valid state.
2372 *******************************************************************************/
2373 static bool eth_port_read_smi_reg (ETH_PORT eth_port_num,
2374 unsigned int phy_reg, unsigned int *value)
2376 unsigned int reg_value;
2377 unsigned int time_out = PHY_BUSY_TIMEOUT;
2380 phy_addr = ethernet_phy_get (eth_port_num);
2381 /* printf(" Phy-Port %d has addess %d \n",eth_port_num, phy_addr );*/
2383 /* first check that it is not busy */
2385 reg_value = MV_REG_READ (MV64460_ETH_SMI_REG);
2386 if (time_out-- == 0) {
2390 while (reg_value & ETH_SMI_BUSY);
2394 MV_REG_WRITE (MV64460_ETH_SMI_REG,
2395 (phy_addr << 16) | (phy_reg << 21) |
2396 ETH_SMI_OPCODE_READ);
2398 time_out = PHY_BUSY_TIMEOUT; /* initialize the time out var again */
2401 reg_value = MV_REG_READ (MV64460_ETH_SMI_REG);
2402 if (time_out-- == 0) {
2406 while ((reg_value & ETH_SMI_READ_VALID) != ETH_SMI_READ_VALID); /* Bit set equ operation done */
2408 /* Wait for the data to update in the SMI register */
2409 #define PHY_UPDATE_TIMEOUT 10000
2410 for (time_out = 0; time_out < PHY_UPDATE_TIMEOUT; time_out++);
2412 reg_value = MV_REG_READ (MV64460_ETH_SMI_REG);
2414 *value = reg_value & 0xffff;
2419 /*******************************************************************************
2420 * eth_port_write_smi_reg - Write to PHY registers
2423 * This routine utilize the SMI interface to interact with the PHY in
2424 * order to perform writes to PHY registers.
2427 * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum.
2428 * unsigned int phy_reg PHY register address offset.
2429 * unsigned int value Register value.
2432 * Write the given value to the specified PHY register.
2435 * false if the PHY is busy.
2438 *******************************************************************************/
2439 static bool eth_port_write_smi_reg (ETH_PORT eth_port_num,
2440 unsigned int phy_reg, unsigned int value)
2442 unsigned int reg_value;
2443 unsigned int time_out = PHY_BUSY_TIMEOUT;
2446 phy_addr = ethernet_phy_get (eth_port_num);
2448 /* first check that it is not busy */
2450 reg_value = MV_REG_READ (MV64460_ETH_SMI_REG);
2451 if (time_out-- == 0) {
2455 while (reg_value & ETH_SMI_BUSY);
2458 MV_REG_WRITE (MV64460_ETH_SMI_REG,
2459 (phy_addr << 16) | (phy_reg << 21) |
2460 ETH_SMI_OPCODE_WRITE | (value & 0xffff));
2464 /*******************************************************************************
2465 * eth_set_access_control - Config address decode parameters for Ethernet unit
2468 * This function configures the address decode parameters for the Gigabit
2469 * Ethernet Controller according the given parameters struct.
2472 * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum.
2473 * ETH_WIN_PARAM *param Address decode parameter struct.
2476 * An access window is opened using the given access parameters.
2481 *******************************************************************************/
2482 static void eth_set_access_control (ETH_PORT eth_port_num,
2483 ETH_WIN_PARAM * param)
2485 unsigned int access_prot_reg;
2487 /* Set access control register */
2488 access_prot_reg = MV_REG_READ (MV64460_ETH_ACCESS_PROTECTION_REG
2490 access_prot_reg &= (~(3 << (param->win * 2))); /* clear window permission */
2491 access_prot_reg |= (param->access_ctrl << (param->win * 2));
2492 MV_REG_WRITE (MV64460_ETH_ACCESS_PROTECTION_REG (eth_port_num),
2495 /* Set window Size reg (SR) */
2496 MV_REG_WRITE ((MV64460_ETH_SIZE_REG_0 +
2497 (ETH_SIZE_REG_GAP * param->win)),
2498 (((param->size / 0x10000) - 1) << 16));
2500 /* Set window Base address reg (BA) */
2501 MV_REG_WRITE ((MV64460_ETH_BAR_0 + (ETH_BAR_GAP * param->win)),
2502 (param->target | param->attributes | param->base_addr));
2503 /* High address remap reg (HARR) */
2505 MV_REG_WRITE ((MV64460_ETH_HIGH_ADDR_REMAP_REG_0 +
2506 (ETH_HIGH_ADDR_REMAP_REG_GAP * param->win)),
2509 /* Base address enable reg (BARER) */
2510 if (param->enable == 1)
2511 MV_RESET_REG_BITS (MV64460_ETH_BASE_ADDR_ENABLE_REG,
2514 MV_SET_REG_BITS (MV64460_ETH_BASE_ADDR_ENABLE_REG,
2518 /*******************************************************************************
2519 * ether_init_rx_desc_ring - Curve a Rx chain desc list and buffer in memory.
2522 * This function prepares a Rx chained list of descriptors and packet
2523 * buffers in a form of a ring. The routine must be called after port
2524 * initialization routine and before port start routine.
2525 * The Ethernet SDMA engine uses CPU bus addresses to access the various
2526 * devices in the system (i.e. DRAM). This function uses the ethernet
2527 * struct 'virtual to physical' routine (set by the user) to set the ring
2528 * with physical addresses.
2531 * ETH_PORT_INFO *p_eth_port_ctrl Ethernet Port Control srtuct.
2532 * ETH_QUEUE rx_queue Number of Rx queue.
2533 * int rx_desc_num Number of Rx descriptors
2534 * int rx_buff_size Size of Rx buffer
2535 * unsigned int rx_desc_base_addr Rx descriptors memory area base addr.
2536 * unsigned int rx_buff_base_addr Rx buffer memory area base addr.
2539 * The routine updates the Ethernet port control struct with information
2540 * regarding the Rx descriptors and buffers.
2543 * false if the given descriptors memory area is not aligned according to
2544 * Ethernet SDMA specifications.
2547 *******************************************************************************/
2548 static bool ether_init_rx_desc_ring (ETH_PORT_INFO * p_eth_port_ctrl,
2552 unsigned int rx_desc_base_addr,
2553 unsigned int rx_buff_base_addr)
2555 ETH_RX_DESC *p_rx_desc;
2556 ETH_RX_DESC *p_rx_prev_desc; /* pointer to link with the last descriptor */
2557 unsigned int buffer_addr;
2558 int ix; /* a counter */
2561 p_rx_desc = (ETH_RX_DESC *) rx_desc_base_addr;
2562 p_rx_prev_desc = p_rx_desc;
2563 buffer_addr = rx_buff_base_addr;
2565 /* Rx desc Must be 4LW aligned (i.e. Descriptor_Address[3:0]=0000). */
2566 if (rx_buff_base_addr & 0xF)
2569 /* Rx buffers are limited to 64K bytes and Minimum size is 8 bytes */
2570 if ((rx_buff_size < 8) || (rx_buff_size > RX_BUFFER_MAX_SIZE))
2573 /* Rx buffers must be 64-bit aligned. */
2574 if ((rx_buff_base_addr + rx_buff_size) & 0x7)
2577 /* initialize the Rx descriptors ring */
2578 for (ix = 0; ix < rx_desc_num; ix++) {
2579 p_rx_desc->buf_size = rx_buff_size;
2580 p_rx_desc->byte_cnt = 0x0000;
2581 p_rx_desc->cmd_sts =
2582 ETH_BUFFER_OWNED_BY_DMA | ETH_RX_ENABLE_INTERRUPT;
2583 p_rx_desc->next_desc_ptr =
2584 ((unsigned int) p_rx_desc) + RX_DESC_ALIGNED_SIZE;
2585 p_rx_desc->buf_ptr = buffer_addr;
2586 p_rx_desc->return_info = 0x00000000;
2587 D_CACHE_FLUSH_LINE (p_rx_desc, 0);
2588 buffer_addr += rx_buff_size;
2589 p_rx_prev_desc = p_rx_desc;
2590 p_rx_desc = (ETH_RX_DESC *)
2591 ((unsigned int) p_rx_desc + RX_DESC_ALIGNED_SIZE);
2594 /* Closing Rx descriptors ring */
2595 p_rx_prev_desc->next_desc_ptr = (rx_desc_base_addr);
2596 D_CACHE_FLUSH_LINE (p_rx_prev_desc, 0);
2598 /* Save Rx desc pointer to driver struct. */
2599 CURR_RFD_SET ((ETH_RX_DESC *) rx_desc_base_addr, rx_queue);
2600 USED_RFD_SET ((ETH_RX_DESC *) rx_desc_base_addr, rx_queue);
2602 p_eth_port_ctrl->p_rx_desc_area_base[rx_queue] =
2603 (ETH_RX_DESC *) rx_desc_base_addr;
2604 p_eth_port_ctrl->rx_desc_area_size[rx_queue] =
2605 rx_desc_num * RX_DESC_ALIGNED_SIZE;
2607 p_eth_port_ctrl->port_rx_queue_command |= (1 << rx_queue);
2612 /*******************************************************************************
2613 * ether_init_tx_desc_ring - Curve a Tx chain desc list and buffer in memory.
2616 * This function prepares a Tx chained list of descriptors and packet
2617 * buffers in a form of a ring. The routine must be called after port
2618 * initialization routine and before port start routine.
2619 * The Ethernet SDMA engine uses CPU bus addresses to access the various
2620 * devices in the system (i.e. DRAM). This function uses the ethernet
2621 * struct 'virtual to physical' routine (set by the user) to set the ring
2622 * with physical addresses.
2625 * ETH_PORT_INFO *p_eth_port_ctrl Ethernet Port Control srtuct.
2626 * ETH_QUEUE tx_queue Number of Tx queue.
2627 * int tx_desc_num Number of Tx descriptors
2628 * int tx_buff_size Size of Tx buffer
2629 * unsigned int tx_desc_base_addr Tx descriptors memory area base addr.
2630 * unsigned int tx_buff_base_addr Tx buffer memory area base addr.
2633 * The routine updates the Ethernet port control struct with information
2634 * regarding the Tx descriptors and buffers.
2637 * false if the given descriptors memory area is not aligned according to
2638 * Ethernet SDMA specifications.
2641 *******************************************************************************/
2642 static bool ether_init_tx_desc_ring (ETH_PORT_INFO * p_eth_port_ctrl,
2646 unsigned int tx_desc_base_addr,
2647 unsigned int tx_buff_base_addr)
2650 ETH_TX_DESC *p_tx_desc;
2651 ETH_TX_DESC *p_tx_prev_desc;
2652 unsigned int buffer_addr;
2653 int ix; /* a counter */
2656 /* save the first desc pointer to link with the last descriptor */
2657 p_tx_desc = (ETH_TX_DESC *) tx_desc_base_addr;
2658 p_tx_prev_desc = p_tx_desc;
2659 buffer_addr = tx_buff_base_addr;
2661 /* Tx desc Must be 4LW aligned (i.e. Descriptor_Address[3:0]=0000). */
2662 if (tx_buff_base_addr & 0xF)
2665 /* Tx buffers are limited to 64K bytes and Minimum size is 8 bytes */
2666 if ((tx_buff_size > TX_BUFFER_MAX_SIZE)
2667 || (tx_buff_size < TX_BUFFER_MIN_SIZE))
2670 /* Initialize the Tx descriptors ring */
2671 for (ix = 0; ix < tx_desc_num; ix++) {
2672 p_tx_desc->byte_cnt = 0x0000;
2673 p_tx_desc->l4i_chk = 0x0000;
2674 p_tx_desc->cmd_sts = 0x00000000;
2675 p_tx_desc->next_desc_ptr =
2676 ((unsigned int) p_tx_desc) + TX_DESC_ALIGNED_SIZE;
2678 p_tx_desc->buf_ptr = buffer_addr;
2679 p_tx_desc->return_info = 0x00000000;
2680 D_CACHE_FLUSH_LINE (p_tx_desc, 0);
2681 buffer_addr += tx_buff_size;
2682 p_tx_prev_desc = p_tx_desc;
2683 p_tx_desc = (ETH_TX_DESC *)
2684 ((unsigned int) p_tx_desc + TX_DESC_ALIGNED_SIZE);
2687 /* Closing Tx descriptors ring */
2688 p_tx_prev_desc->next_desc_ptr = tx_desc_base_addr;
2689 D_CACHE_FLUSH_LINE (p_tx_prev_desc, 0);
2690 /* Set Tx desc pointer in driver struct. */
2691 CURR_TFD_SET ((ETH_TX_DESC *) tx_desc_base_addr, tx_queue);
2692 USED_TFD_SET ((ETH_TX_DESC *) tx_desc_base_addr, tx_queue);
2694 /* Init Tx ring base and size parameters */
2695 p_eth_port_ctrl->p_tx_desc_area_base[tx_queue] =
2696 (ETH_TX_DESC *) tx_desc_base_addr;
2697 p_eth_port_ctrl->tx_desc_area_size[tx_queue] =
2698 (tx_desc_num * TX_DESC_ALIGNED_SIZE);
2700 /* Add the queue to the list of Tx queues of this port */
2701 p_eth_port_ctrl->port_tx_queue_command |= (1 << tx_queue);
2706 /*******************************************************************************
2707 * eth_port_send - Send an Ethernet packet
2710 * This routine send a given packet described by p_pktinfo parameter. It
2711 * supports transmitting of a packet spaned over multiple buffers. The
2712 * routine updates 'curr' and 'first' indexes according to the packet
2713 * segment passed to the routine. In case the packet segment is first,
2714 * the 'first' index is update. In any case, the 'curr' index is updated.
2715 * If the routine get into Tx resource error it assigns 'curr' index as
2716 * 'first'. This way the function can abort Tx process of multiple
2717 * descriptors per packet.
2720 * ETH_PORT_INFO *p_eth_port_ctrl Ethernet Port Control srtuct.
2721 * ETH_QUEUE tx_queue Number of Tx queue.
2722 * PKT_INFO *p_pkt_info User packet buffer.
2725 * Tx ring 'curr' and 'first' indexes are updated.
2728 * ETH_QUEUE_FULL in case of Tx resource error.
2729 * ETH_ERROR in case the routine can not access Tx desc ring.
2730 * ETH_QUEUE_LAST_RESOURCE if the routine uses the last Tx resource.
2733 *******************************************************************************/
2734 static ETH_FUNC_RET_STATUS eth_port_send (ETH_PORT_INFO * p_eth_port_ctrl,
2736 PKT_INFO * p_pkt_info)
2738 volatile ETH_TX_DESC *p_tx_desc_first;
2739 volatile ETH_TX_DESC *p_tx_desc_curr;
2740 volatile ETH_TX_DESC *p_tx_next_desc_curr;
2741 volatile ETH_TX_DESC *p_tx_desc_used;
2742 unsigned int command_status;
2744 /* Do not process Tx ring in case of Tx ring resource error */
2745 if (p_eth_port_ctrl->tx_resource_err[tx_queue] == true)
2746 return ETH_QUEUE_FULL;
2748 /* Get the Tx Desc ring indexes */
2749 CURR_TFD_GET (p_tx_desc_curr, tx_queue);
2750 USED_TFD_GET (p_tx_desc_used, tx_queue);
2752 if (p_tx_desc_curr == NULL)
2755 /* The following parameters are used to save readings from memory */
2756 p_tx_next_desc_curr = TX_NEXT_DESC_PTR (p_tx_desc_curr, tx_queue);
2757 command_status = p_pkt_info->cmd_sts | ETH_ZERO_PADDING | ETH_GEN_CRC;
2759 if (command_status & (ETH_TX_FIRST_DESC)) {
2760 /* Update first desc */
2761 FIRST_TFD_SET (p_tx_desc_curr, tx_queue);
2762 p_tx_desc_first = p_tx_desc_curr;
2764 FIRST_TFD_GET (p_tx_desc_first, tx_queue);
2765 command_status |= ETH_BUFFER_OWNED_BY_DMA;
2768 /* Buffers with a payload smaller than 8 bytes must be aligned to 64-bit */
2769 /* boundary. We use the memory allocated for Tx descriptor. This memory */
2770 /* located in TX_BUF_OFFSET_IN_DESC offset within the Tx descriptor. */
2771 if (p_pkt_info->byte_cnt <= 8) {
2772 printf ("You have failed in the < 8 bytes errata - fixme\n"); /* RABEEH - TBD */
2775 p_tx_desc_curr->buf_ptr =
2776 (unsigned int) p_tx_desc_curr + TX_BUF_OFFSET_IN_DESC;
2777 eth_b_copy (p_pkt_info->buf_ptr, p_tx_desc_curr->buf_ptr,
2778 p_pkt_info->byte_cnt);
2780 p_tx_desc_curr->buf_ptr = p_pkt_info->buf_ptr;
2782 p_tx_desc_curr->byte_cnt = p_pkt_info->byte_cnt;
2783 p_tx_desc_curr->return_info = p_pkt_info->return_info;
2785 if (p_pkt_info->cmd_sts & (ETH_TX_LAST_DESC)) {
2786 /* Set last desc with DMA ownership and interrupt enable. */
2787 p_tx_desc_curr->cmd_sts = command_status |
2788 ETH_BUFFER_OWNED_BY_DMA | ETH_TX_ENABLE_INTERRUPT;
2790 if (p_tx_desc_curr != p_tx_desc_first)
2791 p_tx_desc_first->cmd_sts |= ETH_BUFFER_OWNED_BY_DMA;
2793 /* Flush CPU pipe */
2795 D_CACHE_FLUSH_LINE ((unsigned int) p_tx_desc_curr, 0);
2796 D_CACHE_FLUSH_LINE ((unsigned int) p_tx_desc_first, 0);
2799 /* Apply send command */
2800 ETH_ENABLE_TX_QUEUE (tx_queue, p_eth_port_ctrl->port_num);
2802 /* Finish Tx packet. Update first desc in case of Tx resource error */
2803 p_tx_desc_first = p_tx_next_desc_curr;
2804 FIRST_TFD_SET (p_tx_desc_first, tx_queue);
2807 p_tx_desc_curr->cmd_sts = command_status;
2808 D_CACHE_FLUSH_LINE ((unsigned int) p_tx_desc_curr, 0);
2811 /* Check for ring index overlap in the Tx desc ring */
2812 if (p_tx_next_desc_curr == p_tx_desc_used) {
2813 /* Update the current descriptor */
2814 CURR_TFD_SET (p_tx_desc_first, tx_queue);
2816 p_eth_port_ctrl->tx_resource_err[tx_queue] = true;
2817 return ETH_QUEUE_LAST_RESOURCE;
2819 /* Update the current descriptor */
2820 CURR_TFD_SET (p_tx_next_desc_curr, tx_queue);
2825 /*******************************************************************************
2826 * eth_tx_return_desc - Free all used Tx descriptors
2829 * This routine returns the transmitted packet information to the caller.
2830 * It uses the 'first' index to support Tx desc return in case a transmit
2831 * of a packet spanned over multiple buffer still in process.
2832 * In case the Tx queue was in "resource error" condition, where there are
2833 * no available Tx resources, the function resets the resource error flag.
2836 * ETH_PORT_INFO *p_eth_port_ctrl Ethernet Port Control srtuct.
2837 * ETH_QUEUE tx_queue Number of Tx queue.
2838 * PKT_INFO *p_pkt_info User packet buffer.
2841 * Tx ring 'first' and 'used' indexes are updated.
2844 * ETH_ERROR in case the routine can not access Tx desc ring.
2845 * ETH_RETRY in case there is transmission in process.
2846 * ETH_END_OF_JOB if the routine has nothing to release.
2849 *******************************************************************************/
2850 static ETH_FUNC_RET_STATUS eth_tx_return_desc (ETH_PORT_INFO *
2853 PKT_INFO * p_pkt_info)
2855 volatile ETH_TX_DESC *p_tx_desc_used = NULL;
2856 volatile ETH_TX_DESC *p_tx_desc_first = NULL;
2857 unsigned int command_status;
2860 /* Get the Tx Desc ring indexes */
2861 USED_TFD_GET (p_tx_desc_used, tx_queue);
2862 FIRST_TFD_GET (p_tx_desc_first, tx_queue);
2866 if (p_tx_desc_used == NULL)
2869 command_status = p_tx_desc_used->cmd_sts;
2871 /* Still transmitting... */
2872 if (command_status & (ETH_BUFFER_OWNED_BY_DMA)) {
2873 D_CACHE_FLUSH_LINE ((unsigned int) p_tx_desc_used, 0);
2877 /* Stop release. About to overlap the current available Tx descriptor */
2878 if ((p_tx_desc_used == p_tx_desc_first) &&
2879 (p_eth_port_ctrl->tx_resource_err[tx_queue] == false)) {
2880 D_CACHE_FLUSH_LINE ((unsigned int) p_tx_desc_used, 0);
2881 return ETH_END_OF_JOB;
2884 /* Pass the packet information to the caller */
2885 p_pkt_info->cmd_sts = command_status;
2886 p_pkt_info->return_info = p_tx_desc_used->return_info;
2887 p_tx_desc_used->return_info = 0;
2889 /* Update the next descriptor to release. */
2890 USED_TFD_SET (TX_NEXT_DESC_PTR (p_tx_desc_used, tx_queue), tx_queue);
2892 /* Any Tx return cancels the Tx resource error status */
2893 if (p_eth_port_ctrl->tx_resource_err[tx_queue] == true)
2894 p_eth_port_ctrl->tx_resource_err[tx_queue] = false;
2896 D_CACHE_FLUSH_LINE ((unsigned int) p_tx_desc_used, 0);
2902 /*******************************************************************************
2903 * eth_port_receive - Get received information from Rx ring.
2906 * This routine returns the received data to the caller. There is no
2907 * data copying during routine operation. All information is returned
2908 * using pointer to packet information struct passed from the caller.
2909 * If the routine exhausts Rx ring resources then the resource error flag
2913 * ETH_PORT_INFO *p_eth_port_ctrl Ethernet Port Control srtuct.
2914 * ETH_QUEUE rx_queue Number of Rx queue.
2915 * PKT_INFO *p_pkt_info User packet buffer.
2918 * Rx ring current and used indexes are updated.
2921 * ETH_ERROR in case the routine can not access Rx desc ring.
2922 * ETH_QUEUE_FULL if Rx ring resources are exhausted.
2923 * ETH_END_OF_JOB if there is no received data.
2926 *******************************************************************************/
2927 static ETH_FUNC_RET_STATUS eth_port_receive (ETH_PORT_INFO * p_eth_port_ctrl,
2929 PKT_INFO * p_pkt_info)
2931 volatile ETH_RX_DESC *p_rx_curr_desc;
2932 volatile ETH_RX_DESC *p_rx_next_curr_desc;
2933 volatile ETH_RX_DESC *p_rx_used_desc;
2934 unsigned int command_status;
2936 /* Do not process Rx ring in case of Rx ring resource error */
2937 if (p_eth_port_ctrl->rx_resource_err[rx_queue] == true) {
2938 printf ("\nRx Queue is full ...\n");
2939 return ETH_QUEUE_FULL;
2942 /* Get the Rx Desc ring 'curr and 'used' indexes */
2943 CURR_RFD_GET (p_rx_curr_desc, rx_queue);
2944 USED_RFD_GET (p_rx_used_desc, rx_queue);
2947 if (p_rx_curr_desc == NULL)
2950 /* The following parameters are used to save readings from memory */
2951 p_rx_next_curr_desc = RX_NEXT_DESC_PTR (p_rx_curr_desc, rx_queue);
2952 command_status = p_rx_curr_desc->cmd_sts;
2954 /* Nothing to receive... */
2955 if (command_status & (ETH_BUFFER_OWNED_BY_DMA)) {
2956 /* DP(printf("Rx: command_status: %08x\n", command_status)); */
2957 D_CACHE_FLUSH_LINE ((unsigned int) p_rx_curr_desc, 0);
2958 /* DP(printf("\nETH_END_OF_JOB ...\n"));*/
2959 return ETH_END_OF_JOB;
2962 p_pkt_info->byte_cnt = (p_rx_curr_desc->byte_cnt) - RX_BUF_OFFSET;
2963 p_pkt_info->cmd_sts = command_status;
2964 p_pkt_info->buf_ptr = (p_rx_curr_desc->buf_ptr) + RX_BUF_OFFSET;
2965 p_pkt_info->return_info = p_rx_curr_desc->return_info;
2966 p_pkt_info->l4i_chk = p_rx_curr_desc->buf_size; /* IP fragment indicator */
2968 /* Clean the return info field to indicate that the packet has been */
2969 /* moved to the upper layers */
2970 p_rx_curr_desc->return_info = 0;
2972 /* Update 'curr' in data structure */
2973 CURR_RFD_SET (p_rx_next_curr_desc, rx_queue);
2975 /* Rx descriptors resource exhausted. Set the Rx ring resource error flag */
2976 if (p_rx_next_curr_desc == p_rx_used_desc)
2977 p_eth_port_ctrl->rx_resource_err[rx_queue] = true;
2979 D_CACHE_FLUSH_LINE ((unsigned int) p_rx_curr_desc, 0);
2984 /*******************************************************************************
2985 * eth_rx_return_buff - Returns a Rx buffer back to the Rx ring.
2988 * This routine returns a Rx buffer back to the Rx ring. It retrieves the
2989 * next 'used' descriptor and attached the returned buffer to it.
2990 * In case the Rx ring was in "resource error" condition, where there are
2991 * no available Rx resources, the function resets the resource error flag.
2994 * ETH_PORT_INFO *p_eth_port_ctrl Ethernet Port Control srtuct.
2995 * ETH_QUEUE rx_queue Number of Rx queue.
2996 * PKT_INFO *p_pkt_info Information on the returned buffer.
2999 * New available Rx resource in Rx descriptor ring.
3002 * ETH_ERROR in case the routine can not access Rx desc ring.
3005 *******************************************************************************/
3006 static ETH_FUNC_RET_STATUS eth_rx_return_buff (ETH_PORT_INFO *
3009 PKT_INFO * p_pkt_info)
3011 volatile ETH_RX_DESC *p_used_rx_desc; /* Where to return Rx resource */
3013 /* Get 'used' Rx descriptor */
3014 USED_RFD_GET (p_used_rx_desc, rx_queue);
3017 if (p_used_rx_desc == NULL)
3020 p_used_rx_desc->buf_ptr = p_pkt_info->buf_ptr;
3021 p_used_rx_desc->return_info = p_pkt_info->return_info;
3022 p_used_rx_desc->byte_cnt = p_pkt_info->byte_cnt;
3023 p_used_rx_desc->buf_size = MV64460_RX_BUFFER_SIZE; /* Reset Buffer size */
3025 /* Flush the write pipe */
3028 /* Return the descriptor to DMA ownership */
3029 p_used_rx_desc->cmd_sts =
3030 ETH_BUFFER_OWNED_BY_DMA | ETH_RX_ENABLE_INTERRUPT;
3032 /* Flush descriptor and CPU pipe */
3033 D_CACHE_FLUSH_LINE ((unsigned int) p_used_rx_desc, 0);
3036 /* Move the used descriptor pointer to the next descriptor */
3037 USED_RFD_SET (RX_NEXT_DESC_PTR (p_used_rx_desc, rx_queue), rx_queue);
3039 /* Any Rx return cancels the Rx resource error status */
3040 if (p_eth_port_ctrl->rx_resource_err[rx_queue] == true)
3041 p_eth_port_ctrl->rx_resource_err[rx_queue] = false;
3046 /*******************************************************************************
3047 * eth_port_set_rx_coal - Sets coalescing interrupt mechanism on RX path
3050 * This routine sets the RX coalescing interrupt mechanism parameter.
3051 * This parameter is a timeout counter, that counts in 64 t_clk
3052 * chunks ; that when timeout event occurs a maskable interrupt
3054 * The parameter is calculated using the tClk of the MV-643xx chip
3055 * , and the required delay of the interrupt in usec.
3058 * ETH_PORT eth_port_num Ethernet port number
3059 * unsigned int t_clk t_clk of the MV-643xx chip in HZ units
3060 * unsigned int delay Delay in usec
3063 * Interrupt coalescing mechanism value is set in MV-643xx chip.
3066 * The interrupt coalescing value set in the gigE port.
3068 *******************************************************************************/
3070 static unsigned int eth_port_set_rx_coal (ETH_PORT eth_port_num,
3076 coal = ((t_clk / 1000000) * delay) / 64;
3077 /* Set RX Coalescing mechanism */
3078 MV_REG_WRITE (MV64460_ETH_SDMA_CONFIG_REG (eth_port_num),
3079 ((coal & 0x3fff) << 8) |
3081 (MV64460_ETH_SDMA_CONFIG_REG (eth_port_num))
3087 /*******************************************************************************
3088 * eth_port_set_tx_coal - Sets coalescing interrupt mechanism on TX path
3091 * This routine sets the TX coalescing interrupt mechanism parameter.
3092 * This parameter is a timeout counter, that counts in 64 t_clk
3093 * chunks ; that when timeout event occurs a maskable interrupt
3095 * The parameter is calculated using the t_cLK frequency of the
3096 * MV-643xx chip and the required delay in the interrupt in uSec
3099 * ETH_PORT eth_port_num Ethernet port number
3100 * unsigned int t_clk t_clk of the MV-643xx chip in HZ units
3101 * unsigned int delay Delay in uSeconds
3104 * Interrupt coalescing mechanism value is set in MV-643xx chip.
3107 * The interrupt coalescing value set in the gigE port.
3109 *******************************************************************************/
3111 static unsigned int eth_port_set_tx_coal (ETH_PORT eth_port_num,
3117 coal = ((t_clk / 1000000) * delay) / 64;
3118 /* Set TX Coalescing mechanism */
3119 MV_REG_WRITE (MV64460_ETH_TX_FIFO_URGENT_THRESHOLD_REG (eth_port_num),
3125 /*******************************************************************************
3126 * eth_b_copy - Copy bytes from source to destination
3129 * This function supports the eight bytes limitation on Tx buffer size.
3130 * The routine will zero eight bytes starting from the destination address
3131 * followed by copying bytes from the source address to the destination.
3134 * unsigned int src_addr 32 bit source address.
3135 * unsigned int dst_addr 32 bit destination address.
3136 * int byte_count Number of bytes to copy.
3144 *******************************************************************************/
3145 static void eth_b_copy (unsigned int src_addr, unsigned int dst_addr,
3148 /* Zero the dst_addr area */
3149 *(unsigned int *) dst_addr = 0x0;
3151 while (byte_count != 0) {
3152 *(char *) dst_addr = *(char *) src_addr;