3 * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 /*************************************************************************
25 * adaption for the Marvell DB64460 Board
26 * Ingo Assmus (ingo.assmus@keymile.com)
27 ************************************************************************/
30 /* sdram_init.c - automatic memory sizing */
34 #include "../include/memory.h"
35 #include "../include/pci.h"
36 #include "../include/mv_gen_reg.h"
41 #include "../common/i2c.h"
45 DECLARE_GLOBAL_DATA_PTR;
49 int set_dfcdlInit (void); /* setup delay line of Mv64460 */
50 int mvDmaIsChannelActive (int);
51 int mvDmaSetMemorySpace (ulong, ulong, ulong, ulong, ulong);
52 int mvDmaTransfer (int, ulong, ulong, ulong, ulong);
54 /* ------------------------------------------------------------------------- */
57 memory_map_bank (unsigned int bankNo,
58 unsigned int bankBase, unsigned int bankLength)
66 debug("mapping bank %d at %08x - %08x\n",
67 bankNo, bankBase, bankBase + bankLength - 1);
69 debug("unmapping bank %d\n", bankNo);
72 memoryMapBank (bankNo, bankBase, bankLength);
75 for (host = PCI_HOST0; host <= PCI_HOST1; host++) {
80 READ_LINE_AGGRESSIVE_PREFETCH |
81 READ_MULTI_AGGRESSIVE_PREFETCH |
82 MAX_BURST_4 | PCI_NO_SWAP;
84 pciMapMemoryBank (host, bankNo, bankBase, bankLength);
86 pciSetRegionSnoopMode (host, bankNo, PCI_SNOOP_WB, bankBase,
89 pciSetRegionFeatures (host, bankNo, features, bankBase,
98 /* much of this code is based on (or is) the code in the pip405 port */
99 /* thanks go to the authors of said port - Josh */
101 /* structure to store the relevant information about an sdram bank */
102 typedef struct sdram_info {
104 uchar registered, ecc;
111 /* Typedefs for 'gtAuxilGetDIMMinfo' function */
113 typedef enum _memoryType { SDRAM, DDR } MEMORY_TYPE;
115 typedef enum _voltageInterface { TTL_5V_TOLERANT, LVTTL, HSTL_1_5V,
116 SSTL_3_3V, SSTL_2_5V, VOLTAGE_UNKNOWN,
119 typedef enum _max_CL_supported_DDR { DDR_CL_1 = 1, DDR_CL_1_5 = 2, DDR_CL_2 =
120 4, DDR_CL_2_5 = 8, DDR_CL_3 = 16, DDR_CL_3_5 =
121 32, DDR_CL_FAULT } MAX_CL_SUPPORTED_DDR;
122 typedef enum _max_CL_supported_SD { SD_CL_1 =
123 1, SD_CL_2, SD_CL_3, SD_CL_4, SD_CL_5, SD_CL_6, SD_CL_7,
124 SD_FAULT } MAX_CL_SUPPORTED_SD;
127 /* SDRAM/DDR information struct */
128 typedef struct _gtMemoryDimmInfo {
129 MEMORY_TYPE memoryType;
130 unsigned int numOfRowAddresses;
131 unsigned int numOfColAddresses;
132 unsigned int numOfModuleBanks;
133 unsigned int dataWidth;
134 VOLTAGE_INTERFACE voltageInterface;
135 unsigned int errorCheckType; /* ECC , PARITY.. */
136 unsigned int sdramWidth; /* 4,8,16 or 32 */ ;
137 unsigned int errorCheckDataWidth; /* 0 - no, 1 - Yes */
138 unsigned int minClkDelay;
139 unsigned int burstLengthSupported;
140 unsigned int numOfBanksOnEachDevice;
141 unsigned int suportedCasLatencies;
142 unsigned int RefreshInterval;
143 unsigned int maxCASlatencySupported_LoP; /* LoP left of point (measured in ns) */
144 unsigned int maxCASlatencySupported_RoP; /* RoP right of point (measured in ns) */
145 MAX_CL_SUPPORTED_DDR maxClSupported_DDR;
146 MAX_CL_SUPPORTED_SD maxClSupported_SD;
147 unsigned int moduleBankDensity;
148 /* module attributes (true for yes) */
149 bool bufferedAddrAndControlInputs;
150 bool registeredAddrAndControlInputs;
152 bool bufferedDQMBinputs;
153 bool registeredDQMBinputs;
154 bool differentialClockInput;
155 bool redundantRowAddressing;
157 /* module general attributes */
158 bool suportedAutoPreCharge;
159 bool suportedPreChargeAll;
160 bool suportedEarlyRasPreCharge;
161 bool suportedWrite1ReadBurst;
162 bool suported5PercentLowVCC;
163 bool suported5PercentUpperVCC;
164 /* module timing parameters */
165 unsigned int minRasToCasDelay;
166 unsigned int minRowActiveRowActiveDelay;
167 unsigned int minRasPulseWidth;
168 unsigned int minRowPrechargeTime; /* measured in ns */
170 int addrAndCommandHoldTime; /* LoP left of point (measured in ns) */
171 int addrAndCommandSetupTime; /* (measured in ns/100) */
172 int dataInputSetupTime; /* LoP left of point (measured in ns) */
173 int dataInputHoldTime; /* LoP left of point (measured in ns) */
174 /* tAC times for highest 2nd and 3rd highest CAS Latency values */
175 unsigned int clockToDataOut_LoP; /* LoP left of point (measured in ns) */
176 unsigned int clockToDataOut_RoP; /* RoP right of point (measured in ns) */
177 unsigned int clockToDataOutMinus1_LoP; /* LoP left of point (measured in ns) */
178 unsigned int clockToDataOutMinus1_RoP; /* RoP right of point (measured in ns) */
179 unsigned int clockToDataOutMinus2_LoP; /* LoP left of point (measured in ns) */
180 unsigned int clockToDataOutMinus2_RoP; /* RoP right of point (measured in ns) */
182 unsigned int minimumCycleTimeAtMaxCasLatancy_LoP; /* LoP left of point (measured in ns) */
183 unsigned int minimumCycleTimeAtMaxCasLatancy_RoP; /* RoP right of point (measured in ns) */
185 unsigned int minimumCycleTimeAtMaxCasLatancyMinus1_LoP; /* LoP left of point (measured in ns) */
186 unsigned int minimumCycleTimeAtMaxCasLatancyMinus1_RoP; /* RoP right of point (measured in ns) */
188 unsigned int minimumCycleTimeAtMaxCasLatancyMinus2_LoP; /* LoP left of point (measured in ns) */
189 unsigned int minimumCycleTimeAtMaxCasLatancyMinus2_RoP; /* RoP right of point (measured in ns) */
191 /* Parameters calculated from
192 the extracted DIMM information */
194 unsigned int deviceDensity; /* 16,64,128,256 or 512 Mbit */
195 unsigned int numberOfDevices;
196 uchar drb_size; /* DRAM size in n*64Mbit */
197 uchar slot; /* Slot Number this module is inserted in */
198 uchar spd_raw_data[128]; /* Content of SPD-EEPROM copied 1:1 */
200 uchar manufactura[8]; /* Content of SPD-EEPROM Byte 64-71 */
201 uchar modul_id[18]; /* Content of SPD-EEPROM Byte 73-90 */
202 uchar vendor_data[27]; /* Content of SPD-EEPROM Byte 99-125 */
203 unsigned long modul_serial_no; /* Content of SPD-EEPROM Byte 95-98 */
204 unsigned int manufac_date; /* Content of SPD-EEPROM Byte 93-94 */
205 unsigned int modul_revision; /* Content of SPD-EEPROM Byte 91-92 */
206 uchar manufac_place; /* Content of SPD-EEPROM Byte 72 */
213 * translate ns.ns/10 coding of SPD timing values
214 * into 10 ps unit values
216 static inline unsigned short NS10to10PS (unsigned char spd_byte)
218 unsigned short ns, ns10;
220 /* isolate upper nibble */
221 ns = (spd_byte >> 4) & 0x0F;
222 /* isolate lower nibble */
223 ns10 = (spd_byte & 0x0F);
225 return (ns * 100 + ns10 * 10);
229 * translate ns coding of SPD timing values
230 * into 10 ps unit values
232 static inline unsigned short NSto10PS (unsigned char spd_byte)
234 return (spd_byte * 100);
237 /* This code reads the SPD chip on the sdram and populates
238 * the array which is passed in with the relevant information */
239 /* static int check_dimm(uchar slot, AUX_MEM_DIMM_INFO *info) */
240 static int check_dimm (uchar slot, AUX_MEM_DIMM_INFO * dimmInfo)
242 unsigned long spd_checksum;
245 /* zero all the values */
246 memset (info, 0, sizeof (*info));
252 info->registered = 0;
253 info->drb_size = 16;*/ /* 16 - 256MBit, 32 - 512MBit */
255 info->tras_clocks = 5;
258 #ifdef CONFIG_MV64460_ECC
259 /* check for ECC/parity [0 = none, 1 = parity, 2 = ecc] */
260 dimmInfo->errorCheckType = 2;
268 uchar addr = slot == 0 ? DIMM0_I2C_ADDR : DIMM1_I2C_ADDR;
270 unsigned int i, j, density = 1;
275 unsigned int rightOfPoint = 0, leftOfPoint = 0, mult, div, time_tmp;
276 int sign = 1, shift, maskLeftOfPoint, maskRightOfPoint;
277 uchar supp_cal, cal_val;
278 ulong memclk, tmemclk;
280 uchar trp_clocks = 0, tras_clocks;
283 memclk = gd->bus_clk;
284 tmemclk = 1000000000 / (memclk / 100); /* in 10 ps units */
286 debug("before i2c read\n");
288 ret = i2c_read (addr, 0, 1, data, 128);
290 debug("after i2c read\n");
292 /* zero all the values */
293 memset (dimmInfo, 0, sizeof (*dimmInfo));
295 /* copy the SPD content 1:1 into the dimmInfo structure */
296 for (i = 0; i <= 127; i++) {
297 dimmInfo->spd_raw_data[i] = data[i];
301 debug("No DIMM in slot %d [err = %x]\n", slot, ret);
304 dimmInfo->slot = slot; /* start to fill up dimminfo for this "slot" */
306 #ifdef CONFIG_SYS_DISPLAY_DIMM_SPD_CONTENT
308 for (i = 0; i <= 127; i++) {
309 printf ("SPD-EEPROM Byte %3d = %3x (%3d)\n", i, data[i],
315 /* find Manufactura of Dimm Module */
316 for (i = 0; i < sizeof (dimmInfo->manufactura); i++) {
317 dimmInfo->manufactura[i] = data[64 + i];
319 printf ("\nThis RAM-Module is produced by: %s\n",
320 dimmInfo->manufactura);
322 /* find Manul-ID of Dimm Module */
323 for (i = 0; i < sizeof (dimmInfo->modul_id); i++) {
324 dimmInfo->modul_id[i] = data[73 + i];
326 printf ("The Module-ID of this RAM-Module is: %s\n",
329 /* find Vendor-Data of Dimm Module */
330 for (i = 0; i < sizeof (dimmInfo->vendor_data); i++) {
331 dimmInfo->vendor_data[i] = data[99 + i];
333 printf ("Vendor Data of this RAM-Module is: %s\n",
334 dimmInfo->vendor_data);
336 /* find modul_serial_no of Dimm Module */
337 dimmInfo->modul_serial_no = (*((unsigned long *) (&data[95])));
338 printf ("Serial No. of this RAM-Module is: %ld (%lx)\n",
339 dimmInfo->modul_serial_no, dimmInfo->modul_serial_no);
341 /* find Manufac-Data of Dimm Module */
342 dimmInfo->manufac_date = (*((unsigned int *) (&data[93])));
343 printf ("Manufactoring Date of this RAM-Module is: %d.%d\n", data[93], data[94]); /*dimmInfo->manufac_date */
345 /* find modul_revision of Dimm Module */
346 dimmInfo->modul_revision = (*((unsigned int *) (&data[91])));
347 printf ("Module Revision of this RAM-Module is: %d.%d\n", data[91], data[92]); /* dimmInfo->modul_revision */
349 /* find manufac_place of Dimm Module */
350 dimmInfo->manufac_place = (*((unsigned char *) (&data[72])));
351 printf ("manufac_place of this RAM-Module is: %d\n",
352 dimmInfo->manufac_place);
356 /*------------------------------------------------------------------------------------------------------------------------------*/
357 /* calculate SPD checksum */
358 /*------------------------------------------------------------------------------------------------------------------------------*/
361 for (i = 0; i <= 62; i++) {
362 spd_checksum += data[i];
365 if ((spd_checksum & 0xff) != data[63]) {
366 printf ("### Error in SPD Checksum !!! Is_value: %2x should value %2x\n", (unsigned int) (spd_checksum & 0xff), data[63]);
371 printf ("SPD Checksum ok!\n");
374 /*------------------------------------------------------------------------------------------------------------------------------*/
375 for (i = 2; i <= 35; i++) {
377 case 2: /* Memory type (DDR / SDRAM) */
378 dimmInfo->memoryType = (data[i] == 0x7) ? DDR : SDRAM;
380 if (dimmInfo->memoryType == 0)
382 ("Dram_type in slot %d is: SDRAM\n",
384 if (dimmInfo->memoryType == 1)
386 ("Dram_type in slot %d is: DDRAM\n",
390 /*------------------------------------------------------------------------------------------------------------------------------*/
392 case 3: /* Number Of Row Addresses */
393 dimmInfo->numOfRowAddresses = data[i];
395 ("Module Number of row addresses: %d\n",
396 dimmInfo->numOfRowAddresses);
398 /*------------------------------------------------------------------------------------------------------------------------------*/
400 case 4: /* Number Of Column Addresses */
401 dimmInfo->numOfColAddresses = data[i];
403 ("Module Number of col addresses: %d\n",
404 dimmInfo->numOfColAddresses);
406 /*------------------------------------------------------------------------------------------------------------------------------*/
408 case 5: /* Number Of Module Banks */
409 dimmInfo->numOfModuleBanks = data[i];
411 ("Number of Banks on Mod. : %d\n",
412 dimmInfo->numOfModuleBanks);
414 /*------------------------------------------------------------------------------------------------------------------------------*/
416 case 6: /* Data Width */
417 dimmInfo->dataWidth = data[i];
419 ("Module Data Width: %d\n",
420 dimmInfo->dataWidth);
422 /*------------------------------------------------------------------------------------------------------------------------------*/
424 case 8: /* Voltage Interface */
427 dimmInfo->voltageInterface = TTL_5V_TOLERANT;
429 ("Module is TTL_5V_TOLERANT\n");
432 dimmInfo->voltageInterface = LVTTL;
434 ("Module is LVTTL\n");
437 dimmInfo->voltageInterface = HSTL_1_5V;
439 ("Module is TTL_5V_TOLERANT\n");
442 dimmInfo->voltageInterface = SSTL_3_3V;
444 ("Module is HSTL_1_5V\n");
447 dimmInfo->voltageInterface = SSTL_2_5V;
449 ("Module is SSTL_2_5V\n");
452 dimmInfo->voltageInterface = VOLTAGE_UNKNOWN;
454 ("Module is VOLTAGE_UNKNOWN\n");
458 /*------------------------------------------------------------------------------------------------------------------------------*/
460 case 9: /* Minimum Cycle Time At Max CasLatancy */
461 shift = (dimmInfo->memoryType == DDR) ? 4 : 2;
462 mult = (dimmInfo->memoryType == DDR) ? 10 : 25;
464 (dimmInfo->memoryType == DDR) ? 0xf0 : 0xfc;
466 (dimmInfo->memoryType == DDR) ? 0xf : 0x03;
467 leftOfPoint = (data[i] & maskLeftOfPoint) >> shift;
468 rightOfPoint = (data[i] & maskRightOfPoint) * mult;
469 dimmInfo->minimumCycleTimeAtMaxCasLatancy_LoP =
471 dimmInfo->minimumCycleTimeAtMaxCasLatancy_RoP =
474 ("Minimum Cycle Time At Max CasLatancy: %d.%d [ns]\n",
475 leftOfPoint, rightOfPoint);
477 /*------------------------------------------------------------------------------------------------------------------------------*/
479 case 10: /* Clock To Data Out */
480 div = (dimmInfo->memoryType == DDR) ? 100 : 10;
482 (((data[i] & 0xf0) >> 4) * 10) +
484 leftOfPoint = time_tmp / div;
485 rightOfPoint = time_tmp % div;
486 dimmInfo->clockToDataOut_LoP = leftOfPoint;
487 dimmInfo->clockToDataOut_RoP = rightOfPoint;
488 debug("Clock To Data Out: %d.%2d [ns]\n", leftOfPoint, rightOfPoint); /*dimmInfo->clockToDataOut */
490 /*------------------------------------------------------------------------------------------------------------------------------*/
492 /*#ifdef CONFIG_ECC */
493 case 11: /* Error Check Type */
494 dimmInfo->errorCheckType = data[i];
496 ("Error Check Type (0=NONE): %d\n",
497 dimmInfo->errorCheckType);
500 /*------------------------------------------------------------------------------------------------------------------------------*/
502 case 12: /* Refresh Interval */
503 dimmInfo->RefreshInterval = data[i];
505 ("RefreshInterval (80= Self refresh Normal, 15.625us) : %x\n",
506 dimmInfo->RefreshInterval);
508 /*------------------------------------------------------------------------------------------------------------------------------*/
510 case 13: /* Sdram Width */
511 dimmInfo->sdramWidth = data[i];
513 ("Sdram Width: %d\n",
514 dimmInfo->sdramWidth);
516 /*------------------------------------------------------------------------------------------------------------------------------*/
518 case 14: /* Error Check Data Width */
519 dimmInfo->errorCheckDataWidth = data[i];
521 ("Error Check Data Width: %d\n",
522 dimmInfo->errorCheckDataWidth);
524 /*------------------------------------------------------------------------------------------------------------------------------*/
526 case 15: /* Minimum Clock Delay */
527 dimmInfo->minClkDelay = data[i];
529 ("Minimum Clock Delay: %d\n",
530 dimmInfo->minClkDelay);
532 /*------------------------------------------------------------------------------------------------------------------------------*/
534 case 16: /* Burst Length Supported */
535 /******-******-******-*******
536 * bit3 | bit2 | bit1 | bit0 *
537 *******-******-******-*******
538 burst length = * 8 | 4 | 2 | 1 *
539 *****************************
541 If for example bit0 and bit2 are set, the burst
542 length supported are 1 and 4. */
544 dimmInfo->burstLengthSupported = data[i];
547 ("Burst Length Supported: ");
548 if (dimmInfo->burstLengthSupported & 0x01)
550 if (dimmInfo->burstLengthSupported & 0x02)
552 if (dimmInfo->burstLengthSupported & 0x04)
554 if (dimmInfo->burstLengthSupported & 0x08)
559 /*------------------------------------------------------------------------------------------------------------------------------*/
561 case 17: /* Number Of Banks On Each Device */
562 dimmInfo->numOfBanksOnEachDevice = data[i];
564 ("Number Of Banks On Each Chip: %d\n",
565 dimmInfo->numOfBanksOnEachDevice);
567 /*------------------------------------------------------------------------------------------------------------------------------*/
569 case 18: /* Suported Cas Latencies */
572 *******-******-******-******-******-******-******-*******
573 * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 *
574 *******-******-******-******-******-******-******-*******
575 CAS = * TBD | TBD | 3.5 | 3 | 2.5 | 2 | 1.5 | 1 *
576 *********************************************************
578 *******-******-******-******-******-******-******-*******
579 * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 *
580 *******-******-******-******-******-******-******-*******
581 CAS = * TBD | 7 | 6 | 5 | 4 | 3 | 2 | 1 *
582 ********************************************************/
583 dimmInfo->suportedCasLatencies = data[i];
586 ("Suported Cas Latencies: (CL) ");
587 if (dimmInfo->memoryType == 0) { /* SDRAM */
588 for (k = 0; k <= 7; k++) {
590 suportedCasLatencies & (1 << k))
596 } else { /* DDR-RAM */
598 if (dimmInfo->suportedCasLatencies & 1)
600 if (dimmInfo->suportedCasLatencies & 2)
602 if (dimmInfo->suportedCasLatencies & 4)
604 if (dimmInfo->suportedCasLatencies & 8)
606 if (dimmInfo->suportedCasLatencies & 16)
608 if (dimmInfo->suportedCasLatencies & 32)
614 /* Calculating MAX CAS latency */
615 for (j = 7; j > 0; j--) {
617 suportedCasLatencies >> j) & 0x1) ==
619 switch (dimmInfo->memoryType) {
621 /* CAS latency 1, 1.5, 2, 2.5, 3, 3.5 */
625 ("Max. Cas Latencies (DDR): ERROR !!!\n");
634 ("Max. Cas Latencies (DDR): ERROR !!!\n");
643 ("Max. Cas Latencies (DDR): 3.5 clk's\n");
650 ("Max. Cas Latencies (DDR): 3 clk's \n");
657 ("Max. Cas Latencies (DDR): 2.5 clk's \n");
664 ("Max. Cas Latencies (DDR): 2 clk's \n");
671 ("Max. Cas Latencies (DDR): 1.5 clk's \n");
678 /* ronen - in case we have a DIMM with minimumCycleTimeAtMaxCasLatancy
679 lower then our SDRAM cycle count, we won't be able to support this CAL
680 and we will have to use lower CAL. (minus - means from 3.0 to 2.5) */
682 minimumCycleTimeAtMaxCasLatancy_LoP
684 CONFIG_SYS_DDR_SDRAM_CYCLE_COUNT_LOP)
687 minimumCycleTimeAtMaxCasLatancy_LoP
689 CONFIG_SYS_DDR_SDRAM_CYCLE_COUNT_LOP)
691 minimumCycleTimeAtMaxCasLatancy_RoP
693 CONFIG_SYS_DDR_SDRAM_CYCLE_COUNT_ROP)))
702 ("*** Change actual Cas Latencies cause of minimumCycleTime n");
704 /* ronen - checkif the Dimm frequency compared to the Sysclock. */
706 minimumCycleTimeAtMaxCasLatancy_LoP
708 CONFIG_SYS_DDR_SDRAM_CYCLE_COUNT_LOP)
711 minimumCycleTimeAtMaxCasLatancy_LoP
713 CONFIG_SYS_DDR_SDRAM_CYCLE_COUNT_LOP)
715 minimumCycleTimeAtMaxCasLatancy_RoP
717 CONFIG_SYS_DDR_SDRAM_CYCLE_COUNT_ROP)))
719 printf ("*********************************************************\n");
720 printf ("*** sysClock is higher than SDRAM's allowed frequency ***\n");
721 printf ("*********************************************************\n");
726 maxCASlatencySupported_LoP
730 if (((5 * j) % 10) != 0)
732 maxCASlatencySupported_RoP
736 maxCASlatencySupported_RoP
739 ("Max. Cas Latencies (DDR LoP.RoP Notation): %d.%d \n",
741 maxCASlatencySupported_LoP,
743 maxCASlatencySupported_RoP);
746 /* CAS latency 1, 2, 3, 4, 5, 6, 7 */
747 dimmInfo->maxClSupported_SD = j; /* Cas Latency DDR-RAM Coded */
749 ("Max. Cas Latencies (SD): %d\n",
753 maxCASlatencySupported_LoP
756 maxCASlatencySupported_RoP
759 ("Max. Cas Latencies (DDR LoP.RoP Notation): %d.%d \n",
761 maxCASlatencySupported_LoP,
763 maxCASlatencySupported_RoP);
770 /*------------------------------------------------------------------------------------------------------------------------------*/
772 case 21: /* Buffered Address And Control Inputs */
773 debug("\nModul Attributes (SPD Byte 21): \n");
774 dimmInfo->bufferedAddrAndControlInputs =
776 dimmInfo->registeredAddrAndControlInputs =
777 (data[i] & BIT1) >> 1;
778 dimmInfo->onCardPLL = (data[i] & BIT2) >> 2;
779 dimmInfo->bufferedDQMBinputs = (data[i] & BIT3) >> 3;
780 dimmInfo->registeredDQMBinputs =
781 (data[i] & BIT4) >> 4;
782 dimmInfo->differentialClockInput =
783 (data[i] & BIT5) >> 5;
784 dimmInfo->redundantRowAddressing =
785 (data[i] & BIT6) >> 6;
787 if (dimmInfo->bufferedAddrAndControlInputs == 1)
789 (" - Buffered Address/Control Input: Yes \n");
792 (" - Buffered Address/Control Input: No \n");
794 if (dimmInfo->registeredAddrAndControlInputs == 1)
796 (" - Registered Address/Control Input: Yes \n");
799 (" - Registered Address/Control Input: No \n");
801 if (dimmInfo->onCardPLL == 1)
803 (" - On-Card PLL (clock): Yes \n");
806 (" - On-Card PLL (clock): No \n");
808 if (dimmInfo->bufferedDQMBinputs == 1)
810 (" - Bufferd DQMB Inputs: Yes \n");
813 (" - Bufferd DQMB Inputs: No \n");
815 if (dimmInfo->registeredDQMBinputs == 1)
817 (" - Registered DQMB Inputs: Yes \n");
820 (" - Registered DQMB Inputs: No \n");
822 if (dimmInfo->differentialClockInput == 1)
824 (" - Differential Clock Input: Yes \n");
827 (" - Differential Clock Input: No \n");
829 if (dimmInfo->redundantRowAddressing == 1)
831 (" - redundant Row Addressing: Yes \n");
834 (" - redundant Row Addressing: No \n");
838 /*------------------------------------------------------------------------------------------------------------------------------*/
840 case 22: /* Suported AutoPreCharge */
841 debug("\nModul Attributes (SPD Byte 22): \n");
842 dimmInfo->suportedEarlyRasPreCharge = data[i] & BIT0;
843 dimmInfo->suportedAutoPreCharge =
844 (data[i] & BIT1) >> 1;
845 dimmInfo->suportedPreChargeAll =
846 (data[i] & BIT2) >> 2;
847 dimmInfo->suportedWrite1ReadBurst =
848 (data[i] & BIT3) >> 3;
849 dimmInfo->suported5PercentLowVCC =
850 (data[i] & BIT4) >> 4;
851 dimmInfo->suported5PercentUpperVCC =
852 (data[i] & BIT5) >> 5;
854 if (dimmInfo->suportedEarlyRasPreCharge == 1)
856 (" - Early Ras Precharge: Yes \n");
859 (" - Early Ras Precharge: No \n");
861 if (dimmInfo->suportedAutoPreCharge == 1)
863 (" - AutoPreCharge: Yes \n");
866 (" - AutoPreCharge: No \n");
868 if (dimmInfo->suportedPreChargeAll == 1)
870 (" - Precharge All: Yes \n");
873 (" - Precharge All: No \n");
875 if (dimmInfo->suportedWrite1ReadBurst == 1)
877 (" - Write 1/ReadBurst: Yes \n");
880 (" - Write 1/ReadBurst: No \n");
882 if (dimmInfo->suported5PercentLowVCC == 1)
884 (" - lower VCC tolerance: 5 Percent \n");
887 (" - lower VCC tolerance: 10 Percent \n");
889 if (dimmInfo->suported5PercentUpperVCC == 1)
891 (" - upper VCC tolerance: 5 Percent \n");
894 (" - upper VCC tolerance: 10 Percent \n");
898 /*------------------------------------------------------------------------------------------------------------------------------*/
900 case 23: /* Minimum Cycle Time At Maximum Cas Latancy Minus 1 (2nd highest CL) */
901 shift = (dimmInfo->memoryType == DDR) ? 4 : 2;
902 mult = (dimmInfo->memoryType == DDR) ? 10 : 25;
904 (dimmInfo->memoryType == DDR) ? 0xf0 : 0xfc;
906 (dimmInfo->memoryType == DDR) ? 0xf : 0x03;
907 leftOfPoint = (data[i] & maskLeftOfPoint) >> shift;
908 rightOfPoint = (data[i] & maskRightOfPoint) * mult;
909 dimmInfo->minimumCycleTimeAtMaxCasLatancyMinus1_LoP =
911 dimmInfo->minimumCycleTimeAtMaxCasLatancyMinus1_RoP =
913 debug("Minimum Cycle Time At 2nd highest CasLatancy (0 = Not supported): %d.%d [ns]\n", leftOfPoint, rightOfPoint); /*dimmInfo->minimumCycleTimeAtMaxCasLatancy */
915 /*------------------------------------------------------------------------------------------------------------------------------*/
917 case 24: /* Clock To Data Out 2nd highest Cas Latency Value */
918 div = (dimmInfo->memoryType == DDR) ? 100 : 10;
920 (((data[i] & 0xf0) >> 4) * 10) +
922 leftOfPoint = time_tmp / div;
923 rightOfPoint = time_tmp % div;
924 dimmInfo->clockToDataOutMinus1_LoP = leftOfPoint;
925 dimmInfo->clockToDataOutMinus1_RoP = rightOfPoint;
927 ("Clock To Data Out (2nd CL value): %d.%2d [ns]\n",
928 leftOfPoint, rightOfPoint);
930 /*------------------------------------------------------------------------------------------------------------------------------*/
932 case 25: /* Minimum Cycle Time At Maximum Cas Latancy Minus 2 (3rd highest CL) */
933 shift = (dimmInfo->memoryType == DDR) ? 4 : 2;
934 mult = (dimmInfo->memoryType == DDR) ? 10 : 25;
936 (dimmInfo->memoryType == DDR) ? 0xf0 : 0xfc;
938 (dimmInfo->memoryType == DDR) ? 0xf : 0x03;
939 leftOfPoint = (data[i] & maskLeftOfPoint) >> shift;
940 rightOfPoint = (data[i] & maskRightOfPoint) * mult;
941 dimmInfo->minimumCycleTimeAtMaxCasLatancyMinus2_LoP =
943 dimmInfo->minimumCycleTimeAtMaxCasLatancyMinus2_RoP =
945 debug("Minimum Cycle Time At 3rd highest CasLatancy (0 = Not supported): %d.%d [ns]\n", leftOfPoint, rightOfPoint); /*dimmInfo->minimumCycleTimeAtMaxCasLatancy */
947 /*------------------------------------------------------------------------------------------------------------------------------*/
949 case 26: /* Clock To Data Out 3rd highest Cas Latency Value */
950 div = (dimmInfo->memoryType == DDR) ? 100 : 10;
952 (((data[i] & 0xf0) >> 4) * 10) +
954 leftOfPoint = time_tmp / div;
955 rightOfPoint = time_tmp % div;
956 dimmInfo->clockToDataOutMinus2_LoP = leftOfPoint;
957 dimmInfo->clockToDataOutMinus2_RoP = rightOfPoint;
959 ("Clock To Data Out (3rd CL value): %d.%2d [ns]\n",
960 leftOfPoint, rightOfPoint);
962 /*------------------------------------------------------------------------------------------------------------------------------*/
964 case 27: /* Minimum Row Precharge Time */
965 shift = (dimmInfo->memoryType == DDR) ? 2 : 0;
967 (dimmInfo->memoryType == DDR) ? 0xfc : 0xff;
969 (dimmInfo->memoryType == DDR) ? 0x03 : 0x00;
970 leftOfPoint = ((data[i] & maskLeftOfPoint) >> shift);
971 rightOfPoint = (data[i] & maskRightOfPoint) * 25;
973 dimmInfo->minRowPrechargeTime = ((leftOfPoint * 100) + rightOfPoint); /* measured in n times 10ps Intervals */
975 (dimmInfo->minRowPrechargeTime +
976 (tmemclk - 1)) / tmemclk;
978 ("*** 1 clock cycle = %ld 10ps intervalls = %ld.%ld ns****\n",
979 tmemclk, tmemclk / 100, tmemclk % 100);
981 ("Minimum Row Precharge Time [ns]: %d.%2d = in Clk cycles %d\n",
982 leftOfPoint, rightOfPoint, trp_clocks);
984 /*------------------------------------------------------------------------------------------------------------------------------*/
986 case 28: /* Minimum Row Active to Row Active Time */
987 shift = (dimmInfo->memoryType == DDR) ? 2 : 0;
989 (dimmInfo->memoryType == DDR) ? 0xfc : 0xff;
991 (dimmInfo->memoryType == DDR) ? 0x03 : 0x00;
992 leftOfPoint = ((data[i] & maskLeftOfPoint) >> shift);
993 rightOfPoint = (data[i] & maskRightOfPoint) * 25;
995 dimmInfo->minRowActiveRowActiveDelay = ((leftOfPoint * 100) + rightOfPoint); /* measured in 100ns Intervals */
997 ("Minimum Row Active -To- Row Active Delay [ns]: %d.%2d = in Clk cycles %d\n",
998 leftOfPoint, rightOfPoint, trp_clocks);
1000 /*------------------------------------------------------------------------------------------------------------------------------*/
1002 case 29: /* Minimum Ras-To-Cas Delay */
1003 shift = (dimmInfo->memoryType == DDR) ? 2 : 0;
1005 (dimmInfo->memoryType == DDR) ? 0xfc : 0xff;
1007 (dimmInfo->memoryType == DDR) ? 0x03 : 0x00;
1008 leftOfPoint = ((data[i] & maskLeftOfPoint) >> shift);
1009 rightOfPoint = (data[i] & maskRightOfPoint) * 25;
1011 dimmInfo->minRowActiveRowActiveDelay = ((leftOfPoint * 100) + rightOfPoint); /* measured in 100ns Intervals */
1013 ("Minimum Ras-To-Cas Delay [ns]: %d.%2d = in Clk cycles %d\n",
1014 leftOfPoint, rightOfPoint, trp_clocks);
1016 /*------------------------------------------------------------------------------------------------------------------------------*/
1018 case 30: /* Minimum Ras Pulse Width */
1019 dimmInfo->minRasPulseWidth = data[i];
1021 (NSto10PS (data[i]) +
1022 (tmemclk - 1)) / tmemclk;
1024 ("Minimum Ras Pulse Width [ns]: %d = in Clk cycles %d\n",
1025 dimmInfo->minRasPulseWidth, tras_clocks);
1028 /*------------------------------------------------------------------------------------------------------------------------------*/
1030 case 31: /* Module Bank Density */
1031 dimmInfo->moduleBankDensity = data[i];
1033 ("Module Bank Density: %d\n",
1034 dimmInfo->moduleBankDensity);
1037 ("*** Offered Densities (more than 1 = Multisize-Module): ");
1039 if (dimmInfo->moduleBankDensity & 1)
1041 if (dimmInfo->moduleBankDensity & 2)
1043 if (dimmInfo->moduleBankDensity & 4)
1045 if (dimmInfo->moduleBankDensity & 8)
1047 if (dimmInfo->moduleBankDensity & 16)
1049 if (dimmInfo->moduleBankDensity & 32)
1051 if ((dimmInfo->moduleBankDensity & 64)
1052 || (dimmInfo->moduleBankDensity & 128)) {
1060 /*------------------------------------------------------------------------------------------------------------------------------*/
1062 case 32: /* Address And Command Setup Time (measured in ns/1000) */
1064 switch (dimmInfo->memoryType) {
1067 (((data[i] & 0xf0) >> 4) * 10) +
1069 leftOfPoint = time_tmp / 100;
1070 rightOfPoint = time_tmp % 100;
1073 leftOfPoint = (data[i] & 0xf0) >> 4;
1074 if (leftOfPoint > 7) {
1075 leftOfPoint = data[i] & 0x70 >> 4;
1078 rightOfPoint = (data[i] & 0x0f);
1081 dimmInfo->addrAndCommandSetupTime =
1082 (leftOfPoint * 100 + rightOfPoint) * sign;
1084 ("Address And Command Setup Time [ns]: %d.%d\n",
1085 sign * leftOfPoint, rightOfPoint);
1087 /*------------------------------------------------------------------------------------------------------------------------------*/
1089 case 33: /* Address And Command Hold Time */
1091 switch (dimmInfo->memoryType) {
1094 (((data[i] & 0xf0) >> 4) * 10) +
1096 leftOfPoint = time_tmp / 100;
1097 rightOfPoint = time_tmp % 100;
1100 leftOfPoint = (data[i] & 0xf0) >> 4;
1101 if (leftOfPoint > 7) {
1102 leftOfPoint = data[i] & 0x70 >> 4;
1105 rightOfPoint = (data[i] & 0x0f);
1108 dimmInfo->addrAndCommandHoldTime =
1109 (leftOfPoint * 100 + rightOfPoint) * sign;
1111 ("Address And Command Hold Time [ns]: %d.%d\n",
1112 sign * leftOfPoint, rightOfPoint);
1114 /*------------------------------------------------------------------------------------------------------------------------------*/
1116 case 34: /* Data Input Setup Time */
1118 switch (dimmInfo->memoryType) {
1121 (((data[i] & 0xf0) >> 4) * 10) +
1123 leftOfPoint = time_tmp / 100;
1124 rightOfPoint = time_tmp % 100;
1127 leftOfPoint = (data[i] & 0xf0) >> 4;
1128 if (leftOfPoint > 7) {
1129 leftOfPoint = data[i] & 0x70 >> 4;
1132 rightOfPoint = (data[i] & 0x0f);
1135 dimmInfo->dataInputSetupTime =
1136 (leftOfPoint * 100 + rightOfPoint) * sign;
1138 ("Data Input Setup Time [ns]: %d.%d\n",
1139 sign * leftOfPoint, rightOfPoint);
1141 /*------------------------------------------------------------------------------------------------------------------------------*/
1143 case 35: /* Data Input Hold Time */
1145 switch (dimmInfo->memoryType) {
1148 (((data[i] & 0xf0) >> 4) * 10) +
1150 leftOfPoint = time_tmp / 100;
1151 rightOfPoint = time_tmp % 100;
1154 leftOfPoint = (data[i] & 0xf0) >> 4;
1155 if (leftOfPoint > 7) {
1156 leftOfPoint = data[i] & 0x70 >> 4;
1159 rightOfPoint = (data[i] & 0x0f);
1162 dimmInfo->dataInputHoldTime =
1163 (leftOfPoint * 100 + rightOfPoint) * sign;
1165 ("Data Input Hold Time [ns]: %d.%d\n\n",
1166 sign * leftOfPoint, rightOfPoint);
1168 /*------------------------------------------------------------------------------------------------------------------------------*/
1171 /* calculating the sdram density */
1173 i < dimmInfo->numOfRowAddresses + dimmInfo->numOfColAddresses;
1175 density = density * 2;
1177 dimmInfo->deviceDensity = density * dimmInfo->numOfBanksOnEachDevice *
1178 dimmInfo->sdramWidth;
1179 dimmInfo->numberOfDevices =
1180 (dimmInfo->dataWidth / dimmInfo->sdramWidth) *
1181 dimmInfo->numOfModuleBanks;
1182 if ((dimmInfo->errorCheckType == 0x1)
1183 || (dimmInfo->errorCheckType == 0x2)
1184 || (dimmInfo->errorCheckType == 0x3)) {
1186 (dimmInfo->deviceDensity / 8) *
1187 (dimmInfo->numberOfDevices -
1188 /* ronen on the 1G dimm we get wrong value. (was devicesForErrCheck) */
1189 dimmInfo->numberOfDevices / 8);
1192 (dimmInfo->deviceDensity / 8) *
1193 dimmInfo->numberOfDevices;
1196 /* compute the module DRB size */
1198 (dimmInfo->numOfRowAddresses + dimmInfo->numOfColAddresses));
1199 tmp *= dimmInfo->numOfModuleBanks;
1200 tmp *= dimmInfo->sdramWidth;
1201 tmp = tmp >> 24; /* div by 0x4000000 (64M) */
1202 dimmInfo->drb_size = (uchar) tmp;
1203 debug("Module DRB size (n*64Mbit): %d\n", dimmInfo->drb_size);
1205 /* try a CAS latency of 3 first... */
1207 /* bit 1 is CL2, bit 2 is CL3 */
1208 supp_cal = (dimmInfo->suportedCasLatencies & 0x6) >> 1;
1212 if (NS10to10PS (data[9]) <= tmemclk)
1218 if (NS10to10PS (data[23]) <= tmemclk)
1222 debug("cal_val = %d\n", cal_val);
1224 /* bummer, did't work... */
1226 debug("Couldn't find a good CAS latency\n");
1235 /* sets up the GT properly with information passed in */
1236 int setup_sdram (AUX_MEM_DIMM_INFO * info)
1239 ulong tmp_sdram_mode = 0; /* 0x141c */
1240 ulong tmp_dunit_control_low = 0; /* 0x1404 */
1243 /* added 8/21/2003 P. Marchese */
1244 unsigned int sdram_config_reg;
1246 /* added 10/10/2003 P. Marchese */
1247 ulong sdram_chip_size;
1249 /* sanity checking */
1250 if (!info->numOfModuleBanks) {
1251 printf ("setup_sdram called with 0 banks\n");
1256 set_dfcdlInit (); /* may be its not needed */
1257 debug("Delay line set done\n");
1259 /* set SDRAM mode NOP */ /* To_do check it */
1260 GT_REG_WRITE (SDRAM_OPERATION, 0x5);
1261 while (GTREGREAD (SDRAM_OPERATION) != 0) {
1263 ("\n*** SDRAM_OPERATION 1418: Module still busy ... please wait... ***\n");
1266 /* SDRAM configuration */
1267 /* added 8/21/2003 P. Marchese */
1268 /* code allows usage of registered DIMMS */
1270 /* figure out the memory refresh internal */
1271 switch (info->RefreshInterval) {
1273 case 0x80: /* refresh period is 15.625 usec */
1275 (unsigned int) (((float) 15.625 * (float) CONFIG_SYS_BUS_CLK)
1276 / (float) 1000000.0);
1279 case 0x81: /* refresh period is 3.9 usec */
1281 (unsigned int) (((float) 3.9 * (float) CONFIG_SYS_BUS_CLK) /
1285 case 0x82: /* refresh period is 7.8 usec */
1287 (unsigned int) (((float) 7.8 * (float) CONFIG_SYS_BUS_CLK) /
1291 case 0x83: /* refresh period is 31.3 usec */
1293 (unsigned int) (((float) 31.3 * (float) CONFIG_SYS_BUS_CLK) /
1297 case 0x84: /* refresh period is 62.5 usec */
1299 (unsigned int) (((float) 62.5 * (float) CONFIG_SYS_BUS_CLK) /
1303 case 0x85: /* refresh period is 125 usec */
1305 (unsigned int) (((float) 125 * (float) CONFIG_SYS_BUS_CLK) /
1308 default: /* refresh period undefined */
1309 printf ("DRAM refresh period is unknown!\n");
1310 printf ("Aborting DRAM setup with an error\n");
1314 debug("calculated refresh interval %0x\n", sdram_config_reg);
1316 /* make sure the refresh value is only 14 bits */
1317 if (sdram_config_reg > 0x1fff)
1318 sdram_config_reg = 0x1fff;
1319 debug("adjusted refresh interval %0x\n", sdram_config_reg);
1321 /* we want physical bank interleaving and */
1322 /* virtual bank interleaving enabled so do nothing */
1323 /* since these bits need to be zero to enable the interleaving */
1325 /* registered DRAM ? */
1326 if (info->registeredAddrAndControlInputs == 1) {
1327 /* it's registered DRAM, so set the reg. DRAM bit */
1328 sdram_config_reg = sdram_config_reg | BIT17;
1329 debug("Enabling registered DRAM bit\n");
1331 /* turn on DRAM ECC? */
1332 #ifdef CONFIG_MV64460_ECC
1333 if (info->errorCheckType == 0x2) {
1334 /* DRAM has ECC, so turn it on */
1335 sdram_config_reg = sdram_config_reg | BIT18;
1336 debug("Enabling ECC\n");
1339 /* set the data DQS pin configuration */
1340 switch (info->sdramWidth) {
1341 case 0x4: /* memory is x4 */
1342 sdram_config_reg = sdram_config_reg | BIT20 | BIT21;
1343 debug("Data DQS pins set for 16 pins\n");
1345 case 0x8: /* memory is x8 or x16 */
1347 sdram_config_reg = sdram_config_reg | BIT21;
1348 debug("Data DQS pins set for 8 pins\n");
1350 case 0x20: /* memory is x32 */
1351 /* both bits are cleared for x32 so nothing to do */
1352 debug("Data DQS pins set for 2 pins\n");
1354 default: /* memory width unsupported */
1355 printf ("DRAM chip width is unknown!\n");
1356 printf ("Aborting DRAM setup with an error\n");
1362 /* perform read buffer assignments */
1363 /* we are going to use the Power-up defaults */
1364 /* bit 27 = PCI bus #0 = buffer 0 */
1365 /* bit 28 = PCI bus #1 = buffer 0 */
1366 /* bit 29 = MPSC = buffer 0 */
1367 /* bit 30 = IDMA = buffer 0 */
1368 /* bit 31 = Gigabit = buffer 0 */
1369 sdram_config_reg = sdram_config_reg | 0x58000000;
1370 sdram_config_reg = sdram_config_reg & 0xffffff00;
1371 /* bit 14 FBSplit = FCRAM controller bsplit enable. */
1372 /* bit 15 vw = FCRAM Variable write length enable. */
1373 /* bit 16 DType = Dram Type (0 = FCRAM,1 = Standard) */
1374 sdram_config_reg = sdram_config_reg | BIT14 | BIT15;
1376 /* write the value into the SDRAM configuration register */
1377 GT_REG_WRITE (SDRAM_CONFIG, sdram_config_reg);
1378 debug("sdram_conf 0x1400: %08x\n", GTREGREAD (SDRAM_CONFIG));
1380 /* SDRAM open pages control keep open as much as I can */
1381 GT_REG_WRITE (SDRAM_OPEN_PAGES_CONTROL, 0x0);
1383 ("sdram_open_pages_controll 0x1414: %08x\n",
1384 GTREGREAD (SDRAM_OPEN_PAGES_CONTROL));
1386 /* SDRAM D_UNIT_CONTROL_LOW 0x1404 */
1387 tmp = (GTREGREAD (D_UNIT_CONTROL_LOW) & 0x01); /* Clock Domain Sync from power on reset */
1389 debug("Core Signals are sync (by HW-Setting)!!!\n");
1392 ("Core Signals syncs. are bypassed (by HW-Setting)!!!\n");
1394 /* SDRAM set CAS Latency according to SPD information */
1395 switch (info->memoryType) {
1397 printf ("### SD-RAM not supported !!!\n");
1398 printf ("Aborting!!!\n");
1400 /* ToDo fill SD-RAM if needed !!!!! */
1402 /* Calculate the settings for SDRAM mode and Dunit control low registers */
1403 /* Values set according to technical bulletin TB-92 rev. c */
1405 debug("### SET-CL for DDR-RAM\n");
1406 /* ronen db64460 - change the tmp_dunit_control_low setting!!! */
1407 switch (info->maxClSupported_DDR) {
1409 tmp_sdram_mode = 0x32; /* CL=3 Burstlength = 4 */
1410 if (tmp == 1) { /* clocks sync */
1411 if (info->registeredAddrAndControlInputs == 1) /* registerd DDR SDRAM? */
1412 tmp_dunit_control_low = 0x05110051;
1414 tmp_dunit_control_low = 0x24110051;
1416 ("Max. CL is 3 CLKs 0x141c= %08lx, 0x1404 = %08lx\n",
1417 tmp_sdram_mode, tmp_dunit_control_low);
1418 printf ("Warnning: DRAM ClkSync was never tested(db64460)!!!!!\n");
1419 } else { /* clk sync. bypassed */
1421 if (info->registeredAddrAndControlInputs == 1) /* registerd DDR SDRAM? */
1422 tmp_dunit_control_low = 0xC5000540;
1424 tmp_dunit_control_low = 0xC4000540;
1426 ("Max. CL is 3 CLKs 0x141c= %08lx, 0x1404 = %08lx\n",
1427 tmp_sdram_mode, tmp_dunit_control_low);
1431 tmp_sdram_mode = 0x62; /* CL=2.5 Burstlength = 4 */
1432 if (tmp == 1) { /* clocks sync */
1433 if (info->registeredAddrAndControlInputs == 1) /* registerd DDR SDRAM? */
1434 tmp_dunit_control_low = 0x25110051;
1436 tmp_dunit_control_low = 0x24110051;
1438 ("Max. CL is 2.5 CLKs 0x141c= %08lx, 0x1404 = %08lx\n",
1439 tmp_sdram_mode, tmp_dunit_control_low);
1440 printf ("Warnning: DRAM ClkSync was never tested(db64460)!!!!!\n");
1441 } else { /* clk sync. bypassed */
1443 if (info->registeredAddrAndControlInputs == 1) { /* registerd DDR SDRAM? */
1444 tmp_dunit_control_low = 0xC5000540;
1445 /* printf("CL = 2.5, Clock Unsync'ed, Dunit Control Low register setting undefined\n");1 */
1446 /* printf("Aborting!!!\n");1 */
1449 tmp_dunit_control_low = 0xC4000540;
1451 ("Max. CL is 2.5 CLKs 0x141c= %08lx, 0x1404 = %08lx\n",
1452 tmp_sdram_mode, tmp_dunit_control_low);
1456 tmp_sdram_mode = 0x22; /* CL=2 Burstlength = 4 */
1457 if (tmp == 1) { /* clocks sync */
1458 if (info->registeredAddrAndControlInputs == 1) /* registerd DDR SDRAM? */
1459 tmp_dunit_control_low = 0x04110051;
1461 tmp_dunit_control_low = 0x03110051;
1463 ("Max. CL is 2 CLKs 0x141c= %08lx, 0x1404 = %08lx\n",
1464 tmp_sdram_mode, tmp_dunit_control_low);
1465 printf ("Warnning: DRAM ClkSync was never tested(db64460)!!!!!\n");
1466 } else { /* clk sync. bypassed */
1468 if (info->registeredAddrAndControlInputs == 1) { /* registerd DDR SDRAM? */
1469 /*printf("CL = 2, Clock Unsync'ed, Dunit Control Low register setting undefined\n");1 */
1470 /*printf("Aborting!!!\n");1 */
1472 tmp_dunit_control_low = 0xC4000540;
1474 tmp_dunit_control_low = 0xC3000540;;
1476 ("Max. CL is 2 CLKs 0x141c= %08lx, 0x1404 = %08lx\n",
1477 tmp_sdram_mode, tmp_dunit_control_low);
1481 tmp_sdram_mode = 0x52; /* CL=1.5 Burstlength = 4 */
1482 if (tmp == 1) { /* clocks sync */
1483 if (info->registeredAddrAndControlInputs == 1) /* registerd DDR SDRAM? */
1484 tmp_dunit_control_low = 0x24110051;
1486 tmp_dunit_control_low = 0x23110051;
1488 ("Max. CL is 1.5 CLKs 0x141c= %08lx, 0x1404 = %08lx\n",
1489 tmp_sdram_mode, tmp_dunit_control_low);
1490 printf ("Warnning: DRAM ClkSync was never tested(db64460)!!!!!\n");
1491 } else { /* clk sync. bypassed */
1493 if (info->registeredAddrAndControlInputs == 1) { /* registerd DDR SDRAM? */
1494 /*printf("CL = 1.5, Clock Unsync'ed, Dunit Control Low register setting undefined\n");1 */
1495 /*printf("Aborting!!!\n");1 */
1497 tmp_dunit_control_low = 0xC4000540;
1499 tmp_dunit_control_low = 0xC3000540;
1501 ("Max. CL is 1.5 CLKs 0x141c= %08lx, 0x1404 = %08lx\n",
1502 tmp_sdram_mode, tmp_dunit_control_low);
1507 printf ("Max. CL is out of range %d\n",
1508 info->maxClSupported_DDR);
1511 } /* end DDR switch */
1513 } /* end CL switch */
1515 /* Write results of CL detection procedure */
1516 /* set SDRAM mode reg. 0x141c */
1517 GT_REG_WRITE (SDRAM_MODE, tmp_sdram_mode);
1519 /* set SDRAM mode SetCommand 0x1418 */
1520 GT_REG_WRITE (SDRAM_OPERATION, 0x3);
1521 while (GTREGREAD (SDRAM_OPERATION) != 0) {
1523 ("\n*** SDRAM_OPERATION 0x1418 after SDRAM_MODE: Module still busy ... please wait... ***\n");
1526 /* SDRAM D_UNIT_CONTROL_LOW 0x1404 */
1527 GT_REG_WRITE (D_UNIT_CONTROL_LOW, tmp_dunit_control_low);
1529 /* set SDRAM mode SetCommand 0x1418 */
1530 GT_REG_WRITE (SDRAM_OPERATION, 0x3);
1531 while (GTREGREAD (SDRAM_OPERATION) != 0) {
1533 ("\n*** SDRAM_OPERATION 1418 after D_UNIT_CONTROL_LOW: Module still busy ... please wait... ***\n");
1536 /*------------------------------------------------------------------------------ */
1538 /* bank parameters */
1539 /* SDRAM address decode register 0x1410 */
1540 /* program this with the default value */
1541 tmp = 0x02; /* power-up default address select decoding value */
1543 debug("drb_size (n*64Mbit): %d\n", info->drb_size);
1544 /* figure out the DRAM chip size */
1546 (1 << (info->numOfRowAddresses + info->numOfColAddresses));
1547 sdram_chip_size *= info->sdramWidth;
1548 sdram_chip_size *= 4;
1549 debug("computed sdram chip size is %#lx\n", sdram_chip_size);
1550 /* divide sdram chip size by 64 Mbits */
1551 sdram_chip_size = sdram_chip_size / 0x4000000;
1552 switch (sdram_chip_size) {
1553 case 1: /* 64 Mbit */
1554 case 2: /* 128 Mbit */
1555 debug("RAM-Device_size 64Mbit or 128Mbit)\n");
1558 case 4: /* 256 Mbit */
1559 case 8: /* 512 Mbit */
1560 debug("RAM-Device_size 256Mbit or 512Mbit)\n");
1563 case 16: /* 1 Gbit */
1564 case 32: /* 2 Gbit */
1565 debug("RAM-Device_size 1Gbit or 2Gbit)\n");
1569 printf ("Error in dram size calculation\n");
1570 printf ("RAM-Device_size is unsupported\n");
1574 /* SDRAM address control */
1575 GT_REG_WRITE (SDRAM_ADDR_CONTROL, tmp);
1577 ("setting up sdram address control (0x1410) with: %08lx \n",
1580 /* ------------------------------------------------------------------------------ */
1581 /* same settings for registerd & non-registerd DDR SDRAM */
1583 ("setting up sdram_timing_control_low (0x1408) with: %08x \n",
1586 GT_REG_WRITE (SDRAM_TIMING_CONTROL_LOW, 0x01501220);
1589 /* ------------------------------------------------------------------------------ */
1591 /* SDRAM configuration */
1592 tmp = GTREGREAD (SDRAM_CONFIG);
1594 if (info->registeredAddrAndControlInputs
1595 || info->registeredDQMBinputs) {
1598 ("SPD says: registered Addr. and Cont.: %d; registered DQMBinputs: %d\n",
1599 info->registeredAddrAndControlInputs,
1600 info->registeredDQMBinputs);
1603 /* Use buffer 1 to return read data to the CPU
1604 * Page 426 MV6indent: Standard input:1464: Warning:old style assignment ambiguity in "=*". Assuming "= *"
1606 indent: Standard input:1465: Warning:old style assignment ambiguity in "=*". Assuming "= *"
1611 ("Before Buffer assignment - sdram_conf (0x1400): %08x\n",
1612 GTREGREAD (SDRAM_CONFIG));
1614 ("After Buffer assignment - sdram_conf (0x1400): %08x\n",
1615 GTREGREAD (SDRAM_CONFIG));
1617 /* SDRAM timing To_do: */
1618 /* ------------------------------------------------------------------------------ */
1621 ("setting up sdram_timing_control_high (0x140c) with: %08x \n",
1623 GT_REG_WRITE (SDRAM_TIMING_CONTROL_HIGH, 0xc);
1626 ("setting up sdram address pads control (0x14c0) with: %08x \n",
1628 GT_REG_WRITE (SDRAM_ADDR_CTRL_PADS_CALIBRATION, 0x7d5014a);
1631 ("setting up sdram data pads control (0x14c4) with: %08x \n",
1633 GT_REG_WRITE (SDRAM_DATA_PADS_CALIBRATION, 0x7d5014a);
1635 /* ------------------------------------------------------------------------------ */
1637 /* set the SDRAM configuration for each bank */
1639 /* for (i = info->slot * 2; i < ((info->slot * 2) + info->banks); i++) */
1643 ("\n*** Running a MRS cycle for bank %d ***\n", i);
1646 memory_map_bank (i, 0, GB / 4);
1648 /* set SDRAM mode */ /* To_do check it */
1649 GT_REG_WRITE (SDRAM_OPERATION, 0x3);
1650 check = GTREGREAD (SDRAM_OPERATION);
1652 ("\n*** SDRAM_OPERATION 1418 (0 = Normal Operation) = %08lx ***\n",
1656 /* switch back to normal operation mode */
1657 GT_REG_WRITE (SDRAM_OPERATION, 0);
1658 check = GTREGREAD (SDRAM_OPERATION);
1660 ("\n*** SDRAM_OPERATION 1418 (0 = Normal Operation) = %08lx ***\n",
1663 /* unmap the bank */
1664 memory_map_bank (i, 0, 0);
1672 * Check memory range for valid RAM. A simple memory test determines
1673 * the actually available RAM size between addresses `base' and
1674 * `base + maxsize'. Some (not all) hardware errors are detected:
1675 * - short between address lines
1676 * - short between data lines
1678 long int dram_size (long int *base, long int maxsize)
1680 volatile long int *addr, *b = base;
1681 long int cnt, val, save1, save2;
1683 #define STARTVAL (1<<20) /* start test at 1M */
1684 for (cnt = STARTVAL / sizeof (long); cnt < maxsize / sizeof (long);
1686 addr = base + cnt; /* pointer arith! */
1688 save1 = *addr; /* save contents of addr */
1689 save2 = *b; /* save contents of base */
1691 *addr = cnt; /* write cnt to addr */
1692 *b = 0; /* put null at base */
1694 /* check at base address */
1696 *addr = save1; /* restore *addr */
1697 *b = save2; /* restore *b */
1700 val = *addr; /* read *addr */
1701 val = *addr; /* read *addr */
1708 ("Found %08x at Address %08x (failure)\n",
1709 (unsigned int) val, (unsigned int) addr);
1710 /* fix boundary condition.. STARTVAL means zero */
1711 if (cnt == STARTVAL / sizeof (long))
1713 return (cnt * sizeof (long));
1719 /* ------------------------------------------------------------------------- */
1721 /* ppcboot interface function to SDRAM init - this is where all the
1722 * controlling logic happens */
1723 phys_size_t initdram (int board_type)
1725 int checkbank[4] = {[0 ... 3] = 0 };
1726 ulong realsize, total;
1727 AUX_MEM_DIMM_INFO dimmInfo1;
1728 AUX_MEM_DIMM_INFO dimmInfo2;
1730 ulong dest, memSpaceAttr;
1732 /* first, use the SPD to get info about the SDRAM/ DDRRAM */
1734 /* check the NHR bit and skip mem init if it's already done */
1735 nhr = get_hid0 () & (1 << 16);
1738 printf ("Skipping SD- DDRRAM setup due to NHR bit being set\n");
1741 check_dimm (0, &dimmInfo1);
1744 check_dimm (1, &dimmInfo2);
1746 memory_map_bank (0, 0, 0);
1747 memory_map_bank (1, 0, 0);
1748 memory_map_bank (2, 0, 0);
1749 memory_map_bank (3, 0, 0);
1751 /* ronen check correct set of DIMMS */
1752 if (dimmInfo1.numOfModuleBanks && dimmInfo2.numOfModuleBanks) {
1753 if (dimmInfo1.errorCheckType !=
1754 dimmInfo2.errorCheckType)
1755 printf ("***WARNNING***!!!! different ECC support of the DIMMS\n");
1756 if (dimmInfo1.maxClSupported_DDR !=
1757 dimmInfo2.maxClSupported_DDR)
1758 printf ("***WARNNING***!!!! different CAL setting of the DIMMS\n");
1759 if (dimmInfo1.registeredAddrAndControlInputs !=
1760 dimmInfo2.registeredAddrAndControlInputs)
1761 printf ("***WARNNING***!!!! different Registration setting of the DIMMS\n");
1764 if (dimmInfo1.numOfModuleBanks && setup_sdram (&dimmInfo1)) {
1765 printf ("Setup for DIMM1 failed.\n");
1768 if (dimmInfo2.numOfModuleBanks && setup_sdram (&dimmInfo2)) {
1769 printf ("Setup for DIMM2 failed.\n");
1772 /* set the NHR bit */
1773 set_hid0 (get_hid0 () | (1 << 16));
1775 /* next, size the SDRAM banks */
1777 realsize = total = 0;
1778 if (dimmInfo1.numOfModuleBanks > 0) {
1781 if (dimmInfo1.numOfModuleBanks > 1) {
1784 if (dimmInfo1.numOfModuleBanks > 2)
1785 printf ("Error, SPD claims DIMM1 has >2 banks\n");
1787 printf ("-- DIMM1 has %d banks\n", dimmInfo1.numOfModuleBanks);
1789 if (dimmInfo2.numOfModuleBanks > 0) {
1792 if (dimmInfo2.numOfModuleBanks > 1) {
1795 if (dimmInfo2.numOfModuleBanks > 2)
1796 printf ("Error, SPD claims DIMM2 has >2 banks\n");
1798 printf ("-- DIMM2 has %d banks\n", dimmInfo2.numOfModuleBanks);
1800 for (bank_no = 0; bank_no < CONFIG_SYS_DRAM_BANKS; bank_no++) {
1801 /* skip over banks that are not populated */
1802 if (!checkbank[bank_no])
1805 /* ronen - realsize = dram_size((long int *)total, check); */
1806 if (bank_no == 0 || bank_no == 1) {
1807 if (checkbank[1] == 1)
1808 realsize = dimmInfo1.size / 2;
1810 realsize = dimmInfo1.size;
1812 if (bank_no == 2 || bank_no == 3) {
1813 if (checkbank[3] == 1)
1814 realsize = dimmInfo2.size / 2;
1816 realsize = dimmInfo2.size;
1818 memory_map_bank (bank_no, total, realsize);
1820 /* ronen - initialize the DRAM for ECC */
1821 #ifdef CONFIG_MV64460_ECC
1822 if ((dimmInfo1.errorCheckType != 0) &&
1823 ((dimmInfo2.errorCheckType != 0)
1824 || (dimmInfo2.numOfModuleBanks == 0))) {
1825 printf ("ECC Initialization of Bank %d:", bank_no);
1826 memSpaceAttr = ((~(BIT0 << bank_no)) & 0xf) << 8;
1827 mvDmaSetMemorySpace (0, 0, memSpaceAttr, total,
1829 for (dest = total; dest < total + realsize;
1831 mvDmaTransfer (0, total, dest, _8M,
1832 BIT8 /*DMA_DTL_128BYTES */ |
1833 BIT3 /*DMA_HOLD_SOURCE_ADDR */
1836 /*DMA_BLOCK_TRANSFER_MODE */ );
1837 while (mvDmaIsChannelActive (0));
1847 switch ((GTREGREAD (0x141c) >> 4) & 0x7) {
1849 printf ("CAS Latency = 2");
1852 printf ("CAS Latency = 3");
1855 printf ("CAS Latency = 1.5");
1858 printf ("CAS Latency = 2.5");
1861 printf (" tRP = %d tRAS = %d tRCD=%d\n",
1862 ((GTREGREAD (0x1408) >> 8) & 0xf) + 1,
1863 ((GTREGREAD (0x1408) >> 20) & 0xf) + 1,
1864 ((GTREGREAD (0x1408) >> 4) & 0xf) + 1);
1866 /* Setup Ethernet DMA Adress window to DRAM Area */
1868 printf ("*** ONLY the first 256MB DRAM memory are used out of the ");
1870 printf ("Total SDRAM memory is ");
1871 /* (cause all the 4 BATS are taken) */
1876 /* ronen- add Idma functions for usage of the ecc dram init. */
1877 /*******************************************************************************
1878 * mvDmaIsChannelActive - Checks if a engine is busy.
1879 ********************************************************************************/
1880 int mvDmaIsChannelActive (int engine)
1884 data = GTREGREAD (MV64460_DMA_CHANNEL0_CONTROL + 4 * engine);
1885 if (data & BIT14 /*activity status */ ) {
1891 /*******************************************************************************
1892 * mvDmaSetMemorySpace - Set a DMA memory window for the DMA's address decoding
1894 *******************************************************************************/
1895 int mvDmaSetMemorySpace (ulong memSpace,
1896 ulong memSpaceTarget,
1897 ulong memSpaceAttr, ulong baseAddress, ulong size)
1901 /* The base address must be aligned to the size. */
1902 if (baseAddress % size != 0) {
1905 if (size >= 0x10000 /*64K */ ) {
1907 baseAddress = (baseAddress & 0xffff0000);
1908 /* Set the new attributes */
1909 GT_REG_WRITE (MV64460_DMA_BASE_ADDR_REG0 + memSpace * 8,
1910 (baseAddress | memSpaceTarget | memSpaceAttr));
1911 GT_REG_WRITE ((MV64460_DMA_SIZE_REG0 + memSpace * 8),
1912 (size - 1) & 0xffff0000);
1913 temp = GTREGREAD (MV64460_DMA_BASE_ADDR_ENABLE_REG);
1914 GT_REG_WRITE (DMA_BASE_ADDR_ENABLE_REG,
1915 (temp & ~(BIT0 << memSpace)));
1922 /*******************************************************************************
1923 * mvDmaTransfer - Transfer data from sourceAddr to destAddr on one of the 4
1925 ********************************************************************************/
1926 int mvDmaTransfer (int engine, ulong sourceAddr,
1927 ulong destAddr, ulong numOfBytes, ulong command)
1929 ulong engOffReg = 0; /* Engine Offset Register */
1931 if (numOfBytes > 0xffff) {
1932 command = command | BIT31 /*DMA_16M_DESCRIPTOR_MODE */ ;
1934 command = command | ((command >> 6) & 0x7);
1935 engOffReg = engine * 4;
1936 GT_REG_WRITE (MV64460_DMA_CHANNEL0_BYTE_COUNT + engOffReg,
1938 GT_REG_WRITE (MV64460_DMA_CHANNEL0_SOURCE_ADDR + engOffReg,
1940 GT_REG_WRITE (MV64460_DMA_CHANNEL0_DESTINATION_ADDR + engOffReg,
1943 command | BIT12 /*DMA_CHANNEL_ENABLE */ | BIT9
1944 /*DMA_NON_CHAIN_MODE */ ;
1945 /* Activate DMA engine By writting to mvDmaControlRegister */
1946 GT_REG_WRITE (MV64460_DMA_CHANNEL0_CONTROL + engOffReg, command);
1950 /****************************************************************************************
1952 * This procedure detect all Sdram types: 64, 128, 256, 512 Mbit, 1Gbit and 2Gb *
1953 * This procedure fits only the Atlantis *
1955 ***************************************************************************************/
1958 /****************************************************************************************
1959 * DFCDL initialize MV643xx Design Considerations *
1961 ***************************************************************************************/
1962 int set_dfcdlInit (void)
1964 /*ronen the dfcdl init are done by the I2C */