3 * Marvell Semiconductor <www.marvell.com>
4 * Written-by: Siddarth Gore <gores@marvell.com>
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
27 #include <asm/arch/kirkwood.h>
28 #include <asm/arch/mpp.h>
31 DECLARE_GLOBAL_DATA_PTR;
36 * default gpio configuration
37 * There are maximum 64 gpios controlled through 2 sets of registers
38 * the below configuration configures mainly initial LED status
40 kw_config_gpio(GURUPLUG_OE_VAL_LOW,
42 GURUPLUG_OE_LOW, GURUPLUG_OE_HIGH);
44 /* Multi-Purpose Pins Functionality configuration */
45 u32 kwmpp_config[] = {
53 MPP7_GPO, /* GPIO_RST */
92 MPP46_GPIO, /* M_RLED */
93 MPP47_GPIO, /* M_GLED */
94 MPP48_GPIO, /* B_RLED */
95 MPP49_GPIO, /* B_GLED */
98 kirkwood_mpp_conf(kwmpp_config);
101 * arch number of board
103 gd->bd->bi_arch_number = MACH_TYPE_GURUPLUG;
105 /* adress of boot parameters */
106 gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100;
111 #ifdef CONFIG_RESET_PHY_R
112 void mv_phy_88e1121_init(char *name)
117 if (miiphy_set_current_dev(name))
120 /* command to read PHY dev address */
121 if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) {
122 printf("Err..%s could not read PHY dev address\n",
128 * Enable RGMII delay on Tx and Rx for CPU port
129 * Ref: sec 4.7.2 of chip datasheet
131 miiphy_write(name, devadr, MV88E1121_PGADR_REG, 2);
132 miiphy_read(name, devadr, MV88E1121_MAC_CTRL2_REG, ®);
133 reg |= (MV88E1121_RGMII_RXTM_CTRL | MV88E1121_RGMII_TXTM_CTRL);
134 miiphy_write(name, devadr, MV88E1121_MAC_CTRL2_REG, reg);
135 miiphy_write(name, devadr, MV88E1121_PGADR_REG, 0);
138 miiphy_reset(name, devadr);
140 printf("88E1121 Initialized on %s\n", name);
145 /* configure and initialize both PHY's */
146 mv_phy_88e1121_init("egiga0");
147 mv_phy_88e1121_init("egiga1");
149 #endif /* CONFIG_RESET_PHY_R */