3 * Marvell Semiconductor <www.marvell.com>
4 * Written-by: Siddarth Gore <gores@marvell.com>
6 * SPDX-License-Identifier: GPL-2.0+
11 #include <asm/arch/cpu.h>
12 #include <asm/arch/soc.h>
13 #include <asm/arch/mpp.h>
16 DECLARE_GLOBAL_DATA_PTR;
18 int board_early_init_f(void)
21 * default gpio configuration
22 * There are maximum 64 gpios controlled through 2 sets of registers
23 * the below configuration configures mainly initial LED status
25 mvebu_config_gpio(GURUPLUG_OE_VAL_LOW,
27 GURUPLUG_OE_LOW, GURUPLUG_OE_HIGH);
29 /* Multi-Purpose Pins Functionality configuration */
30 static const u32 kwmpp_config[] = {
38 MPP7_GPO, /* GPIO_RST */
77 MPP46_GPIO, /* M_RLED */
78 MPP47_GPIO, /* M_GLED */
79 MPP48_GPIO, /* B_RLED */
80 MPP49_GPIO, /* B_GLED */
83 kirkwood_mpp_conf(kwmpp_config, NULL);
90 * arch number of board
92 gd->bd->bi_arch_number = MACH_TYPE_GURUPLUG;
94 /* adress of boot parameters */
95 gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
100 #ifdef CONFIG_RESET_PHY_R
101 void mv_phy_88e1121_init(char *name)
106 if (miiphy_set_current_dev(name))
109 /* command to read PHY dev address */
110 if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) {
111 printf("Err..%s could not read PHY dev address\n",
117 * Enable RGMII delay on Tx and Rx for CPU port
118 * Ref: sec 4.7.2 of chip datasheet
120 miiphy_write(name, devadr, MV88E1121_PGADR_REG, 2);
121 miiphy_read(name, devadr, MV88E1121_MAC_CTRL2_REG, ®);
122 reg |= (MV88E1121_RGMII_RXTM_CTRL | MV88E1121_RGMII_TXTM_CTRL);
123 miiphy_write(name, devadr, MV88E1121_MAC_CTRL2_REG, reg);
124 miiphy_write(name, devadr, MV88E1121_PGADR_REG, 0);
127 miiphy_reset(name, devadr);
129 printf("88E1121 Initialized on %s\n", name);
134 /* configure and initialize both PHY's */
135 mv_phy_88e1121_init("egiga0");
136 mv_phy_88e1121_init("egiga1");
138 #endif /* CONFIG_RESET_PHY_R */