3 * Net Insight <www.netinsight.net>
4 * Written-by: Simon Kagstrom <simon.kagstrom@netinsight.net>
6 * Based on sheevaplug.c:
8 * Marvell Semiconductor <www.marvell.com>
9 * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
11 * See file CREDITS for list of people who contributed to this
14 * This program is free software; you can redistribute it and/or
15 * modify it under the terms of the GNU General Public License as
16 * published by the Free Software Foundation; either version 2 of
17 * the License, or (at your option) any later version.
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, write to the Free Software
26 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
32 #include <asm/arch/kirkwood.h>
33 #include <asm/arch/mpp.h>
36 DECLARE_GLOBAL_DATA_PTR;
38 int board_early_init_f(void)
41 * default gpio configuration
42 * There are maximum 64 gpios controlled through 2 sets of registers
43 * the below configuration configures mainly initial LED status
45 kw_config_gpio(OPENRD_OE_VAL_LOW,
47 OPENRD_OE_LOW, OPENRD_OE_HIGH);
49 /* Multi-Purpose Pins Functionality configuration */
50 u32 kwmpp_config[] = {
64 MPP13_SD_CMD, /* Alt UART1_TXD */
65 MPP14_SD_D0, /* Alt UART1_RXD */
85 MPP34_GPIO, /* UART1 / SD sel */
104 kirkwood_mpp_conf(kwmpp_config);
111 * arch number of board
113 #if defined(CONFIG_BOARD_IS_OPENRD_BASE)
114 gd->bd->bi_arch_number = MACH_TYPE_OPENRD_BASE;
115 #elif defined(CONFIG_BOARD_IS_OPENRD_CLIENT)
116 gd->bd->bi_arch_number = MACH_TYPE_OPENRD_CLIENT;
117 #elif defined(CONFIG_BOARD_IS_OPENRD_ULTIMATE)
118 gd->bd->bi_arch_number = MACH_TYPE_OPENRD_ULTIMATE;
121 /* adress of boot parameters */
122 gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100;
126 #ifdef CONFIG_RESET_PHY_R
127 /* Configure and enable MV88E1116 PHY */
132 char *name = "egiga0";
134 if (miiphy_set_current_dev(name))
137 /* command to read PHY dev address */
138 if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) {
139 printf("Err..%s could not read PHY dev address\n",
145 * Enable RGMII delay on Tx and Rx for CPU port
146 * Ref: sec 4.7.2 of chip datasheet
148 miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2);
149 miiphy_read(name, devadr, MV88E1116_MAC_CTRL_REG, ®);
150 reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL);
151 miiphy_write(name, devadr, MV88E1116_MAC_CTRL_REG, reg);
152 miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0);
155 miiphy_reset(name, devadr);
157 printf("88E1116 Initialized on %s\n", name);
159 #endif /* CONFIG_RESET_PHY_R */