3 * Net Insight <www.netinsight.net>
4 * Written-by: Simon Kagstrom <simon.kagstrom@netinsight.net>
6 * Based on sheevaplug.c:
8 * Marvell Semiconductor <www.marvell.com>
9 * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
11 * SPDX-License-Identifier: GPL-2.0+
16 #include <asm/mach-types.h>
17 #include <asm/arch/cpu.h>
18 #include <asm/arch/soc.h>
19 #include <asm/arch/mpp.h>
22 DECLARE_GLOBAL_DATA_PTR;
24 int board_early_init_f(void)
27 * default gpio configuration
28 * There are maximum 64 gpios controlled through 2 sets of registers
29 * the below configuration configures mainly initial LED status
31 mvebu_config_gpio(OPENRD_OE_VAL_LOW,
33 OPENRD_OE_LOW, OPENRD_OE_HIGH);
35 /* Multi-Purpose Pins Functionality configuration */
36 static const u32 kwmpp_config[] = {
50 MPP13_SD_CMD, /* Alt UART1_TXD */
51 MPP14_SD_D0, /* Alt UART1_RXD */
71 MPP34_GPIO, /* UART1 / SD sel */
90 kirkwood_mpp_conf(kwmpp_config, NULL);
97 * arch number of board
99 #if defined(CONFIG_BOARD_IS_OPENRD_BASE)
100 gd->bd->bi_arch_number = MACH_TYPE_OPENRD_BASE;
101 #elif defined(CONFIG_BOARD_IS_OPENRD_CLIENT)
102 gd->bd->bi_arch_number = MACH_TYPE_OPENRD_CLIENT;
103 #elif defined(CONFIG_BOARD_IS_OPENRD_ULTIMATE)
104 gd->bd->bi_arch_number = MACH_TYPE_OPENRD_ULTIMATE;
107 /* adress of boot parameters */
108 gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
112 #ifdef CONFIG_RESET_PHY_R
113 /* Configure and enable MV88E1116/88E1121 PHY */
114 void mv_phy_init(char *name)
119 if (miiphy_set_current_dev(name))
122 /* command to read PHY dev address */
123 if (miiphy_read(name, 0xEE, 0xEE, (u16 *)&devadr)) {
124 printf("Err..%s could not read PHY dev address\n", __func__);
129 * Enable RGMII delay on Tx and Rx for CPU port
130 * Ref: sec 4.7.2 of chip datasheet
132 miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2);
133 miiphy_read(name, devadr, MV88E1116_MAC_CTRL_REG, ®);
134 reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL);
135 miiphy_write(name, devadr, MV88E1116_MAC_CTRL_REG, reg);
136 miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0);
139 miiphy_reset(name, devadr);
141 printf(PHY_NO" Initialized on %s\n", name);
146 mv_phy_init("egiga0");
148 #ifdef CONFIG_BOARD_IS_OPENRD_CLIENT
149 /* Kirkwood ethernet driver is written with the assumption that in case
150 * of multiple PHYs, their addresses are consecutive. But unfortunately
151 * in case of OpenRD-Client, PHY addresses are not consecutive.*/
152 miiphy_write("egiga1", 0xEE, 0xEE, 24);
155 #if defined(CONFIG_BOARD_IS_OPENRD_CLIENT) || \
156 defined(CONFIG_BOARD_IS_OPENRD_ULTIMATE)
157 /* configure and initialize both PHY's */
158 mv_phy_init("egiga1");
161 #endif /* CONFIG_RESET_PHY_R */