3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
6 * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
9 * Sergei Poselenov, Emcraft Systems, sposelenov@emcraft.com.
11 * See file CREDITS for list of people who contributed to this
14 * This program is free software; you can redistribute it and/or
15 * modify it under the terms of the GNU General Public License as
16 * published by the Free Software Foundation; either version 2 of
17 * the License, or (at your option) any later version.
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, write to the Free Software
26 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
33 #include <asm/processor.h>
38 #include "mt46v32m16.h"
40 #ifndef CONFIG_SYS_RAMBOOT
41 static void sdram_start (int hi_addr)
43 long hi_addr_bit = hi_addr ? 0x01000000 : 0;
44 long control = SDRAM_CONTROL | hi_addr_bit;
46 /* unlock mode register */
47 out_be32((void *)MPC5XXX_SDRAM_CTRL, control | 0x80000000);
48 __asm__ volatile ("sync");
50 /* precharge all banks */
51 out_be32((void *)MPC5XXX_SDRAM_CTRL, control | 0x80000002);
52 __asm__ volatile ("sync");
55 /* set mode register: extended mode */
56 out_be32((void *)MPC5XXX_SDRAM_MODE, SDRAM_EMODE);
57 __asm__ volatile ("sync");
59 /* set mode register: reset DLL */
60 out_be32((void *)MPC5XXX_SDRAM_MODE, SDRAM_MODE | 0x04000000);
61 __asm__ volatile ("sync");
64 /* precharge all banks */
65 out_be32((void *)MPC5XXX_SDRAM_CTRL, control | 0x80000002);
66 __asm__ volatile ("sync");
69 out_be32((void *)MPC5XXX_SDRAM_CTRL, control | 0x80000004);
70 __asm__ volatile ("sync");
72 /* set mode register */
73 out_be32((void *)MPC5XXX_SDRAM_MODE, SDRAM_MODE);
74 __asm__ volatile ("sync");
76 /* normal operation */
77 out_be32((void *)MPC5XXX_SDRAM_CTRL, control);
78 __asm__ volatile ("sync");
83 * ATTENTION: Although partially referenced initdram does NOT make real use
84 * use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE
85 * is something else than 0x00000000.
88 phys_size_t initdram (int board_type)
93 #ifndef CONFIG_SYS_RAMBOOT
96 /* setup SDRAM chip selects */
97 out_be32((void *)MPC5XXX_SDRAM_CS0CFG, 0x0000001e); /* 2GB at 0x0 */
98 out_be32((void *)MPC5XXX_SDRAM_CS1CFG, 0x80000000); /* disabled */
99 __asm__ volatile ("sync");
101 /* setup config registers */
102 out_be32((void *)MPC5XXX_SDRAM_CONFIG1, SDRAM_CONFIG1);
103 out_be32((void *)MPC5XXX_SDRAM_CONFIG2, SDRAM_CONFIG2);
104 __asm__ volatile ("sync");
108 out_be32((void *)MPC5XXX_CDM_PORCFG, SDRAM_TAPDELAY);
109 __asm__ volatile ("sync");
112 /* find RAM size using SDRAM CS0 only */
114 test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
116 test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
124 /* memory smaller than 1MB is impossible */
125 if (dramsize < (1 << 20)) {
129 /* set SDRAM CS0 size according to the amount of RAM found */
131 out_be32((void *)MPC5XXX_SDRAM_CS0CFG,
132 0x13 + __builtin_ffs(dramsize >> 20) - 1);
134 out_be32((void *)MPC5XXX_SDRAM_CS0CFG, 0); /* disabled */
137 #else /* CONFIG_SYS_RAMBOOT */
139 /* retrieve size of memory connected to SDRAM CS0 */
140 dramsize = in_be32((void *)MPC5XXX_SDRAM_CS0CFG) & 0xFF;
141 if (dramsize >= 0x13) {
142 dramsize = (1 << (dramsize - 0x13)) << 20;
147 #endif /* CONFIG_SYS_RAMBOOT */
150 * On MPC5200B we need to set the special configuration delay in the
151 * DDR controller. Please refer to Freescale's AN3221 "MPC5200B SDRAM
152 * Initialization and Configuration", 3.3.1 SDelay--MBAR + 0x0190:
154 * "The SDelay should be written to a value of 0x00000004. It is
155 * required to account for changes caused by normal wafer processing
160 if ((SVR_MJREV(svr) >= 2) &&
161 (PVR_MAJ(pvr) == 1) && (PVR_MIN(pvr) == 4)) {
163 out_be32((void *)MPC5XXX_SDRAM_SDELAY, 0x04);
164 __asm__ volatile ("sync");
170 int checkboard (void)
172 puts ("Board: A4M072\n");
177 static struct pci_controller hose;
179 extern void pci_mpc5xxx_init(struct pci_controller *);
181 void pci_init_board(void)
183 pci_mpc5xxx_init(&hose);
187 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
189 ft_board_setup(void *blob, bd_t *bd)
191 ft_cpu_setup(blob, bd);
195 int board_eth_init(bd_t *bis)
199 /* Initialize TSECs first */
200 if ((rv = cpu_eth_init(bis)) >= 0)
203 printf("ERROR: failed to initialize FEC.\n");
205 if ((rv = pci_eth_init(bis)) >= 0)
208 printf("ERROR: failed to initialize PCI Ethernet.\n");
213 * Miscellaneous late-boot configurations
215 * Initialize EEPROM write-protect GPIO pin.
217 int misc_init_r(void)
219 #if defined(CONFIG_SYS_EEPROM_WREN)
220 /* Enable GPIO pin */
221 setbits_be32((void *)MPC5XXX_WU_GPIO_ENABLE, CONFIG_SYS_EEPROM_WP);
222 /* Set direction, output */
223 setbits_be32((void *)MPC5XXX_WU_GPIO_DIR, CONFIG_SYS_EEPROM_WP);
224 /* De-assert write enable */
225 setbits_be32((void *)MPC5XXX_WU_GPIO_DATA_O, CONFIG_SYS_EEPROM_WP);
229 #if defined(CONFIG_SYS_EEPROM_WREN)
230 /* Input: <dev_addr> I2C address of EEPROM device to enable.
231 * <state> -1: deliver current state
234 * Returns: -1: wrong device address
235 * 0: dis-/en- able done
236 * 0/1: current state if <state> was -1.
238 int eeprom_write_enable (unsigned dev_addr, int state)
240 if (CONFIG_SYS_I2C_EEPROM_ADDR != dev_addr) {
245 /* Enable write access */
246 clrbits_be32((void *)MPC5XXX_WU_GPIO_DATA_O, CONFIG_SYS_EEPROM_WP);
250 /* Disable write access */
251 setbits_be32((void *)MPC5XXX_WU_GPIO_DATA_O, CONFIG_SYS_EEPROM_WP);
255 /* Read current status back. */
256 state = (0 == (in_be32((void *)MPC5XXX_WU_GPIO_DATA_O) &
257 CONFIG_SYS_EEPROM_WP));