2 * (C) Copyright 2007 DENX Software Engineering
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 #include <asm/bitops.h>
29 #include <fdt_support.h>
30 #ifdef CONFIG_MISC_INIT_R
33 #include "iopin.h" /* for iopin_initialize() prototype */
36 #define SCCR1_CLOCKS_EN (CLOCK_SCCR1_CFG_EN | \
37 CLOCK_SCCR1_LPC_EN | \
38 CLOCK_SCCR1_PSC_EN(CONFIG_PSC_CONSOLE) | \
39 CLOCK_SCCR1_PSCFIFO_EN | \
40 CLOCK_SCCR1_DDR_EN | \
41 CLOCK_SCCR1_FEC_EN | \
42 CLOCK_SCCR1_PCI_EN | \
45 #define SCCR2_CLOCKS_EN (CLOCK_SCCR2_MEM_EN | \
46 CLOCK_SCCR2_SPDIF_EN | \
47 CLOCK_SCCR2_DIU_EN | \
50 #define CSAW_START(start) ((start) & 0xFFFF0000)
51 #define CSAW_STOP(start, size) (((start) + (size) - 1) >> 16)
53 extern void ads5121_diu_init(void);
55 long int fixed_sdram(void);
57 int board_early_init_f (void)
59 volatile immap_t *im = (immap_t *) CFG_IMMR;
63 * Initialize Local Window for the CPLD registers access (CS2 selects
66 im->sysconf.lpcs2aw = CSAW_START(CFG_CPLD_BASE) |
67 CSAW_STOP(CFG_CPLD_BASE, CFG_CPLD_SIZE);
68 im->lpc.cs_cfg[2] = CFG_CS2_CFG;
71 * According to MPC5121e RM, configuring local access windows should
72 * be followed by a dummy read of the config register that was
73 * modified last and an isync
75 lpcaw = im->sysconf.lpcs2aw;
76 __asm__ __volatile__ ("isync");
79 * Disable Boot NOR FLASH write protect - CPLD Reg 8 NOR FLASH Control
81 * Without this the flash identification routine fails, as it needs to issue
82 * write commands in order to establish the device ID.
85 #ifdef CONFIG_ADS5121_REV2
86 *((volatile u8 *)(CFG_CPLD_BASE + 0x08)) = 0xC1;
88 if (*((u8 *)(CFG_CPLD_BASE + 0x08)) & 0x04) {
89 *((volatile u8 *)(CFG_CPLD_BASE + 0x08)) = 0xC1;
91 /* running from Backup flash */
92 *((volatile u8 *)(CFG_CPLD_BASE + 0x08)) = 0x32;
96 * Configure Flash Speed
98 *((volatile u32 *)(CFG_IMMR + LPC_OFFSET + CS0_CONFIG)) = CFG_CS0_CFG;
102 im->clk.sccr[0] = SCCR1_CLOCKS_EN;
103 im->clk.sccr[1] = SCCR2_CLOCKS_EN;
108 phys_size_t initdram (int board_type)
112 msize = fixed_sdram ();
118 * fixed sdram init -- the board doesn't use memory modules that have serial presence
119 * detect or similar mechanism for discovery of the DRAM settings
121 long int fixed_sdram (void)
123 volatile immap_t *im = (immap_t *) CFG_IMMR;
124 u32 msize = CFG_DDR_SIZE * 1024 * 1024;
125 u32 msize_log2 = __ilog2 (msize);
128 /* Initialize IO Control */
129 im->io_ctrl.regs[MEM_IDX] = IOCTRL_MUX_DDR;
131 /* Initialize DDR Local Window */
132 im->sysconf.ddrlaw.bar = CFG_DDR_BASE & 0xFFFFF000;
133 im->sysconf.ddrlaw.ar = msize_log2 - 1;
136 * According to MPC5121e RM, configuring local access windows should
137 * be followed by a dummy read of the config register that was
138 * modified last and an isync
140 i = im->sysconf.ddrlaw.ar;
141 __asm__ __volatile__ ("isync");
144 im->mddrc.ddr_sys_config = CFG_MDDRC_SYS_CFG_EN;
146 /* Initialize DDR Priority Manager */
147 im->mddrc.prioman_config1 = CFG_MDDRCGRP_PM_CFG1;
148 im->mddrc.prioman_config2 = CFG_MDDRCGRP_PM_CFG2;
149 im->mddrc.hiprio_config = CFG_MDDRCGRP_HIPRIO_CFG;
150 im->mddrc.lut_table0_main_upper = CFG_MDDRCGRP_LUT0_MU;
151 im->mddrc.lut_table0_main_lower = CFG_MDDRCGRP_LUT0_ML;
152 im->mddrc.lut_table1_main_upper = CFG_MDDRCGRP_LUT1_MU;
153 im->mddrc.lut_table1_main_lower = CFG_MDDRCGRP_LUT1_ML;
154 im->mddrc.lut_table2_main_upper = CFG_MDDRCGRP_LUT2_MU;
155 im->mddrc.lut_table2_main_lower = CFG_MDDRCGRP_LUT2_ML;
156 im->mddrc.lut_table3_main_upper = CFG_MDDRCGRP_LUT3_MU;
157 im->mddrc.lut_table3_main_lower = CFG_MDDRCGRP_LUT3_ML;
158 im->mddrc.lut_table4_main_upper = CFG_MDDRCGRP_LUT4_MU;
159 im->mddrc.lut_table4_main_lower = CFG_MDDRCGRP_LUT4_ML;
160 im->mddrc.lut_table0_alternate_upper = CFG_MDDRCGRP_LUT0_AU;
161 im->mddrc.lut_table0_alternate_lower = CFG_MDDRCGRP_LUT0_AL;
162 im->mddrc.lut_table1_alternate_upper = CFG_MDDRCGRP_LUT1_AU;
163 im->mddrc.lut_table1_alternate_lower = CFG_MDDRCGRP_LUT1_AL;
164 im->mddrc.lut_table2_alternate_upper = CFG_MDDRCGRP_LUT2_AU;
165 im->mddrc.lut_table2_alternate_lower = CFG_MDDRCGRP_LUT2_AL;
166 im->mddrc.lut_table3_alternate_upper = CFG_MDDRCGRP_LUT3_AU;
167 im->mddrc.lut_table3_alternate_lower = CFG_MDDRCGRP_LUT3_AL;
168 im->mddrc.lut_table4_alternate_upper = CFG_MDDRCGRP_LUT4_AU;
169 im->mddrc.lut_table4_alternate_lower = CFG_MDDRCGRP_LUT4_AL;
171 /* Initialize MDDRC */
172 im->mddrc.ddr_sys_config = CFG_MDDRC_SYS_CFG;
173 im->mddrc.ddr_time_config0 = CFG_MDDRC_TIME_CFG0;
174 im->mddrc.ddr_time_config1 = CFG_MDDRC_TIME_CFG1;
175 im->mddrc.ddr_time_config2 = CFG_MDDRC_TIME_CFG2;
178 for (i = 0; i < 10; i++)
179 im->mddrc.ddr_command = CFG_MICRON_NOP;
181 im->mddrc.ddr_command = CFG_MICRON_PCHG_ALL;
182 im->mddrc.ddr_command = CFG_MICRON_NOP;
183 im->mddrc.ddr_command = CFG_MICRON_RFSH;
184 im->mddrc.ddr_command = CFG_MICRON_NOP;
185 im->mddrc.ddr_command = CFG_MICRON_RFSH;
186 im->mddrc.ddr_command = CFG_MICRON_NOP;
187 im->mddrc.ddr_command = CFG_MICRON_INIT_DEV_OP;
188 im->mddrc.ddr_command = CFG_MICRON_NOP;
189 im->mddrc.ddr_command = CFG_MICRON_EM2;
190 im->mddrc.ddr_command = CFG_MICRON_NOP;
191 im->mddrc.ddr_command = CFG_MICRON_PCHG_ALL;
192 im->mddrc.ddr_command = CFG_MICRON_EM2;
193 im->mddrc.ddr_command = CFG_MICRON_EM3;
194 im->mddrc.ddr_command = CFG_MICRON_EN_DLL;
195 im->mddrc.ddr_command = CFG_MICRON_INIT_DEV_OP;
196 im->mddrc.ddr_command = CFG_MICRON_PCHG_ALL;
197 im->mddrc.ddr_command = CFG_MICRON_RFSH;
198 im->mddrc.ddr_command = CFG_MICRON_INIT_DEV_OP;
199 im->mddrc.ddr_command = CFG_MICRON_OCD_DEFAULT;
200 im->mddrc.ddr_command = CFG_MICRON_PCHG_ALL;
201 im->mddrc.ddr_command = CFG_MICRON_NOP;
204 im->mddrc.ddr_time_config0 = CFG_MDDRC_TIME_CFG0_RUN;
205 im->mddrc.ddr_sys_config = CFG_MDDRC_SYS_CFG_RUN;
210 int misc_init_r(void)
213 extern int ads5121_diu_init(void);
215 /* Using this for DIU init before the driver in linux takes over
216 * Enable the TFP410 Encoder (I2C address 0x38)
221 i2c_write(0x38, 0x08, 1, &tmp_val, sizeof(tmp_val));
222 /* Verify if enabled */
224 i2c_read(0x38, 0x08, 1, &tmp_val, sizeof(tmp_val));
225 debug("DVI Encoder Read: 0x%02lx\n", tmp_val);
228 i2c_write(0x38, 0x0A, 1, &tmp_val, sizeof(tmp_val));
229 /* Verify if enabled */
231 i2c_read(0x38, 0x0A, 1, &tmp_val, sizeof(tmp_val));
232 debug("DVI Encoder Read: 0x%02lx\n", tmp_val);
234 #ifdef CONFIG_FSL_DIU_FB
235 #if !(defined(CONFIG_VIDEO) || defined(CONFIG_CFB_CONSOLE))
243 int checkboard (void)
245 ushort brd_rev = *(vu_short *) (CFG_CPLD_BASE + 0x00);
246 uchar cpld_rev = *(vu_char *) (CFG_CPLD_BASE + 0x02);
248 printf ("Board: ADS5121 rev. 0x%04x (CPLD rev. 0x%02x)\n",
250 /* initialize function mux & slew rate IO inter alia on IO Pins */
256 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
257 void ft_board_setup(void *blob, bd_t *bd)
259 ft_cpu_setup(blob, bd);
260 fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize);
262 #endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */