git.sur5r.net Git - u-boot/blob - board/advantech/som-db5800-som-6867/som-db5800-som-6867.c

   1 /*
   2  * Copyright (C) 2016 Stefan Roese <sr@denx.de>
   3  * Copyright (C) 2016 George McCollister <george.mccollister@gmail.com>
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 #include <common.h>
   9 #include <asm/fsp/fsp_support.h>
  10
  11 /* ALC262 Verb Table - 10EC0262 */
  12 static const u32 verb_table_data13[] = {
  13         /* Pin Complex (NID 0x11) */
  14         0x01171cf0,
  15         0x01171d11,
  16         0x01171e11,
  17         0x01171f41,
  18         /* Pin Complex (NID 0x12) */
  19         0x01271cf0,
  20         0x01271d11,
  21         0x01271e11,
  22         0x01271f41,
  23         /* Pin Complex (NID 0x14) */
  24         0x01471c10,
  25         0x01471d40,
  26         0x01471e01,
  27         0x01471f01,
  28         /* Pin Complex (NID 0x15) */
  29         0x01571cf0,
  30         0x01571d11,
  31         0x01571e11,
  32         0x01571f41,
  33         /* Pin Complex (NID 0x16) */
  34         0x01671cf0,
  35         0x01671d11,
  36         0x01671e11,
  37         0x01671f41,
  38         /* Pin Complex (NID 0x18) */
  39         0x01871c20,
  40         0x01871d98,
  41         0x01871ea1,
  42         0x01871f01,
  43         /* Pin Complex (NID 0x19) */
  44         0x01971c21,
  45         0x01971d98,
  46         0x01971ea1,
  47         0x01971f02,
  48         /* Pin Complex (NID 0x1A) */
  49         0x01a71c2f,
  50         0x01a71d30,
  51         0x01a71e81,
  52         0x01a71f01,
  53         /* Pin Complex */
  54         0x01b71c1f,
  55         0x01b71d40,
  56         0x01b71e21,
  57         0x01b71f02,
  58         /* Pin Complex */
  59         0x01c71cf0,
  60         0x01c71d11,
  61         0x01c71e11,
  62         0x01c71f41,
  63         /* Pin Complex */
  64         0x01d71c01,
  65         0x01d71dc6,
  66         0x01d71e14,
  67         0x01d71f40,
  68         /* Pin Complex */
  69         0x01e71cf0,
  70         0x01e71d11,
  71         0x01e71e11,
  72         0x01e71f41,
  73         /* Pin Complex */
  74         0x01f71cf0,
  75         0x01f71d11,
  76         0x01f71e11,
  77         0x01f71f41,
  78 };
  79
  80 /*
  81  * This needs to be in ROM since if we put it in CAR, FSP init loses it when
  82  * it drops CAR.
  83  *
  84  * VerbTable: (RealTek ALC262)
  85  * Revision ID = 0xFF, support all steps
  86  * Codec Verb Table For AZALIA
  87  * Codec Address: CAd value (0/1/2)
  88  * Codec Vendor: 0x10EC0262
  89  */
  90 static const struct azalia_verb_table azalia_verb_table[] = {
  91         {
  92                 {
  93                         0x10ec0262,
  94                         0x0000,
  95                         0xff,
  96                         0x01,
  97                         0x000b,
  98                         0x0002,
  99                 },
 100                 verb_table_data13
 101         }
 102 };
 103
 104 static const struct azalia_config azalia_config = {
 105         .pme_enable = 1,
 106         .docking_supported = 1,
 107         .docking_attached = 0,
 108         .hdmi_codec_enable = 1,
 109         .azalia_v_ci_enable = 1,
 110         .rsvdbits = 0,
 111         .verb_table_num = 1,
 112         .verb_table = azalia_verb_table,
 113         .reset_wait_timer_ms = 300
 114 };
 115
 116 void update_fsp_azalia_configs(const struct azalia_config **azalia)
 117 {
 118         *azalia = &azalia_config;
 119 }
 120
 121 int board_early_init_f(void)
 122 {
 123         /*
 124          * The FSP enables the BayTrail internal legacy UART (again).
 125          * Disable it again, so that the one on the EC can be used.
 126          */
 127         setup_internal_uart(0);
 128
 129         return 0;
 130 }