2 * Copyright (C) 2009 Texas Instruments Incorporated
5 * Heiko Schocher, DENX Software Engineering, hs@denx.de.
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 #include <linux/mtd/nand.h>
28 #include <asm/arch/hardware.h>
29 #include <asm/arch/nand_defs.h>
30 #include <asm/arch/davinci_misc.h>
31 #ifdef CONFIG_DAVINCI_MMC
33 #include <asm/arch/sdmmc_defs.h>
36 DECLARE_GLOBAL_DATA_PTR;
38 #ifndef CONFIG_SPL_BUILD
41 /* dram_init must store complete ramsize in gd->ram_size */
42 gd->ram_size = get_ram_size(
43 (void *)CONFIG_SYS_SDRAM_BASE,
44 CONFIG_MAX_RAM_BANK_SIZE);
48 void dram_init_banksize(void)
50 gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
51 gd->bd->bi_dram[0].size = gd->ram_size;
54 static struct davinci_timer *timer =
55 (struct davinci_timer *)DAVINCI_TIMER3_BASE;
57 static unsigned long get_timer_val(void)
59 unsigned long now = readl(&timer->tim34);
64 static void stop_timer(void)
66 writel(0x0, &timer->tcr);
72 printf("Board: AIT CAM ENC 4XX\n");
78 gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
83 #ifdef CONFIG_DRIVER_TI_EMAC
84 int board_eth_init(bd_t *bis)
86 davinci_emac_initialize();
92 #ifdef CONFIG_NAND_DAVINCI
94 davinci_std_read_page_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
95 uint8_t *buf, int page)
97 struct nand_chip *this = mtd->priv;
98 int i, eccsize = chip->ecc.size;
99 int eccbytes = chip->ecc.bytes;
100 int eccsteps = chip->ecc.steps;
102 uint8_t *oob = chip->oob_poi;
104 chip->cmdfunc(mtd, NAND_CMD_READOOB, 0x0, page & this->pagemask);
106 chip->read_buf(mtd, oob, mtd->oobsize);
108 chip->cmdfunc(mtd, NAND_CMD_READ0, 0x0, page & this->pagemask);
111 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
114 chip->ecc.hwctl(mtd, NAND_ECC_READ);
115 chip->read_buf(mtd, p, eccsize);
116 chip->ecc.hwctl(mtd, NAND_ECC_READSYN);
118 if (chip->ecc.prepad)
119 oob += chip->ecc.prepad;
121 stat = chip->ecc.correct(mtd, p, oob, NULL);
124 mtd->ecc_stats.failed++;
126 mtd->ecc_stats.corrected += stat;
130 if (chip->ecc.postpad)
131 oob += chip->ecc.postpad;
134 /* Calculate remaining oob bytes */
135 i = mtd->oobsize - (oob - chip->oob_poi);
137 chip->read_buf(mtd, oob, i);
142 static void davinci_std_write_page_syndrome(struct mtd_info *mtd,
143 struct nand_chip *chip, const uint8_t *buf)
145 unsigned char davinci_ecc_buf[NAND_MAX_OOBSIZE];
146 struct nand_chip *this = mtd->priv;
147 int i, eccsize = chip->ecc.size;
148 int eccbytes = chip->ecc.bytes;
149 int eccsteps = chip->ecc.steps;
150 int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
152 const uint8_t *p = buf;
153 uint8_t *oob = chip->oob_poi;
155 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
156 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
157 chip->write_buf(mtd, p, eccsize);
159 /* Calculate ECC without prepad */
160 chip->ecc.calculate(mtd, p, oob + chip->ecc.prepad);
162 if (chip->ecc.prepad) {
163 offset = (chip->ecc.steps - eccsteps) * chunk;
164 memcpy(&davinci_ecc_buf[offset], oob, chip->ecc.prepad);
165 oob += chip->ecc.prepad;
168 offset = ((chip->ecc.steps - eccsteps) * chunk) +
170 memcpy(&davinci_ecc_buf[offset], oob, eccbytes);
173 if (chip->ecc.postpad) {
174 offset = ((chip->ecc.steps - eccsteps) * chunk) +
175 chip->ecc.prepad + eccbytes;
176 memcpy(&davinci_ecc_buf[offset], oob,
178 oob += chip->ecc.postpad;
183 * Write the sparebytes into the page once
184 * all eccsteps have been covered
186 for (i = 0; i < mtd->oobsize; i++)
187 writeb(davinci_ecc_buf[i], this->IO_ADDR_W);
189 /* Calculate remaining oob bytes */
190 i = mtd->oobsize - (oob - chip->oob_poi);
192 chip->write_buf(mtd, oob, i);
195 static int davinci_std_write_oob_syndrome(struct mtd_info *mtd,
196 struct nand_chip *chip, int page)
199 const uint8_t *bufpoi = chip->oob_poi;
201 pos = mtd->writesize;
203 chip->cmdfunc(mtd, NAND_CMD_SEQIN, pos, page);
205 chip->write_buf(mtd, bufpoi, mtd->oobsize);
207 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
208 status = chip->waitfunc(mtd, chip);
210 return status & NAND_STATUS_FAIL ? -1 : 0;
213 static int davinci_std_read_oob_syndrome(struct mtd_info *mtd,
214 struct nand_chip *chip, int page, int sndcmd)
216 struct nand_chip *this = mtd->priv;
217 uint8_t *buf = chip->oob_poi;
218 uint8_t *bufpoi = buf;
220 chip->cmdfunc(mtd, NAND_CMD_READOOB, 0x0, page & this->pagemask);
222 chip->read_buf(mtd, bufpoi, mtd->oobsize);
227 static void nand_dm365evm_select_chip(struct mtd_info *mtd, int chip)
229 struct nand_chip *this = mtd->priv;
230 unsigned long wbase = (unsigned long) this->IO_ADDR_W;
231 unsigned long rbase = (unsigned long) this->IO_ADDR_R;
234 __set_bit(14, &wbase);
235 __set_bit(14, &rbase);
237 __clear_bit(14, &wbase);
238 __clear_bit(14, &rbase);
240 this->IO_ADDR_W = (void *)wbase;
241 this->IO_ADDR_R = (void *)rbase;
244 int board_nand_init(struct nand_chip *nand)
246 davinci_nand_init(nand);
247 nand->select_chip = nand_dm365evm_select_chip;
252 struct nand_ecc_ctrl org_ecc;
253 static int notsaved = 1;
255 static int nand_switch_hw_func(int mode)
257 struct nand_chip *nand;
258 struct mtd_info *mtd;
260 if (nand_curr_device < 0 ||
261 nand_curr_device >= CONFIG_SYS_MAX_NAND_DEVICE ||
262 !nand_info[nand_curr_device].name) {
263 printf("Error: Can't switch hw functions," \
264 " no devices available\n");
268 mtd = &nand_info[nand_curr_device];
272 printf("switching to uboot hw functions.\n");
273 memcpy(&nand->ecc, &org_ecc, sizeof(struct nand_ecc_ctrl));
276 printf("switching to RBL hw functions.\n");
278 memcpy(&org_ecc, &nand->ecc,
279 sizeof(struct nand_ecc_ctrl));
282 nand->ecc.mode = NAND_ECC_HW_SYNDROME;
283 nand->ecc.prepad = 6;
284 nand->ecc.read_page = davinci_std_read_page_syndrome;
285 nand->ecc.write_page = davinci_std_write_page_syndrome;
286 nand->ecc.read_oob = davinci_std_read_oob_syndrome;
287 nand->ecc.write_oob = davinci_std_write_oob_syndrome;
294 static int do_switch_ecc(cmd_tbl_t *cmdtp, int flag, int argc,
299 if (strncmp(argv[1], "rbl", 2) == 0)
300 hwmode = nand_switch_hw_func(1);
301 else if (strncmp(argv[1], "uboot", 2) == 0)
302 hwmode = nand_switch_hw_func(0);
309 printf("Usage: nandrbl %s\n", cmdtp->usage);
314 nandrbl, 2, 1, do_switch_ecc,
315 "switch between rbl/uboot NAND ECC calculation algorithm",
316 "[rbl/uboot] - Switch between rbl/uboot NAND ECC algorithm"
320 #endif /* #ifdef CONFIG_NAND_DAVINCI */
322 #ifdef CONFIG_DAVINCI_MMC
323 static struct davinci_mmc mmc_sd0 = {
324 .reg_base = (struct davinci_mmc_regs *)DAVINCI_MMC_SD0_BASE,
325 .input_clk = 121500000,
326 .host_caps = MMC_MODE_4BIT,
327 .voltages = MMC_VDD_32_33 | MMC_VDD_33_34,
328 .version = MMC_CTLR_VERSION_2,
331 int board_mmc_init(bd_t *bis)
335 /* Add slot-0 to mmc subsystem */
336 err = davinci_mmc_init(bis, &mmc_sd0);
342 int board_late_init(void)
344 struct davinci_gpio *gpio = davinci_gpio_bank45;
346 /* 24MHz InputClock / 15 prediv -> 1.6 MHz timer running */
347 while (get_timer_val() < 0x186a00)
350 /* 1 sec reached -> stop timer, clear all LED */
352 clrbits_le32(&gpio->out_data, CONFIG_CAM_ENC_LED_MASK);
358 char *name = "GENERIC @ 0x00";
361 miiphy_reset(name, 0x0);
364 #else /* #ifndef CONFIG_SPL_BUILD */
365 static void cam_enc_4xx_set_all_led(void)
367 struct davinci_gpio *gpio = davinci_gpio_bank45;
369 setbits_le32(&gpio->out_data, CONFIG_CAM_ENC_LED_MASK);
373 * TIMER 0 is used for tick
375 static struct davinci_timer *timer =
376 (struct davinci_timer *)DAVINCI_TIMER3_BASE;
378 #define TIMER_LOAD_VAL 0xffffffff
379 #define TIM_CLK_DIV 16
381 static int cam_enc_4xx_timer_init(void)
383 /* We are using timer34 in unchained 32-bit mode, full speed */
384 writel(0x0, &timer->tcr);
385 writel(0x0, &timer->tgcr);
386 writel(0x06 | ((TIM_CLK_DIV - 1) << 8), &timer->tgcr);
387 writel(0x0, &timer->tim34);
388 writel(TIMER_LOAD_VAL, &timer->prd34);
389 writel(2 << 22, &timer->tcr);
393 void board_gpio_init(void)
395 struct davinci_gpio *gpio;
397 cam_enc_4xx_set_all_led();
398 cam_enc_4xx_timer_init();
399 gpio = davinci_gpio_bank01;
400 clrbits_le32(&gpio->dir, ~0xfdfffffe);
401 /* clear LED D14 = GPIO25 */
402 clrbits_le32(&gpio->out_data, 0x02000000);
403 gpio = davinci_gpio_bank23;
404 clrbits_le32(&gpio->dir, ~0x5ff0afef);
405 /* set GPIO61 to 1 -> intern UART0 as Console */
406 setbits_le32(&gpio->out_data, 0x20000000);
408 * PHY out of reset GIO 50 = 1
409 * NAND WP off GIO 51 = 1
411 setbits_le32(&gpio->out_data, 0x000c0004);
412 gpio = davinci_gpio_bank45;
413 clrbits_le32(&gpio->dir, ~(0xdb2fffff) | CONFIG_CAM_ENC_LED_MASK);
423 clrbits_le32(&gpio->out_data, CONFIG_CAM_ENC_LED_MASK);
424 gpio = davinci_gpio_bank67;
425 clrbits_le32(&gpio->dir, ~0x000007ff);
429 * functions for the post memory test.
431 int arch_memory_test_prepare(u32 *vstart, u32 *size, phys_addr_t *phys_offset)
433 *vstart = CONFIG_SYS_SDRAM_BASE;
434 *size = PHYS_SDRAM_1_SIZE;
439 void arch_memory_failure_handle(void)
441 cam_enc_4xx_set_all_led();
442 puts("mem failure\n");