2 * (C) Copyright 2005-2007
3 * Stefan Roese, DENX Software Engineering, sr@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 #include <asm/processor.h>
27 #include <spd_sdram.h>
31 void ext_bus_cntlr_init(void);
32 void configure_ppc440ep_pins(void);
33 int is_nand_selected(void);
35 #if !(defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL))
36 /*************************************************************************
38 * Bamboo has one bank onboard sdram (plus DIMM)
40 * Fixed memory is composed of :
41 * MT46V16M16TG-75 from Micron (x 2), 256Mb, 16 M x16, DDR266,
42 * 13 row add bits, 10 column add bits (but 12 row used only).
43 * ECC device: MT46V16M8TG-75 from Micron (x 1), 128Mb, x8, DDR266,
44 * 12 row add bits, 10 column add bits.
45 * Prepare a subset (only the used ones) of SPD data
47 * Note : if the ECC is enabled (SDRAM_ECC_ENABLE) the size of
48 * the corresponding bank is divided by 2 due to number of Row addresses
49 * 12 in the ECC module
51 * Assumes: 64 MB, ECC, non-registered
54 ************************************************************************/
55 const unsigned char cfg_simulate_spd_eeprom[128] = {
56 0x80, /* number of SPD bytes used: 128 */
57 0x08, /* total number bytes in SPD device = 256 */
60 0x0C, /* num Row Addr: 12 */
62 0x0D, /* num Row Addr: 13 */
64 0x09, /* numColAddr: 9 */
65 0x01, /* numBanks: 1 */
66 0x20, /* Module data width: 32 bits */
67 0x00, /* Module data width continued: +0 */
69 0x75, /* SDRAM Cycle Time (cas latency 2.5) = 7.5 ns */
70 0x00, /* SDRAM Access from clock */
72 0x02, /* ECC ON : 02 OFF : 00 */
74 0x00, /* ECC ON : 02 OFF : 00 */
76 0x82, /* refresh Rate Type: Normal (7.8us) + Self refresh */
82 0x0C, /* casBit (2,2.5) */
85 0x00, /* not registered: 0 registered : 0x02*/
87 0xA0, /* SDRAM Cycle Time (cas latency 2) = 10 ns */
89 0x00, /* SDRAM Cycle Time (cas latency 1.5) = N.A */
91 0x50, /* tRpNs = 20 ns */
93 0x50, /* tRcdNs = 20 ns */
96 0x08, /* bankSizeID: 32MB */
98 0x10, /* bankSizeID: 64MB */
200 { /* GPIO Alternate1 Alternate2 Alternate3 */
203 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_0 -> EBC_ADDR(7) DMA_REQ(2) */
204 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_1 -> EBC_ADDR(6) DMA_ACK(2) */
205 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_2 -> EBC_ADDR(5) DMA_EOT/TC(2) */
206 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_3 -> EBC_ADDR(4) DMA_REQ(3) */
207 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_4 -> EBC_ADDR(3) DMA_ACK(3) */
208 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_5 ................. */
209 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_6 -> EBC_CS_N(1) */
210 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_7 -> EBC_CS_N(2) */
211 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_8 -> EBC_CS_N(3) */
212 { GPIO0_BASE, GPIO_DIS, GPIO_ALT1 }, /* GPIO0_9 -> EBC_CS_N(4) */
213 { GPIO0_BASE, GPIO_OUT, GPIO_ALT1 }, /* GPIO0_10 -> EBC_CS_N(5) */
214 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_11 -> EBC_BUS_ERR */
215 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_12 -> ZII_p0Rxd(0) */
216 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_13 -> ZII_p0Rxd(1) */
217 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_14 -> ZII_p0Rxd(2) */
218 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_15 -> ZII_p0Rxd(3) */
219 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_16 -> ZII_p0Txd(0) */
220 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_17 -> ZII_p0Txd(1) */
221 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_18 -> ZII_p0Txd(2) */
222 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_19 -> ZII_p0Txd(3) */
223 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_20 -> ZII_p0Rx_er */
224 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_21 -> ZII_p0Rx_dv */
225 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_22 -> ZII_p0RxCrs */
226 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_23 -> ZII_p0Tx_er */
227 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_24 -> ZII_p0Tx_en */
228 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_25 -> ZII_p0Col */
229 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_26 -> USB2D_RXVALID */
230 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_27 -> EXT_EBC_REQ USB2D_RXERROR */
231 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_28 -> USB2D_TXVALID */
232 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_29 -> EBC_EXT_HDLA USB2D_PAD_SUSPNDM */
233 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_30 -> EBC_EXT_ACK USB2D_XCVRSELECT */
234 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_31 -> EBC_EXR_BUSREQ USB2D_TERMSELECT */
238 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_0 -> USB2D_OPMODE0 */
239 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_1 -> USB2D_OPMODE1 */
240 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_2 -> UART0_DCD_N UART1_DSR_CTS_N UART2_SOUT */
241 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_3 -> UART0_8PIN_DSR_N UART1_RTS_DTR_N UART2_SIN */
242 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_4 -> UART0_8PIN_CTS_N UART3_SIN */
243 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_5 -> UART0_RTS_N */
244 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_6 -> UART0_DTR_N UART1_SOUT */
245 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_7 -> UART0_RI_N UART1_SIN */
246 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_8 -> UIC_IRQ(0) */
247 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_9 -> UIC_IRQ(1) */
248 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_10 -> UIC_IRQ(2) */
249 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_11 -> UIC_IRQ(3) */
250 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_12 -> UIC_IRQ(4) DMA_ACK(1) */
251 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_13 -> UIC_IRQ(6) DMA_EOT/TC(1) */
252 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_14 -> UIC_IRQ(7) DMA_REQ(0) */
253 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_15 -> UIC_IRQ(8) DMA_ACK(0) */
254 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_16 -> UIC_IRQ(9) DMA_EOT/TC(0) */
255 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_17 -> - */
256 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_18 -> | */
257 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_19 -> | */
258 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_20 -> | */
259 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_21 -> | */
260 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_22 -> | */
261 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_23 -> \ Can be unselected thru TraceSelect Bit */
262 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_24 -> / in PowerPC440EP Chip */
263 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_25 -> | */
264 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_26 -> | */
265 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_27 -> | */
266 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_28 -> | */
267 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_29 -> | */
268 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_30 -> | */
269 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_31 -> - */
274 /*----------------------------------------------------------------------------+
275 | EBC Devices Characteristics
276 | Peripheral Bank Access Parameters - EBC0_BnAP
277 | Peripheral Bank Configuration Register - EBC0_BnCR
278 +----------------------------------------------------------------------------*/
280 #define EBC0_BNAP_SMALL_FLASH \
281 EBC0_BNAP_BME_DISABLED | \
282 EBC0_BNAP_TWT_ENCODE(6) | \
283 EBC0_BNAP_CSN_ENCODE(0) | \
284 EBC0_BNAP_OEN_ENCODE(1) | \
285 EBC0_BNAP_WBN_ENCODE(1) | \
286 EBC0_BNAP_WBF_ENCODE(3) | \
287 EBC0_BNAP_TH_ENCODE(1) | \
288 EBC0_BNAP_RE_ENABLED | \
289 EBC0_BNAP_SOR_DELAYED | \
290 EBC0_BNAP_BEM_WRITEONLY | \
291 EBC0_BNAP_PEN_DISABLED
293 #define EBC0_BNCR_SMALL_FLASH_CS0 \
294 EBC0_BNCR_BAS_ENCODE(0xFFF00000) | \
299 #define EBC0_BNCR_SMALL_FLASH_CS4 \
300 EBC0_BNCR_BAS_ENCODE(0x87F00000) | \
305 /* Large Flash or SRAM */
306 #define EBC0_BNAP_LARGE_FLASH_OR_SRAM \
307 EBC0_BNAP_BME_DISABLED | \
308 EBC0_BNAP_TWT_ENCODE(8) | \
309 EBC0_BNAP_CSN_ENCODE(0) | \
310 EBC0_BNAP_OEN_ENCODE(1) | \
311 EBC0_BNAP_WBN_ENCODE(1) | \
312 EBC0_BNAP_WBF_ENCODE(1) | \
313 EBC0_BNAP_TH_ENCODE(2) | \
314 EBC0_BNAP_SOR_DELAYED | \
316 EBC0_BNAP_PEN_DISABLED
318 #define EBC0_BNCR_LARGE_FLASH_OR_SRAM_CS0 \
319 EBC0_BNCR_BAS_ENCODE(0xFF800000) | \
325 #define EBC0_BNCR_LARGE_FLASH_OR_SRAM_CS4 \
326 EBC0_BNCR_BAS_ENCODE(0x87800000) | \
332 #define EBC0_BNAP_NVRAM_FPGA \
333 EBC0_BNAP_BME_DISABLED | \
334 EBC0_BNAP_TWT_ENCODE(9) | \
335 EBC0_BNAP_CSN_ENCODE(0) | \
336 EBC0_BNAP_OEN_ENCODE(1) | \
337 EBC0_BNAP_WBN_ENCODE(1) | \
338 EBC0_BNAP_WBF_ENCODE(0) | \
339 EBC0_BNAP_TH_ENCODE(2) | \
340 EBC0_BNAP_RE_ENABLED | \
341 EBC0_BNAP_SOR_DELAYED | \
342 EBC0_BNAP_BEM_WRITEONLY | \
343 EBC0_BNAP_PEN_DISABLED
345 #define EBC0_BNCR_NVRAM_FPGA_CS5 \
346 EBC0_BNCR_BAS_ENCODE(0x80000000) | \
352 #define EBC0_BNAP_NAND_FLASH \
353 EBC0_BNAP_BME_DISABLED | \
354 EBC0_BNAP_TWT_ENCODE(3) | \
355 EBC0_BNAP_CSN_ENCODE(0) | \
356 EBC0_BNAP_OEN_ENCODE(0) | \
357 EBC0_BNAP_WBN_ENCODE(0) | \
358 EBC0_BNAP_WBF_ENCODE(0) | \
359 EBC0_BNAP_TH_ENCODE(1) | \
360 EBC0_BNAP_RE_ENABLED | \
361 EBC0_BNAP_SOR_NOT_DELAYED | \
363 EBC0_BNAP_PEN_DISABLED
366 #define EBC0_BNCR_NAND_FLASH_CS0 0xB8400000
369 #define EBC0_BNCR_NAND_FLASH_CS1 \
370 EBC0_BNCR_BAS_ENCODE(0x90000000) | \
375 #define EBC0_BNCR_NAND_FLASH_CS2 \
376 EBC0_BNCR_BAS_ENCODE(0x94000000) | \
382 #define EBC0_BNCR_NAND_FLASH_CS3 \
383 EBC0_BNCR_BAS_ENCODE(0x94000000) | \
388 int board_early_init_f(void)
390 ext_bus_cntlr_init();
392 /*--------------------------------------------------------------------
393 * Setup the interrupt controller polarities, triggers, etc.
394 *-------------------------------------------------------------------*/
395 mtdcr(UIC0SR, 0xffffffff); /* clear all */
396 mtdcr(UIC0ER, 0x00000000); /* disable all */
397 mtdcr(UIC0CR, 0x00000009); /* ATI & UIC1 crit are critical */
398 mtdcr(UIC0PR, 0xfffffe13); /* per ref-board manual */
399 mtdcr(UIC0TR, 0x01c00008); /* per ref-board manual */
400 mtdcr(UIC0VR, 0x00000001); /* int31 highest, base=0x000 */
401 mtdcr(UIC0SR, 0xffffffff); /* clear all */
403 mtdcr(UIC1SR, 0xffffffff); /* clear all */
404 mtdcr(UIC1ER, 0x00000000); /* disable all */
405 mtdcr(UIC1CR, 0x00000000); /* all non-critical */
406 mtdcr(UIC1PR, 0xffffe0ff); /* per ref-board manual */
407 mtdcr(UIC1TR, 0x00ffc000); /* per ref-board manual */
408 mtdcr(UIC1VR, 0x00000001); /* int31 highest, base=0x000 */
409 mtdcr(UIC1SR, 0xffffffff); /* clear all */
411 /*--------------------------------------------------------------------
412 * Setup the GPIO pins
413 *-------------------------------------------------------------------*/
414 out32(GPIO0_OSRL, 0x00000400);
415 out32(GPIO0_OSRH, 0x00000000);
416 out32(GPIO0_TSRL, 0x00000400);
417 out32(GPIO0_TSRH, 0x00000000);
418 out32(GPIO0_ISR1L, 0x00000000);
419 out32(GPIO0_ISR1H, 0x00000000);
420 out32(GPIO0_ISR2L, 0x00000000);
421 out32(GPIO0_ISR2H, 0x00000000);
422 out32(GPIO0_ISR3L, 0x00000000);
423 out32(GPIO0_ISR3H, 0x00000000);
425 out32(GPIO1_OSRL, 0x0C380000);
426 out32(GPIO1_OSRH, 0x00000000);
427 out32(GPIO1_TSRL, 0x0C380000);
428 out32(GPIO1_TSRH, 0x00000000);
429 out32(GPIO1_ISR1L, 0x0FC30000);
430 out32(GPIO1_ISR1H, 0x00000000);
431 out32(GPIO1_ISR2L, 0x0C010000);
432 out32(GPIO1_ISR2H, 0x00000000);
433 out32(GPIO1_ISR3L, 0x01400000);
434 out32(GPIO1_ISR3H, 0x00000000);
436 configure_ppc440ep_pins();
443 char *s = getenv("serial#");
445 printf("Board: Bamboo - AMCC PPC440EP Evaluation Board");
456 phys_size_t initdram (int board_type)
458 #if !(defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL))
461 dram_size = spd_sdram();
465 return CONFIG_SYS_MBYTES_SDRAM << 20;
469 /*************************************************************************
472 * This routine is called just prior to registering the hose and gives
473 * the board the opportunity to check things. Returning a value of zero
474 * indicates that things are bad & PCI initialization should be aborted.
476 * Different boards may wish to customize the pci controller structure
477 * (add regions, override default access routines, etc) or perform
478 * certain pre-initialization actions.
480 ************************************************************************/
481 #if defined(CONFIG_PCI)
482 int pci_pre_init(struct pci_controller *hose)
486 /*-------------------------------------------------------------------------+
487 | Set priority for all PLB3 devices to 0.
488 | Set PLB3 arbiter to fair mode.
489 +-------------------------------------------------------------------------*/
490 mfsdr(SD0_AMP1, addr);
491 mtsdr(SD0_AMP1, (addr & 0x000000FF) | 0x0000FF00);
492 addr = mfdcr(PLB3_ACR);
493 mtdcr(PLB3_ACR, addr | 0x80000000);
495 /*-------------------------------------------------------------------------+
496 | Set priority for all PLB4 devices to 0.
497 +-------------------------------------------------------------------------*/
498 mfsdr(SD0_AMP0, addr);
499 mtsdr(SD0_AMP0, (addr & 0x000000FF) | 0x0000FF00);
500 addr = mfdcr(PLB4_ACR) | 0xa0000000; /* Was 0x8---- */
501 mtdcr(PLB4_ACR, addr);
503 /*-------------------------------------------------------------------------+
504 | Set Nebula PLB4 arbiter to fair mode.
505 +-------------------------------------------------------------------------*/
507 addr = (mfdcr(PLB0_ACR) & ~PLB0_ACR_PPM_MASK) | PLB0_ACR_PPM_FAIR;
508 addr = (addr & ~PLB0_ACR_HBU_MASK) | PLB0_ACR_HBU_ENABLED;
509 addr = (addr & ~PLB0_ACR_RDP_MASK) | PLB0_ACR_RDP_4DEEP;
510 addr = (addr & ~PLB0_ACR_WRP_MASK) | PLB0_ACR_WRP_2DEEP;
511 mtdcr(PLB0_ACR, addr);
514 addr = (mfdcr(PLB1_ACR) & ~PLB1_ACR_PPM_MASK) | PLB1_ACR_PPM_FAIR;
515 addr = (addr & ~PLB1_ACR_HBU_MASK) | PLB1_ACR_HBU_ENABLED;
516 addr = (addr & ~PLB1_ACR_RDP_MASK) | PLB1_ACR_RDP_4DEEP;
517 addr = (addr & ~PLB1_ACR_WRP_MASK) | PLB1_ACR_WRP_2DEEP;
518 mtdcr(PLB1_ACR, addr);
522 #endif /* defined(CONFIG_PCI) */
524 /*************************************************************************
527 * The bootstrap configuration provides default settings for the pci
528 * inbound map (PIM). But the bootstrap config choices are limited and
529 * may not be sufficient for a given board.
531 ************************************************************************/
532 #if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT)
533 void pci_target_init(struct pci_controller *hose)
535 /*--------------------------------------------------------------------------+
536 * Set up Direct MMIO registers
537 *--------------------------------------------------------------------------*/
538 /*--------------------------------------------------------------------------+
539 | PowerPC440 EP PCI Master configuration.
540 | Map one 1Gig range of PLB/processor addresses to PCI memory space.
541 | PLB address 0xA0000000-0xDFFFFFFF ==> PCI address 0xA0000000-0xDFFFFFFF
542 | Use byte reversed out routines to handle endianess.
543 | Make this region non-prefetchable.
544 +--------------------------------------------------------------------------*/
545 out32r(PCIL0_PMM0MA, 0x00000000); /* PMM0 Mask/Attribute - disabled b4 setting */
546 out32r(PCIL0_PMM0LA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 Local Address */
547 out32r(PCIL0_PMM0PCILA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 PCI Low Address */
548 out32r(PCIL0_PMM0PCIHA, 0x00000000); /* PMM0 PCI High Address */
549 out32r(PCIL0_PMM0MA, 0xE0000001); /* 512M + No prefetching, and enable region */
551 out32r(PCIL0_PMM1MA, 0x00000000); /* PMM0 Mask/Attribute - disabled b4 setting */
552 out32r(PCIL0_PMM1LA, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 Local Address */
553 out32r(PCIL0_PMM1PCILA, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 PCI Low Address */
554 out32r(PCIL0_PMM1PCIHA, 0x00000000); /* PMM0 PCI High Address */
555 out32r(PCIL0_PMM1MA, 0xE0000001); /* 512M + No prefetching, and enable region */
557 out32r(PCIL0_PTM1MS, 0x00000001); /* Memory Size/Attribute */
558 out32r(PCIL0_PTM1LA, 0); /* Local Addr. Reg */
559 out32r(PCIL0_PTM2MS, 0); /* Memory Size/Attribute */
560 out32r(PCIL0_PTM2LA, 0); /* Local Addr. Reg */
562 /*--------------------------------------------------------------------------+
563 * Set up Configuration registers
564 *--------------------------------------------------------------------------*/
566 /* Program the board's subsystem id/vendor id */
567 pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID,
568 CONFIG_SYS_PCI_SUBSYS_VENDORID);
569 pci_write_config_word(0, PCI_SUBSYSTEM_ID, CONFIG_SYS_PCI_SUBSYS_ID);
571 /* Configure command register as bus master */
572 pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER);
574 /* 240nS PCI clock */
575 pci_write_config_word(0, PCI_LATENCY_TIMER, 1);
577 /* No error reporting */
578 pci_write_config_word(0, PCI_ERREN, 0);
580 pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101);
583 #endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */
585 /*************************************************************************
588 ************************************************************************/
589 #if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_MASTER_INIT)
590 void pci_master_init(struct pci_controller *hose)
592 unsigned short temp_short;
594 /*--------------------------------------------------------------------------+
595 | Write the PowerPC440 EP PCI Configuration regs.
596 | Enable PowerPC440 EP to be a master on the PCI bus (PMM).
597 | Enable PowerPC440 EP to act as a PCI memory target (PTM).
598 +--------------------------------------------------------------------------*/
599 pci_read_config_word(0, PCI_COMMAND, &temp_short);
600 pci_write_config_word(0, PCI_COMMAND,
601 temp_short | PCI_COMMAND_MASTER |
604 #endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_MASTER_INIT) */
606 /*----------------------------------------------------------------------------+
607 | is_powerpc440ep_pass1.
608 +----------------------------------------------------------------------------*/
609 int is_powerpc440ep_pass1(void)
615 if (pvr == PVR_POWERPC_440EP_PASS1)
617 else if (pvr == PVR_POWERPC_440EP_PASS2)
620 printf("brdutil error 3\n");
628 /*----------------------------------------------------------------------------+
630 +----------------------------------------------------------------------------*/
631 int is_nand_selected(void)
633 #ifdef CONFIG_BAMBOO_NAND
640 /*----------------------------------------------------------------------------+
641 | config_on_ebc_cs4_is_small_flash => from EPLD
642 +----------------------------------------------------------------------------*/
643 unsigned char config_on_ebc_cs4_is_small_flash(void)
645 /* Not implemented yet => returns constant value */
649 /*----------------------------------------------------------------------------+
650 | Ext_bus_cntlr_init.
651 | Initialize the external bus controller
652 +----------------------------------------------------------------------------*/
653 void ext_bus_cntlr_init(void)
655 unsigned long sdr0_pstrp0, sdr0_sdstp1;
656 unsigned long bootstrap_settings, boot_selection, ebc_boot_size;
657 int computed_boot_device = BOOT_DEVICE_UNKNOWN;
658 unsigned long ebc0_cs0_bnap_value = 0, ebc0_cs0_bncr_value = 0;
659 unsigned long ebc0_cs1_bnap_value = 0, ebc0_cs1_bncr_value = 0;
660 unsigned long ebc0_cs2_bnap_value = 0, ebc0_cs2_bncr_value = 0;
661 unsigned long ebc0_cs3_bnap_value = 0, ebc0_cs3_bncr_value = 0;
662 unsigned long ebc0_cs4_bnap_value = 0, ebc0_cs4_bncr_value = 0;
665 /*-------------------------------------------------------------------------+
667 | PART 1 : Initialize EBC Bank 5
668 | ==============================
669 | Bank5 is always associated to the NVRAM/EPLD.
670 | It has to be initialized prior to other banks settings computation since
671 | some board registers values may be needed
673 +-------------------------------------------------------------------------*/
675 mtebc(PB5AP, EBC0_BNAP_NVRAM_FPGA);
676 mtebc(PB5CR, EBC0_BNCR_NVRAM_FPGA_CS5);
678 /*-------------------------------------------------------------------------+
680 | PART 2 : Determine which boot device was selected
681 | =========================================
683 | Read Pin Strap Register in PPC440EP
684 | In case of boot from IIC, read Serial Device Strap Register1
686 | Result can either be :
687 | - Boot from EBC 8bits => SMALL FLASH
688 | - Boot from EBC 16bits => Large Flash or SRAM
689 | - Boot from NAND Flash
692 +-------------------------------------------------------------------------*/
693 /* Read Pin Strap Register in PPC440EP */
694 mfsdr(sdr_pstrp0, sdr0_pstrp0);
695 bootstrap_settings = sdr0_pstrp0 & SDR0_PSTRP0_BOOTSTRAP_MASK;
697 /*-------------------------------------------------------------------------+
699 +-------------------------------------------------------------------------*/
700 if (is_powerpc440ep_pass1() == TRUE) {
701 switch(bootstrap_settings) {
702 case SDR0_PSTRP0_BOOTSTRAP_SETTINGS0:
703 /* Default Strap Settings 0 : CPU 400 - PLB 133 - Boot EBC 8 bit 33MHz */
704 /* Boot from Small Flash */
705 computed_boot_device = BOOT_FROM_SMALL_FLASH;
707 case SDR0_PSTRP0_BOOTSTRAP_SETTINGS1:
708 /* Default Strap Settings 1 : CPU 533 - PLB 133 - Boot PCI 66MHz */
710 computed_boot_device = BOOT_FROM_PCI;
713 case SDR0_PSTRP0_BOOTSTRAP_SETTINGS2:
714 /* Default Strap Settings 2 : CPU 500 - PLB 100 - Boot NDFC16 66MHz */
715 /* Boot from Nand Flash */
716 computed_boot_device = BOOT_FROM_NAND_FLASH0;
719 case SDR0_PSTRP0_BOOTSTRAP_SETTINGS3:
720 /* Default Strap Settings 3 : CPU 333 - PLB 133 - Boot EBC 8 bit 66MHz */
721 /* Boot from Small Flash */
722 computed_boot_device = BOOT_FROM_SMALL_FLASH;
725 case SDR0_PSTRP0_BOOTSTRAP_IIC_A8_EN:
726 case SDR0_PSTRP0_BOOTSTRAP_IIC_A4_EN:
727 /* Boot Settings in IIC EEprom address 0xA8 or 0xA4 */
728 /* Read Serial Device Strap Register1 in PPC440EP */
729 mfsdr(SDR0_SDSTP1, sdr0_sdstp1);
730 boot_selection = sdr0_sdstp1 & SDR0_SDSTP1_BOOT_SEL_MASK;
731 ebc_boot_size = sdr0_sdstp1 & SDR0_SDSTP1_EBC_ROM_BS_MASK;
733 switch(boot_selection) {
734 case SDR0_SDSTP1_BOOT_SEL_EBC:
735 switch(ebc_boot_size) {
736 case SDR0_SDSTP1_EBC_ROM_BS_16BIT:
737 computed_boot_device = BOOT_FROM_LARGE_FLASH_OR_SRAM;
739 case SDR0_SDSTP1_EBC_ROM_BS_8BIT:
740 computed_boot_device = BOOT_FROM_SMALL_FLASH;
745 case SDR0_SDSTP1_BOOT_SEL_PCI:
746 computed_boot_device = BOOT_FROM_PCI;
749 case SDR0_SDSTP1_BOOT_SEL_NDFC:
750 computed_boot_device = BOOT_FROM_NAND_FLASH0;
757 /*-------------------------------------------------------------------------+
759 +-------------------------------------------------------------------------*/
761 switch(bootstrap_settings) {
762 case SDR0_PSTRP0_BOOTSTRAP_SETTINGS0:
763 /* Default Strap Settings 0 : CPU 400 - PLB 133 - Boot EBC 8 bit 33MHz */
764 /* Boot from Small Flash */
765 computed_boot_device = BOOT_FROM_SMALL_FLASH;
767 case SDR0_PSTRP0_BOOTSTRAP_SETTINGS1:
768 /* Default Strap Settings 1 : CPU 333 - PLB 133 - Boot PCI 66MHz */
770 computed_boot_device = BOOT_FROM_PCI;
773 case SDR0_PSTRP0_BOOTSTRAP_SETTINGS2:
774 /* Default Strap Settings 2 : CPU 400 - PLB 100 - Boot NDFC16 33MHz */
775 /* Boot from Nand Flash */
776 computed_boot_device = BOOT_FROM_NAND_FLASH0;
779 case SDR0_PSTRP0_BOOTSTRAP_SETTINGS3:
780 /* Default Strap Settings 3 : CPU 400 - PLB 100 - Boot EBC 16 bit 33MHz */
781 /* Boot from Large Flash or SRAM */
782 computed_boot_device = BOOT_FROM_LARGE_FLASH_OR_SRAM;
785 case SDR0_PSTRP0_BOOTSTRAP_SETTINGS4:
786 /* Default Strap Settings 4 : CPU 333 - PLB 133 - Boot EBC 16 bit 66MHz */
787 /* Boot from Large Flash or SRAM */
788 computed_boot_device = BOOT_FROM_LARGE_FLASH_OR_SRAM;
791 case SDR0_PSTRP0_BOOTSTRAP_SETTINGS6:
792 /* Default Strap Settings 6 : CPU 400 - PLB 100 - Boot PCI 33MHz */
794 computed_boot_device = BOOT_FROM_PCI;
797 case SDR0_PSTRP0_BOOTSTRAP_IIC_A8_EN:
798 case SDR0_PSTRP0_BOOTSTRAP_IIC_A4_EN:
799 /* Default Strap Settings 5-7 */
800 /* Boot Settings in IIC EEprom address 0xA8 or 0xA4 */
801 /* Read Serial Device Strap Register1 in PPC440EP */
802 mfsdr(SDR0_SDSTP1, sdr0_sdstp1);
803 boot_selection = sdr0_sdstp1 & SDR0_SDSTP1_BOOT_SEL_MASK;
804 ebc_boot_size = sdr0_sdstp1 & SDR0_SDSTP1_EBC_ROM_BS_MASK;
806 switch(boot_selection) {
807 case SDR0_SDSTP1_BOOT_SEL_EBC:
808 switch(ebc_boot_size) {
809 case SDR0_SDSTP1_EBC_ROM_BS_16BIT:
810 computed_boot_device = BOOT_FROM_LARGE_FLASH_OR_SRAM;
812 case SDR0_SDSTP1_EBC_ROM_BS_8BIT:
813 computed_boot_device = BOOT_FROM_SMALL_FLASH;
818 case SDR0_SDSTP1_BOOT_SEL_PCI:
819 computed_boot_device = BOOT_FROM_PCI;
822 case SDR0_SDSTP1_BOOT_SEL_NDFC:
823 computed_boot_device = BOOT_FROM_NAND_FLASH0;
830 /*-------------------------------------------------------------------------+
832 | PART 3 : Compute EBC settings depending on selected boot device
833 | ====== ======================================================
835 | Resulting EBC init will be among following configurations :
837 | - Boot from EBC 8bits => boot from SMALL FLASH selected
838 | EBC-CS0 = Small Flash
839 | EBC-CS1,2,3 = NAND Flash or
840 | Exp.Slot depending on Soft Config
841 | EBC-CS4 = SRAM/Large Flash or
842 | Large Flash/SRAM depending on jumpers
843 | EBC-CS5 = NVRAM / EPLD
845 | - Boot from EBC 16bits => boot from Large Flash or SRAM selected
846 | EBC-CS0 = SRAM/Large Flash or
847 | Large Flash/SRAM depending on jumpers
848 | EBC-CS1,2,3 = NAND Flash or
849 | Exp.Slot depending on Software Configuration
850 | EBC-CS4 = Small Flash
851 | EBC-CS5 = NVRAM / EPLD
853 | - Boot from NAND Flash
854 | EBC-CS0 = NAND Flash0
855 | EBC-CS1,2,3 = NAND Flash1
856 | EBC-CS4 = SRAM/Large Flash or
857 | Large Flash/SRAM depending on jumpers
858 | EBC-CS5 = NVRAM / EPLD
862 | EBC-CS1,2,3 = NAND Flash or
863 | Exp.Slot depending on Software Configuration
864 | EBC-CS4 = SRAM/Large Flash or
865 | Large Flash/SRAM or
866 | Small Flash depending on jumpers
867 | EBC-CS5 = NVRAM / EPLD
869 +-------------------------------------------------------------------------*/
871 switch(computed_boot_device) {
872 /*------------------------------------------------------------------------- */
873 case BOOT_FROM_SMALL_FLASH:
874 /*------------------------------------------------------------------------- */
875 ebc0_cs0_bnap_value = EBC0_BNAP_SMALL_FLASH;
876 ebc0_cs0_bncr_value = EBC0_BNCR_SMALL_FLASH_CS0;
877 if ((is_nand_selected()) == TRUE) {
879 ebc0_cs1_bnap_value = EBC0_BNAP_NAND_FLASH;
880 ebc0_cs1_bncr_value = EBC0_BNCR_NAND_FLASH_CS1;
881 ebc0_cs2_bnap_value = EBC0_BNAP_NAND_FLASH;
882 ebc0_cs2_bncr_value = EBC0_BNCR_NAND_FLASH_CS2;
883 ebc0_cs3_bnap_value = 0;
884 ebc0_cs3_bncr_value = 0;
887 ebc0_cs1_bnap_value = 0;
888 ebc0_cs1_bncr_value = 0;
889 ebc0_cs2_bnap_value = 0;
890 ebc0_cs2_bncr_value = 0;
891 ebc0_cs3_bnap_value = 0;
892 ebc0_cs3_bncr_value = 0;
894 ebc0_cs4_bnap_value = EBC0_BNAP_LARGE_FLASH_OR_SRAM;
895 ebc0_cs4_bncr_value = EBC0_BNCR_LARGE_FLASH_OR_SRAM_CS4;
899 /*------------------------------------------------------------------------- */
900 case BOOT_FROM_LARGE_FLASH_OR_SRAM:
901 /*------------------------------------------------------------------------- */
902 ebc0_cs0_bnap_value = EBC0_BNAP_LARGE_FLASH_OR_SRAM;
903 ebc0_cs0_bncr_value = EBC0_BNCR_LARGE_FLASH_OR_SRAM_CS0;
904 if ((is_nand_selected()) == TRUE) {
906 ebc0_cs1_bnap_value = EBC0_BNAP_NAND_FLASH;
907 ebc0_cs1_bncr_value = EBC0_BNCR_NAND_FLASH_CS1;
908 ebc0_cs2_bnap_value = 0;
909 ebc0_cs2_bncr_value = 0;
910 ebc0_cs3_bnap_value = 0;
911 ebc0_cs3_bncr_value = 0;
914 ebc0_cs1_bnap_value = 0;
915 ebc0_cs1_bncr_value = 0;
916 ebc0_cs2_bnap_value = 0;
917 ebc0_cs2_bncr_value = 0;
918 ebc0_cs3_bnap_value = 0;
919 ebc0_cs3_bncr_value = 0;
921 ebc0_cs4_bnap_value = EBC0_BNAP_SMALL_FLASH;
922 ebc0_cs4_bncr_value = EBC0_BNCR_SMALL_FLASH_CS4;
926 /*------------------------------------------------------------------------- */
927 case BOOT_FROM_NAND_FLASH0:
928 /*------------------------------------------------------------------------- */
929 ebc0_cs0_bnap_value = EBC0_BNAP_NAND_FLASH;
930 ebc0_cs0_bncr_value = EBC0_BNCR_NAND_FLASH_CS1;
932 ebc0_cs1_bnap_value = 0;
933 ebc0_cs1_bncr_value = 0;
934 ebc0_cs2_bnap_value = 0;
935 ebc0_cs2_bncr_value = 0;
936 ebc0_cs3_bnap_value = 0;
937 ebc0_cs3_bncr_value = 0;
939 /* Large Flash or SRAM */
940 ebc0_cs4_bnap_value = EBC0_BNAP_LARGE_FLASH_OR_SRAM;
941 ebc0_cs4_bncr_value = EBC0_BNCR_LARGE_FLASH_OR_SRAM_CS4;
945 /*------------------------------------------------------------------------- */
947 /*------------------------------------------------------------------------- */
948 ebc0_cs0_bnap_value = 0;
949 ebc0_cs0_bncr_value = 0;
951 if ((is_nand_selected()) == TRUE) {
953 ebc0_cs1_bnap_value = EBC0_BNAP_NAND_FLASH;
954 ebc0_cs1_bncr_value = EBC0_BNCR_NAND_FLASH_CS1;
955 ebc0_cs2_bnap_value = 0;
956 ebc0_cs2_bncr_value = 0;
957 ebc0_cs3_bnap_value = 0;
958 ebc0_cs3_bncr_value = 0;
961 ebc0_cs1_bnap_value = 0;
962 ebc0_cs1_bncr_value = 0;
963 ebc0_cs2_bnap_value = 0;
964 ebc0_cs2_bncr_value = 0;
965 ebc0_cs3_bnap_value = 0;
966 ebc0_cs3_bncr_value = 0;
969 if ((config_on_ebc_cs4_is_small_flash()) == TRUE) {
971 ebc0_cs4_bnap_value = EBC0_BNAP_SMALL_FLASH;
972 ebc0_cs4_bncr_value = EBC0_BNCR_SMALL_FLASH_CS4;
974 /* Large Flash or SRAM */
975 ebc0_cs4_bnap_value = EBC0_BNAP_LARGE_FLASH_OR_SRAM;
976 ebc0_cs4_bncr_value = EBC0_BNCR_LARGE_FLASH_OR_SRAM_CS4;
981 /*------------------------------------------------------------------------- */
982 case BOOT_DEVICE_UNKNOWN:
983 /*------------------------------------------------------------------------- */
990 /*-------------------------------------------------------------------------+
991 | Initialize EBC CONFIG
992 +-------------------------------------------------------------------------*/
993 mtdcr(EBC0_CFGADDR, EBC0_CFG);
994 mtdcr(EBC0_CFGDATA, EBC0_CFG_EBTC_DRIVEN |
995 EBC0_CFG_PTD_ENABLED |
996 EBC0_CFG_RTC_2048PERCLK |
999 EBC0_CFG_CSTC_DRIVEN |
1000 EBC0_CFG_BPF_ONEDW |
1002 EBC0_CFG_PME_DISABLED |
1003 EBC0_CFG_PMT_ENCODE(0) );
1005 /*-------------------------------------------------------------------------+
1006 | Initialize EBC Bank 0-4
1007 +-------------------------------------------------------------------------*/
1009 mtebc(PB0AP, ebc0_cs0_bnap_value);
1010 mtebc(PB0CR, ebc0_cs0_bncr_value);
1012 mtebc(PB1AP, ebc0_cs1_bnap_value);
1013 mtebc(PB1CR, ebc0_cs1_bncr_value);
1015 mtebc(PB2AP, ebc0_cs2_bnap_value);
1016 mtebc(PB2CR, ebc0_cs2_bncr_value);
1018 mtebc(PB3AP, ebc0_cs3_bnap_value);
1019 mtebc(PB3CR, ebc0_cs3_bncr_value);
1021 mtebc(PB4AP, ebc0_cs4_bnap_value);
1022 mtebc(PB4CR, ebc0_cs4_bncr_value);
1028 /*----------------------------------------------------------------------------+
1029 | get_uart_configuration.
1030 +----------------------------------------------------------------------------*/
1031 uart_config_nb_t get_uart_configuration(void)
1036 /*----------------------------------------------------------------------------+
1037 | set_phy_configuration_through_fpga => to EPLD
1038 +----------------------------------------------------------------------------*/
1039 void set_phy_configuration_through_fpga(zmii_config_t config)
1042 unsigned long fpga_selection_reg;
1044 fpga_selection_reg = in8(FPGA_SELECTION_1_REG) & ~FPGA_SEL_1_REG_PHY_MASK;
1048 case ZMII_CONFIGURATION_IS_MII:
1049 fpga_selection_reg = fpga_selection_reg | FPGA_SEL_1_REG_MII;
1051 case ZMII_CONFIGURATION_IS_RMII:
1052 fpga_selection_reg = fpga_selection_reg | FPGA_SEL_1_REG_RMII;
1054 case ZMII_CONFIGURATION_IS_SMII:
1055 fpga_selection_reg = fpga_selection_reg | FPGA_SEL_1_REG_SMII;
1057 case ZMII_CONFIGURATION_UNKNOWN:
1061 out8(FPGA_SELECTION_1_REG,fpga_selection_reg);
1065 /*----------------------------------------------------------------------------+
1066 | scp_selection_in_fpga.
1067 +----------------------------------------------------------------------------*/
1068 void scp_selection_in_fpga(void)
1070 unsigned long fpga_selection_2_reg;
1072 fpga_selection_2_reg = in8(FPGA_SELECTION_2_REG) & ~FPGA_SEL2_REG_IIC1_SCP_SEL_MASK;
1073 fpga_selection_2_reg |= FPGA_SEL2_REG_SEL_SCP;
1074 out8(FPGA_SELECTION_2_REG,fpga_selection_2_reg);
1077 /*----------------------------------------------------------------------------+
1078 | iic1_selection_in_fpga.
1079 +----------------------------------------------------------------------------*/
1080 void iic1_selection_in_fpga(void)
1082 unsigned long fpga_selection_2_reg;
1084 fpga_selection_2_reg = in8(FPGA_SELECTION_2_REG) & ~FPGA_SEL2_REG_IIC1_SCP_SEL_MASK;
1085 fpga_selection_2_reg |= FPGA_SEL2_REG_SEL_IIC1;
1086 out8(FPGA_SELECTION_2_REG,fpga_selection_2_reg);
1089 /*----------------------------------------------------------------------------+
1090 | dma_a_b_selection_in_fpga.
1091 +----------------------------------------------------------------------------*/
1092 void dma_a_b_selection_in_fpga(void)
1094 unsigned long fpga_selection_2_reg;
1096 fpga_selection_2_reg = in8(FPGA_SELECTION_2_REG) | FPGA_SEL2_REG_SEL_DMA_A_B;
1097 out8(FPGA_SELECTION_2_REG,fpga_selection_2_reg);
1100 /*----------------------------------------------------------------------------+
1101 | dma_a_b_unselect_in_fpga.
1102 +----------------------------------------------------------------------------*/
1103 void dma_a_b_unselect_in_fpga(void)
1105 unsigned long fpga_selection_2_reg;
1107 fpga_selection_2_reg = in8(FPGA_SELECTION_2_REG) & ~FPGA_SEL2_REG_SEL_DMA_A_B;
1108 out8(FPGA_SELECTION_2_REG,fpga_selection_2_reg);
1111 /*----------------------------------------------------------------------------+
1112 | dma_c_d_selection_in_fpga.
1113 +----------------------------------------------------------------------------*/
1114 void dma_c_d_selection_in_fpga(void)
1116 unsigned long fpga_selection_2_reg;
1118 fpga_selection_2_reg = in8(FPGA_SELECTION_2_REG) | FPGA_SEL2_REG_SEL_DMA_C_D;
1119 out8(FPGA_SELECTION_2_REG,fpga_selection_2_reg);
1122 /*----------------------------------------------------------------------------+
1123 | dma_c_d_unselect_in_fpga.
1124 +----------------------------------------------------------------------------*/
1125 void dma_c_d_unselect_in_fpga(void)
1127 unsigned long fpga_selection_2_reg;
1129 fpga_selection_2_reg = in8(FPGA_SELECTION_2_REG) & ~FPGA_SEL2_REG_SEL_DMA_C_D;
1130 out8(FPGA_SELECTION_2_REG,fpga_selection_2_reg);
1133 /*----------------------------------------------------------------------------+
1134 | usb2_device_selection_in_fpga.
1135 +----------------------------------------------------------------------------*/
1136 void usb2_device_selection_in_fpga(void)
1138 unsigned long fpga_selection_1_reg;
1140 fpga_selection_1_reg = in8(FPGA_SELECTION_1_REG) | FPGA_SEL_1_REG_USB2_DEV_SEL;
1141 out8(FPGA_SELECTION_1_REG,fpga_selection_1_reg);
1144 /*----------------------------------------------------------------------------+
1145 | usb2_device_reset_through_fpga.
1146 +----------------------------------------------------------------------------*/
1147 void usb2_device_reset_through_fpga(void)
1149 /* Perform soft Reset pulse */
1150 unsigned long fpga_reset_reg;
1153 fpga_reset_reg = in8(FPGA_RESET_REG);
1154 out8(FPGA_RESET_REG,fpga_reset_reg | FPGA_RESET_REG_RESET_USB20_DEV);
1155 for (i=0; i<500; i++)
1157 out8(FPGA_RESET_REG,fpga_reset_reg);
1160 /*----------------------------------------------------------------------------+
1161 | usb2_host_selection_in_fpga.
1162 +----------------------------------------------------------------------------*/
1163 void usb2_host_selection_in_fpga(void)
1165 unsigned long fpga_selection_1_reg;
1167 fpga_selection_1_reg = in8(FPGA_SELECTION_1_REG) | FPGA_SEL_1_REG_USB2_HOST_SEL;
1168 out8(FPGA_SELECTION_1_REG,fpga_selection_1_reg);
1171 /*----------------------------------------------------------------------------+
1172 | ndfc_selection_in_fpga.
1173 +----------------------------------------------------------------------------*/
1174 void ndfc_selection_in_fpga(void)
1176 unsigned long fpga_selection_1_reg;
1178 fpga_selection_1_reg = in8(FPGA_SELECTION_1_REG) &~FPGA_SEL_1_REG_NF_SELEC_MASK;
1179 fpga_selection_1_reg |= FPGA_SEL_1_REG_NF0_SEL_BY_NFCS1;
1180 fpga_selection_1_reg |= FPGA_SEL_1_REG_NF1_SEL_BY_NFCS2;
1181 out8(FPGA_SELECTION_1_REG,fpga_selection_1_reg);
1184 /*----------------------------------------------------------------------------+
1185 | uart_selection_in_fpga.
1186 +----------------------------------------------------------------------------*/
1187 void uart_selection_in_fpga(uart_config_nb_t uart_config)
1190 unsigned char fpga_selection_3_reg;
1192 /* Read FPGA Reagister */
1193 fpga_selection_3_reg = in8(FPGA_SELECTION_3_REG);
1195 switch (uart_config)
1198 /* ----------------------------------------------------------------------- */
1199 /* L1 configuration: UART0 = 8 pins */
1200 /* ----------------------------------------------------------------------- */
1201 /* Configure FPGA */
1202 fpga_selection_3_reg = fpga_selection_3_reg & ~FPGA_SEL3_REG_SEL_UART_CONFIG_MASK;
1203 fpga_selection_3_reg = fpga_selection_3_reg | FPGA_SEL3_REG_SEL_UART_CONFIG1;
1204 out8(FPGA_SELECTION_3_REG, fpga_selection_3_reg);
1209 /* ----------------------------------------------------------------------- */
1210 /* L2 configuration: UART0 = 4 pins */
1211 /* UART1 = 4 pins */
1212 /* ----------------------------------------------------------------------- */
1213 /* Configure FPGA */
1214 fpga_selection_3_reg = fpga_selection_3_reg & ~FPGA_SEL3_REG_SEL_UART_CONFIG_MASK;
1215 fpga_selection_3_reg = fpga_selection_3_reg | FPGA_SEL3_REG_SEL_UART_CONFIG2;
1216 out8(FPGA_SELECTION_3_REG, fpga_selection_3_reg);
1221 /* ----------------------------------------------------------------------- */
1222 /* L3 configuration: UART0 = 4 pins */
1223 /* UART1 = 2 pins */
1224 /* UART2 = 2 pins */
1225 /* ----------------------------------------------------------------------- */
1226 /* Configure FPGA */
1227 fpga_selection_3_reg = fpga_selection_3_reg & ~FPGA_SEL3_REG_SEL_UART_CONFIG_MASK;
1228 fpga_selection_3_reg = fpga_selection_3_reg | FPGA_SEL3_REG_SEL_UART_CONFIG3;
1229 out8(FPGA_SELECTION_3_REG, fpga_selection_3_reg);
1233 /* Configure FPGA */
1234 fpga_selection_3_reg = fpga_selection_3_reg & ~FPGA_SEL3_REG_SEL_UART_CONFIG_MASK;
1235 fpga_selection_3_reg = fpga_selection_3_reg | FPGA_SEL3_REG_SEL_UART_CONFIG4;
1236 out8(FPGA_SELECTION_3_REG, fpga_selection_3_reg);
1241 /* Unsupported UART configuration number */
1250 /*----------------------------------------------------------------------------+
1252 +----------------------------------------------------------------------------*/
1253 void init_default_gpio(gpio_param_s (*gpio_tab)[GPIO_MAX])
1258 for(i=0; i<GPIO_MAX; i++)
1260 gpio_tab[GPIO0][i].add = GPIO0_BASE;
1261 gpio_tab[GPIO0][i].in_out = GPIO_DIS;
1262 gpio_tab[GPIO0][i].alt_nb = GPIO_SEL;
1266 for(i=0; i<GPIO_MAX; i++)
1268 gpio_tab[GPIO1][i].add = GPIO1_BASE;
1269 gpio_tab[GPIO1][i].in_out = GPIO_DIS;
1270 gpio_tab[GPIO1][i].alt_nb = GPIO_SEL;
1273 /* EBC_CS_N(5) - GPIO0_10 */
1274 gpio_tab[GPIO0][10].in_out = GPIO_OUT;
1275 gpio_tab[GPIO0][10].alt_nb = GPIO_ALT1;
1277 /* EBC_CS_N(4) - GPIO0_9 */
1278 gpio_tab[GPIO0][9].in_out = GPIO_OUT;
1279 gpio_tab[GPIO0][9].alt_nb = GPIO_ALT1;
1282 /*----------------------------------------------------------------------------+
1284 +------------------------------------------------------------------------------
1286 | Set UART Configuration in PowerPC440EP
1288 | +---------------------------------------------------------------------+
1289 | | Configuartion | Connector | Nb of pins | Pins | Associated |
1290 | | Number | Port Name | available | naming | CORE |
1291 | +-----------------+---------------+------------+--------+-------------+
1292 | | L1 | Port_A | 8 | UART | UART core 0 |
1293 | +-----------------+---------------+------------+--------+-------------+
1294 | | L2 | Port_A | 4 | UART1 | UART core 0 |
1295 | | (L2D) | Port_B | 4 | UART2 | UART core 1 |
1296 | +-----------------+---------------+------------+--------+-------------+
1297 | | L3 | Port_A | 4 | UART1 | UART core 0 |
1298 | | (L3D) | Port_B | 2 | UART2 | UART core 1 |
1299 | | | Port_C | 2 | UART3 | UART core 2 |
1300 | +-----------------+---------------+------------+--------+-------------+
1301 | | | Port_A | 2 | UART1 | UART core 0 |
1302 | | L4 | Port_B | 2 | UART2 | UART core 1 |
1303 | | (L4D) | Port_C | 2 | UART3 | UART core 2 |
1304 | | | Port_D | 2 | UART4 | UART core 3 |
1305 | +-----------------+---------------+------------+--------+-------------+
1309 | +------------------------------------------------------------------------------+
1310 | | GPIO | Aternate 1 | I/O | Alternate 2 | I/O | Alternate 3 | I/O |
1311 | +---------+------------------+-----+-----------------+-----+-------------+-----+
1312 | | GPIO1_2 | UART0_DCD_N | I | UART1_DSR_CTS_N | I | UART2_SOUT | O |
1313 | | GPIO1_3 | UART0_8PIN_DSR_N | I | UART1_RTS_DTR_N | O | UART2_SIN | I |
1314 | | GPIO1_4 | UART0_8PIN_CTS_N | I | NA | NA | UART3_SIN | I |
1315 | | GPIO1_5 | UART0_RTS_N | O | NA | NA | UART3_SOUT | O |
1316 | | GPIO1_6 | UART0_DTR_N | O | UART1_SOUT | O | NA | NA |
1317 | | GPIO1_7 | UART0_RI_N | I | UART1_SIN | I | NA | NA |
1318 | +------------------------------------------------------------------------------+
1321 +----------------------------------------------------------------------------*/
1323 void update_uart_ios(uart_config_nb_t uart_config, gpio_param_s (*gpio_tab)[GPIO_MAX])
1325 switch (uart_config)
1328 /* ----------------------------------------------------------------------- */
1329 /* L1 configuration: UART0 = 8 pins */
1330 /* ----------------------------------------------------------------------- */
1331 /* Update GPIO Configuration Table */
1332 gpio_tab[GPIO1][2].in_out = GPIO_IN;
1333 gpio_tab[GPIO1][2].alt_nb = GPIO_ALT1;
1335 gpio_tab[GPIO1][3].in_out = GPIO_IN;
1336 gpio_tab[GPIO1][3].alt_nb = GPIO_ALT1;
1338 gpio_tab[GPIO1][4].in_out = GPIO_IN;
1339 gpio_tab[GPIO1][4].alt_nb = GPIO_ALT1;
1341 gpio_tab[GPIO1][5].in_out = GPIO_OUT;
1342 gpio_tab[GPIO1][5].alt_nb = GPIO_ALT1;
1344 gpio_tab[GPIO1][6].in_out = GPIO_OUT;
1345 gpio_tab[GPIO1][6].alt_nb = GPIO_ALT1;
1347 gpio_tab[GPIO1][7].in_out = GPIO_IN;
1348 gpio_tab[GPIO1][7].alt_nb = GPIO_ALT1;
1353 /* ----------------------------------------------------------------------- */
1354 /* L2 configuration: UART0 = 4 pins */
1355 /* UART1 = 4 pins */
1356 /* ----------------------------------------------------------------------- */
1357 /* Update GPIO Configuration Table */
1358 gpio_tab[GPIO1][2].in_out = GPIO_IN;
1359 gpio_tab[GPIO1][2].alt_nb = GPIO_ALT2;
1361 gpio_tab[GPIO1][3].in_out = GPIO_OUT;
1362 gpio_tab[GPIO1][3].alt_nb = GPIO_ALT2;
1364 gpio_tab[GPIO1][4].in_out = GPIO_IN;
1365 gpio_tab[GPIO1][4].alt_nb = GPIO_ALT1;
1367 gpio_tab[GPIO1][5].in_out = GPIO_OUT;
1368 gpio_tab[GPIO1][5].alt_nb = GPIO_ALT1;
1370 gpio_tab[GPIO1][6].in_out = GPIO_OUT;
1371 gpio_tab[GPIO1][6].alt_nb = GPIO_ALT2;
1373 gpio_tab[GPIO1][7].in_out = GPIO_IN;
1374 gpio_tab[GPIO1][7].alt_nb = GPIO_ALT2;
1379 /* ----------------------------------------------------------------------- */
1380 /* L3 configuration: UART0 = 4 pins */
1381 /* UART1 = 2 pins */
1382 /* UART2 = 2 pins */
1383 /* ----------------------------------------------------------------------- */
1384 /* Update GPIO Configuration Table */
1385 gpio_tab[GPIO1][2].in_out = GPIO_OUT;
1386 gpio_tab[GPIO1][2].alt_nb = GPIO_ALT3;
1388 gpio_tab[GPIO1][3].in_out = GPIO_IN;
1389 gpio_tab[GPIO1][3].alt_nb = GPIO_ALT3;
1391 gpio_tab[GPIO1][4].in_out = GPIO_IN;
1392 gpio_tab[GPIO1][4].alt_nb = GPIO_ALT1;
1394 gpio_tab[GPIO1][5].in_out = GPIO_OUT;
1395 gpio_tab[GPIO1][5].alt_nb = GPIO_ALT1;
1397 gpio_tab[GPIO1][6].in_out = GPIO_OUT;
1398 gpio_tab[GPIO1][6].alt_nb = GPIO_ALT2;
1400 gpio_tab[GPIO1][7].in_out = GPIO_IN;
1401 gpio_tab[GPIO1][7].alt_nb = GPIO_ALT2;
1406 /* ----------------------------------------------------------------------- */
1407 /* L4 configuration: UART0 = 2 pins */
1408 /* UART1 = 2 pins */
1409 /* UART2 = 2 pins */
1410 /* UART3 = 2 pins */
1411 /* ----------------------------------------------------------------------- */
1412 /* Update GPIO Configuration Table */
1413 gpio_tab[GPIO1][2].in_out = GPIO_OUT;
1414 gpio_tab[GPIO1][2].alt_nb = GPIO_ALT3;
1416 gpio_tab[GPIO1][3].in_out = GPIO_IN;
1417 gpio_tab[GPIO1][3].alt_nb = GPIO_ALT3;
1419 gpio_tab[GPIO1][4].in_out = GPIO_IN;
1420 gpio_tab[GPIO1][4].alt_nb = GPIO_ALT3;
1422 gpio_tab[GPIO1][5].in_out = GPIO_OUT;
1423 gpio_tab[GPIO1][5].alt_nb = GPIO_ALT3;
1425 gpio_tab[GPIO1][6].in_out = GPIO_OUT;
1426 gpio_tab[GPIO1][6].alt_nb = GPIO_ALT2;
1428 gpio_tab[GPIO1][7].in_out = GPIO_IN;
1429 gpio_tab[GPIO1][7].alt_nb = GPIO_ALT2;
1434 /* Unsupported UART configuration number */
1435 printf("ERROR - Unsupported UART configuration number.\n\n");
1442 /* Set input Selection Register on Alt_Receive for UART Input Core */
1443 out32(GPIO1_IS1L, (in32(GPIO1_IS1L) | 0x0FC30000));
1444 out32(GPIO1_IS2L, (in32(GPIO1_IS2L) | 0x0C030000));
1445 out32(GPIO1_IS3L, (in32(GPIO1_IS3L) | 0x03C00000));
1448 /*----------------------------------------------------------------------------+
1449 | update_ndfc_ios(void).
1450 +----------------------------------------------------------------------------*/
1451 void update_ndfc_ios(gpio_param_s (*gpio_tab)[GPIO_MAX])
1453 /* Update GPIO Configuration Table */
1454 gpio_tab[GPIO0][6].in_out = GPIO_OUT; /* EBC_CS_N(1) */
1455 gpio_tab[GPIO0][6].alt_nb = GPIO_ALT1;
1457 gpio_tab[GPIO0][7].in_out = GPIO_OUT; /* EBC_CS_N(2) */
1458 gpio_tab[GPIO0][7].alt_nb = GPIO_ALT1;
1461 gpio_tab[GPIO0][7].in_out = GPIO_OUT; /* EBC_CS_N(3) */
1462 gpio_tab[GPIO0][7].alt_nb = GPIO_ALT1;
1466 /*----------------------------------------------------------------------------+
1467 | update_zii_ios(void).
1468 +----------------------------------------------------------------------------*/
1469 void update_zii_ios(gpio_param_s (*gpio_tab)[GPIO_MAX])
1471 /* Update GPIO Configuration Table */
1472 gpio_tab[GPIO0][12].in_out = GPIO_IN; /* ZII_p0Rxd(0) */
1473 gpio_tab[GPIO0][12].alt_nb = GPIO_ALT1;
1475 gpio_tab[GPIO0][13].in_out = GPIO_IN; /* ZII_p0Rxd(1) */
1476 gpio_tab[GPIO0][13].alt_nb = GPIO_ALT1;
1478 gpio_tab[GPIO0][14].in_out = GPIO_IN; /* ZII_p0Rxd(2) */
1479 gpio_tab[GPIO0][14].alt_nb = GPIO_ALT1;
1481 gpio_tab[GPIO0][15].in_out = GPIO_IN; /* ZII_p0Rxd(3) */
1482 gpio_tab[GPIO0][15].alt_nb = GPIO_ALT1;
1484 gpio_tab[GPIO0][16].in_out = GPIO_OUT; /* ZII_p0Txd(0) */
1485 gpio_tab[GPIO0][16].alt_nb = GPIO_ALT1;
1487 gpio_tab[GPIO0][17].in_out = GPIO_OUT; /* ZII_p0Txd(1) */
1488 gpio_tab[GPIO0][17].alt_nb = GPIO_ALT1;
1490 gpio_tab[GPIO0][18].in_out = GPIO_OUT; /* ZII_p0Txd(2) */
1491 gpio_tab[GPIO0][18].alt_nb = GPIO_ALT1;
1493 gpio_tab[GPIO0][19].in_out = GPIO_OUT; /* ZII_p0Txd(3) */
1494 gpio_tab[GPIO0][19].alt_nb = GPIO_ALT1;
1496 gpio_tab[GPIO0][20].in_out = GPIO_IN; /* ZII_p0Rx_er */
1497 gpio_tab[GPIO0][20].alt_nb = GPIO_ALT1;
1499 gpio_tab[GPIO0][21].in_out = GPIO_IN; /* ZII_p0Rx_dv */
1500 gpio_tab[GPIO0][21].alt_nb = GPIO_ALT1;
1502 gpio_tab[GPIO0][22].in_out = GPIO_IN; /* ZII_p0Crs */
1503 gpio_tab[GPIO0][22].alt_nb = GPIO_ALT1;
1505 gpio_tab[GPIO0][23].in_out = GPIO_OUT; /* ZII_p0Tx_er */
1506 gpio_tab[GPIO0][23].alt_nb = GPIO_ALT1;
1508 gpio_tab[GPIO0][24].in_out = GPIO_OUT; /* ZII_p0Tx_en */
1509 gpio_tab[GPIO0][24].alt_nb = GPIO_ALT1;
1511 gpio_tab[GPIO0][25].in_out = GPIO_IN; /* ZII_p0Col */
1512 gpio_tab[GPIO0][25].alt_nb = GPIO_ALT1;
1516 /*----------------------------------------------------------------------------+
1517 | update_uic_0_3_irq_ios().
1518 +----------------------------------------------------------------------------*/
1519 void update_uic_0_3_irq_ios(gpio_param_s (*gpio_tab)[GPIO_MAX])
1521 gpio_tab[GPIO1][8].in_out = GPIO_IN; /* UIC_IRQ(0) */
1522 gpio_tab[GPIO1][8].alt_nb = GPIO_ALT1;
1524 gpio_tab[GPIO1][9].in_out = GPIO_IN; /* UIC_IRQ(1) */
1525 gpio_tab[GPIO1][9].alt_nb = GPIO_ALT1;
1527 gpio_tab[GPIO1][10].in_out = GPIO_IN; /* UIC_IRQ(2) */
1528 gpio_tab[GPIO1][10].alt_nb = GPIO_ALT1;
1530 gpio_tab[GPIO1][11].in_out = GPIO_IN; /* UIC_IRQ(3) */
1531 gpio_tab[GPIO1][11].alt_nb = GPIO_ALT1;
1534 /*----------------------------------------------------------------------------+
1535 | update_uic_4_9_irq_ios().
1536 +----------------------------------------------------------------------------*/
1537 void update_uic_4_9_irq_ios(gpio_param_s (*gpio_tab)[GPIO_MAX])
1539 gpio_tab[GPIO1][12].in_out = GPIO_IN; /* UIC_IRQ(4) */
1540 gpio_tab[GPIO1][12].alt_nb = GPIO_ALT1;
1542 gpio_tab[GPIO1][13].in_out = GPIO_IN; /* UIC_IRQ(6) */
1543 gpio_tab[GPIO1][13].alt_nb = GPIO_ALT1;
1545 gpio_tab[GPIO1][14].in_out = GPIO_IN; /* UIC_IRQ(7) */
1546 gpio_tab[GPIO1][14].alt_nb = GPIO_ALT1;
1548 gpio_tab[GPIO1][15].in_out = GPIO_IN; /* UIC_IRQ(8) */
1549 gpio_tab[GPIO1][15].alt_nb = GPIO_ALT1;
1551 gpio_tab[GPIO1][16].in_out = GPIO_IN; /* UIC_IRQ(9) */
1552 gpio_tab[GPIO1][16].alt_nb = GPIO_ALT1;
1555 /*----------------------------------------------------------------------------+
1556 | update_dma_a_b_ios().
1557 +----------------------------------------------------------------------------*/
1558 void update_dma_a_b_ios(gpio_param_s (*gpio_tab)[GPIO_MAX])
1560 gpio_tab[GPIO1][12].in_out = GPIO_OUT; /* DMA_ACK(1) */
1561 gpio_tab[GPIO1][12].alt_nb = GPIO_ALT2;
1563 gpio_tab[GPIO1][13].in_out = GPIO_BI; /* DMA_EOT/TC(1) */
1564 gpio_tab[GPIO1][13].alt_nb = GPIO_ALT2;
1566 gpio_tab[GPIO1][14].in_out = GPIO_IN; /* DMA_REQ(0) */
1567 gpio_tab[GPIO1][14].alt_nb = GPIO_ALT2;
1569 gpio_tab[GPIO1][15].in_out = GPIO_OUT; /* DMA_ACK(0) */
1570 gpio_tab[GPIO1][15].alt_nb = GPIO_ALT2;
1572 gpio_tab[GPIO1][16].in_out = GPIO_BI; /* DMA_EOT/TC(0) */
1573 gpio_tab[GPIO1][16].alt_nb = GPIO_ALT2;
1576 /*----------------------------------------------------------------------------+
1577 | update_dma_c_d_ios().
1578 +----------------------------------------------------------------------------*/
1579 void update_dma_c_d_ios(gpio_param_s (*gpio_tab)[GPIO_MAX])
1581 gpio_tab[GPIO0][0].in_out = GPIO_IN; /* DMA_REQ(2) */
1582 gpio_tab[GPIO0][0].alt_nb = GPIO_ALT2;
1584 gpio_tab[GPIO0][1].in_out = GPIO_OUT; /* DMA_ACK(2) */
1585 gpio_tab[GPIO0][1].alt_nb = GPIO_ALT2;
1587 gpio_tab[GPIO0][2].in_out = GPIO_BI; /* DMA_EOT/TC(2) */
1588 gpio_tab[GPIO0][2].alt_nb = GPIO_ALT2;
1590 gpio_tab[GPIO0][3].in_out = GPIO_IN; /* DMA_REQ(3) */
1591 gpio_tab[GPIO0][3].alt_nb = GPIO_ALT2;
1593 gpio_tab[GPIO0][4].in_out = GPIO_OUT; /* DMA_ACK(3) */
1594 gpio_tab[GPIO0][4].alt_nb = GPIO_ALT2;
1596 gpio_tab[GPIO0][5].in_out = GPIO_BI; /* DMA_EOT/TC(3) */
1597 gpio_tab[GPIO0][5].alt_nb = GPIO_ALT2;
1601 /*----------------------------------------------------------------------------+
1602 | update_ebc_master_ios().
1603 +----------------------------------------------------------------------------*/
1604 void update_ebc_master_ios(gpio_param_s (*gpio_tab)[GPIO_MAX])
1606 gpio_tab[GPIO0][27].in_out = GPIO_IN; /* EXT_EBC_REQ */
1607 gpio_tab[GPIO0][27].alt_nb = GPIO_ALT1;
1609 gpio_tab[GPIO0][29].in_out = GPIO_OUT; /* EBC_EXT_HDLA */
1610 gpio_tab[GPIO0][29].alt_nb = GPIO_ALT1;
1612 gpio_tab[GPIO0][30].in_out = GPIO_OUT; /* EBC_EXT_ACK */
1613 gpio_tab[GPIO0][30].alt_nb = GPIO_ALT1;
1615 gpio_tab[GPIO0][31].in_out = GPIO_OUT; /* EBC_EXR_BUSREQ */
1616 gpio_tab[GPIO0][31].alt_nb = GPIO_ALT1;
1619 /*----------------------------------------------------------------------------+
1620 | update_usb2_device_ios().
1621 +----------------------------------------------------------------------------*/
1622 void update_usb2_device_ios(gpio_param_s (*gpio_tab)[GPIO_MAX])
1624 gpio_tab[GPIO0][26].in_out = GPIO_IN; /* USB2D_RXVALID */
1625 gpio_tab[GPIO0][26].alt_nb = GPIO_ALT2;
1627 gpio_tab[GPIO0][27].in_out = GPIO_IN; /* USB2D_RXERROR */
1628 gpio_tab[GPIO0][27].alt_nb = GPIO_ALT2;
1630 gpio_tab[GPIO0][28].in_out = GPIO_OUT; /* USB2D_TXVALID */
1631 gpio_tab[GPIO0][28].alt_nb = GPIO_ALT2;
1633 gpio_tab[GPIO0][29].in_out = GPIO_OUT; /* USB2D_PAD_SUSPNDM */
1634 gpio_tab[GPIO0][29].alt_nb = GPIO_ALT2;
1636 gpio_tab[GPIO0][30].in_out = GPIO_OUT; /* USB2D_XCVRSELECT */
1637 gpio_tab[GPIO0][30].alt_nb = GPIO_ALT2;
1639 gpio_tab[GPIO0][31].in_out = GPIO_OUT; /* USB2D_TERMSELECT */
1640 gpio_tab[GPIO0][31].alt_nb = GPIO_ALT2;
1642 gpio_tab[GPIO1][0].in_out = GPIO_OUT; /* USB2D_OPMODE0 */
1643 gpio_tab[GPIO1][0].alt_nb = GPIO_ALT1;
1645 gpio_tab[GPIO1][1].in_out = GPIO_OUT; /* USB2D_OPMODE1 */
1646 gpio_tab[GPIO1][1].alt_nb = GPIO_ALT1;
1650 /*----------------------------------------------------------------------------+
1651 | update_pci_patch_ios().
1652 +----------------------------------------------------------------------------*/
1653 void update_pci_patch_ios(gpio_param_s (*gpio_tab)[GPIO_MAX])
1655 gpio_tab[GPIO0][29].in_out = GPIO_OUT; /* EBC_EXT_HDLA */
1656 gpio_tab[GPIO0][29].alt_nb = GPIO_ALT1;
1659 /*----------------------------------------------------------------------------+
1660 | set_chip_gpio_configuration(unsigned char gpio_core,
1661 | gpio_param_s (*gpio_tab)[GPIO_MAX])
1662 | Put the core impacted by clock modification and sharing in reset.
1663 | Config the select registers to resolve the sharing depending of the config.
1664 | Configure the GPIO registers.
1666 +----------------------------------------------------------------------------*/
1667 void set_chip_gpio_configuration(unsigned char gpio_core, gpio_param_s (*gpio_tab)[GPIO_MAX])
1669 unsigned char i=0, j=0, reg_offset = 0;
1670 unsigned long gpio_reg, gpio_core_add;
1672 /* GPIO config of the GPIOs 0 to 31 */
1673 for (i=0; i<GPIO_MAX; i++, j++)
1675 if (i == GPIO_MAX/2)
1681 gpio_core_add = gpio_tab[gpio_core][i].add;
1683 if ( (gpio_tab[gpio_core][i].in_out == GPIO_IN) ||
1684 (gpio_tab[gpio_core][i].in_out == GPIO_BI ))
1686 switch (gpio_tab[gpio_core][i].alt_nb)
1692 gpio_reg = in32(GPIO_IS1(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2));
1693 gpio_reg = gpio_reg | (GPIO_IN_SEL >> (j*2));
1694 out32(GPIO_IS1(gpio_core_add+reg_offset), gpio_reg);
1698 gpio_reg = in32(GPIO_IS2(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2));
1699 gpio_reg = gpio_reg | (GPIO_IN_SEL >> (j*2));
1700 out32(GPIO_IS2(gpio_core_add+reg_offset), gpio_reg);
1704 gpio_reg = in32(GPIO_IS3(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2));
1705 gpio_reg = gpio_reg | (GPIO_IN_SEL >> (j*2));
1706 out32(GPIO_IS3(gpio_core_add+reg_offset), gpio_reg);
1710 if ( (gpio_tab[gpio_core][i].in_out == GPIO_OUT) ||
1711 (gpio_tab[gpio_core][i].in_out == GPIO_BI ))
1714 switch (gpio_tab[gpio_core][i].alt_nb)
1719 gpio_reg = in32(GPIO_OS(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2));
1720 gpio_reg = gpio_reg | (GPIO_ALT1_SEL >> (j*2));
1721 out32(GPIO_OS(gpio_core_add+reg_offset), gpio_reg);
1722 gpio_reg = in32(GPIO_TS(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2));
1723 gpio_reg = gpio_reg | (GPIO_ALT1_SEL >> (j*2));
1724 out32(GPIO_TS(gpio_core_add+reg_offset), gpio_reg);
1727 gpio_reg = in32(GPIO_OS(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2));
1728 gpio_reg = gpio_reg | (GPIO_ALT2_SEL >> (j*2));
1729 out32(GPIO_OS(gpio_core_add+reg_offset), gpio_reg);
1730 gpio_reg = in32(GPIO_TS(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2));
1731 gpio_reg = gpio_reg | (GPIO_ALT2_SEL >> (j*2));
1732 out32(GPIO_TS(gpio_core_add+reg_offset), gpio_reg);
1735 gpio_reg = in32(GPIO_OS(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2));
1736 gpio_reg = gpio_reg | (GPIO_ALT3_SEL >> (j*2));
1737 out32(GPIO_OS(gpio_core_add+reg_offset), gpio_reg);
1738 gpio_reg = in32(GPIO_TS(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2));
1739 gpio_reg = gpio_reg | (GPIO_ALT3_SEL >> (j*2));
1740 out32(GPIO_TS(gpio_core_add+reg_offset), gpio_reg);
1747 /*----------------------------------------------------------------------------+
1748 | force_bup_core_selection.
1749 +----------------------------------------------------------------------------*/
1750 void force_bup_core_selection(core_selection_t *core_select_P, config_validity_t *config_val_P)
1752 /* Pointer invalid */
1753 if (core_select_P == NULL)
1755 printf("Configuration invalid pointer 1\n");
1761 *(core_select_P+UART_CORE0) = CORE_SELECTED;
1762 *(core_select_P+UART_CORE1) = CORE_SELECTED;
1763 *(core_select_P+UART_CORE2) = CORE_SELECTED;
1764 *(core_select_P+UART_CORE3) = CORE_SELECTED;
1766 /* RMII Selection */
1767 *(core_select_P+RMII_SEL) = CORE_SELECTED;
1769 /* External Interrupt 0-9 selection */
1770 *(core_select_P+UIC_0_3) = CORE_SELECTED;
1771 *(core_select_P+UIC_4_9) = CORE_SELECTED;
1773 *(core_select_P+SCP_CORE) = CORE_SELECTED;
1774 *(core_select_P+DMA_CHANNEL_CD) = CORE_SELECTED;
1775 *(core_select_P+PACKET_REJ_FUNC_AVAIL) = CORE_SELECTED;
1776 *(core_select_P+USB1_DEVICE) = CORE_SELECTED;
1778 if (is_nand_selected()) {
1779 *(core_select_P+NAND_FLASH) = CORE_SELECTED;
1782 *config_val_P = CONFIG_IS_VALID;
1786 /*----------------------------------------------------------------------------+
1787 | configure_ppc440ep_pins.
1788 +----------------------------------------------------------------------------*/
1789 void configure_ppc440ep_pins(void)
1791 uart_config_nb_t uart_configuration;
1792 config_validity_t config_val = CONFIG_IS_INVALID;
1794 /* Create Core Selection Table */
1795 core_selection_t ppc440ep_core_selection[MAX_CORE_SELECT_NB] =
1797 CORE_NOT_SELECTED, /* IIC_CORE, */
1798 CORE_NOT_SELECTED, /* SPC_CORE, */
1799 CORE_NOT_SELECTED, /* DMA_CHANNEL_AB, */
1800 CORE_NOT_SELECTED, /* UIC_4_9, */
1801 CORE_NOT_SELECTED, /* USB2_HOST, */
1802 CORE_NOT_SELECTED, /* DMA_CHANNEL_CD, */
1803 CORE_NOT_SELECTED, /* USB2_DEVICE, */
1804 CORE_NOT_SELECTED, /* PACKET_REJ_FUNC_AVAIL, */
1805 CORE_NOT_SELECTED, /* USB1_DEVICE, */
1806 CORE_NOT_SELECTED, /* EBC_MASTER, */
1807 CORE_NOT_SELECTED, /* NAND_FLASH, */
1808 CORE_NOT_SELECTED, /* UART_CORE0, */
1809 CORE_NOT_SELECTED, /* UART_CORE1, */
1810 CORE_NOT_SELECTED, /* UART_CORE2, */
1811 CORE_NOT_SELECTED, /* UART_CORE3, */
1812 CORE_NOT_SELECTED, /* MII_SEL, */
1813 CORE_NOT_SELECTED, /* RMII_SEL, */
1814 CORE_NOT_SELECTED, /* SMII_SEL, */
1815 CORE_NOT_SELECTED, /* PACKET_REJ_FUNC_EN */
1816 CORE_NOT_SELECTED, /* UIC_0_3 */
1817 CORE_NOT_SELECTED, /* USB1_HOST */
1818 CORE_NOT_SELECTED /* PCI_PATCH */
1821 gpio_param_s gpio_tab[GPIO_GROUP_MAX][GPIO_MAX];
1823 /* Table Default Initialisation + FPGA Access */
1824 init_default_gpio(gpio_tab);
1825 set_chip_gpio_configuration(GPIO0, gpio_tab);
1826 set_chip_gpio_configuration(GPIO1, gpio_tab);
1829 force_bup_core_selection(ppc440ep_core_selection, &config_val);
1830 #if 0 /* test-only */
1831 /* If we are running PIBS 1, force known configuration */
1832 update_core_selection_table(ppc440ep_core_selection, &config_val);
1835 /*----------------------------------------------------------------------------+
1836 | SDR + ios table update + fpga initialization
1837 +----------------------------------------------------------------------------*/
1838 unsigned long sdr0_pfc1 = 0;
1839 unsigned long sdr0_usb0 = 0;
1840 unsigned long sdr0_mfr = 0;
1842 /* PCI Always selected */
1845 if (ppc440ep_core_selection[IIC_CORE] == CORE_SELECTED)
1847 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SIS_MASK) | SDR0_PFC1_SIS_IIC1_SEL;
1848 iic1_selection_in_fpga();
1852 if (ppc440ep_core_selection[SCP_CORE] == CORE_SELECTED)
1854 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SIS_MASK) | SDR0_PFC1_SIS_SCP_SEL;
1855 scp_selection_in_fpga();
1858 /* UIC 0:3 Selection */
1859 if (ppc440ep_core_selection[UIC_0_3] == CORE_SELECTED)
1861 update_uic_0_3_irq_ios(gpio_tab);
1862 dma_a_b_unselect_in_fpga();
1865 /* UIC 4:9 Selection */
1866 if (ppc440ep_core_selection[UIC_4_9] == CORE_SELECTED)
1868 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_DIS_MASK) | SDR0_PFC1_DIS_UICIRQ5_SEL;
1869 update_uic_4_9_irq_ios(gpio_tab);
1872 /* DMA AB Selection */
1873 if (ppc440ep_core_selection[DMA_CHANNEL_AB] == CORE_SELECTED)
1875 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_DIS_MASK) | SDR0_PFC1_DIS_DMAR_SEL;
1876 update_dma_a_b_ios(gpio_tab);
1877 dma_a_b_selection_in_fpga();
1880 /* DMA CD Selection */
1881 if (ppc440ep_core_selection[DMA_CHANNEL_CD] == CORE_SELECTED)
1883 update_dma_c_d_ios(gpio_tab);
1884 dma_c_d_selection_in_fpga();
1887 /* EBC Master Selection */
1888 if (ppc440ep_core_selection[EBC_MASTER] == CORE_SELECTED)
1890 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_ERE_MASK) | SDR0_PFC1_ERE_EXTR_SEL;
1891 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_UES_MASK) | SDR0_PFC1_UES_EBCHR_SEL;
1892 update_ebc_master_ios(gpio_tab);
1895 /* PCI Patch Enable */
1896 if (ppc440ep_core_selection[PCI_PATCH] == CORE_SELECTED)
1898 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_UES_MASK) | SDR0_PFC1_UES_EBCHR_SEL;
1899 update_pci_patch_ios(gpio_tab);
1902 /* USB2 Host Selection - Not Implemented in PowerPC 440EP Pass1 */
1903 if (ppc440ep_core_selection[USB2_HOST] == CORE_SELECTED)
1905 /* Not Implemented in PowerPC 440EP Pass1-Pass2 */
1906 printf("Invalid configuration => USB2 Host selected\n");
1909 /*usb2_host_selection_in_fpga(); */
1912 /* USB2.0 Device Selection */
1913 if (ppc440ep_core_selection[USB2_DEVICE] == CORE_SELECTED)
1915 update_usb2_device_ios(gpio_tab);
1916 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_UES_MASK) | SDR0_PFC1_UES_USB2D_SEL;
1917 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_UPR_MASK) | SDR0_PFC1_UPR_DISABLE;
1919 mfsdr(SDR0_USB0, sdr0_usb0);
1920 sdr0_usb0 = sdr0_usb0 &~SDR0_USB0_USB_DEVSEL_MASK;
1921 sdr0_usb0 = sdr0_usb0 | SDR0_USB0_USB20D_DEVSEL;
1922 mtsdr(SDR0_USB0, sdr0_usb0);
1924 usb2_device_selection_in_fpga();
1927 /* USB1.1 Device Selection */
1928 if (ppc440ep_core_selection[USB1_DEVICE] == CORE_SELECTED)
1930 mfsdr(SDR0_USB0, sdr0_usb0);
1931 sdr0_usb0 = sdr0_usb0 &~SDR0_USB0_USB_DEVSEL_MASK;
1932 sdr0_usb0 = sdr0_usb0 | SDR0_USB0_USB11D_DEVSEL;
1933 mtsdr(SDR0_USB0, sdr0_usb0);
1936 /* USB1.1 Host Selection */
1937 if (ppc440ep_core_selection[USB1_HOST] == CORE_SELECTED)
1939 mfsdr(SDR0_USB0, sdr0_usb0);
1940 sdr0_usb0 = sdr0_usb0 &~SDR0_USB0_LEEN_MASK;
1941 sdr0_usb0 = sdr0_usb0 | SDR0_USB0_LEEN_ENABLE;
1942 mtsdr(SDR0_USB0, sdr0_usb0);
1945 /* NAND Flash Selection */
1946 if (ppc440ep_core_selection[NAND_FLASH] == CORE_SELECTED)
1948 update_ndfc_ios(gpio_tab);
1950 #if !(defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL))
1951 mtsdr(SDR0_CUST0, SDR0_CUST0_MUX_NDFC_SEL |
1952 SDR0_CUST0_NDFC_ENABLE |
1953 SDR0_CUST0_NDFC_BW_8_BIT |
1954 SDR0_CUST0_NDFC_ARE_MASK |
1955 SDR0_CUST0_CHIPSELGAT_EN1 |
1956 SDR0_CUST0_CHIPSELGAT_EN2);
1958 mtsdr(SDR0_CUST0, SDR0_CUST0_MUX_NDFC_SEL |
1959 SDR0_CUST0_NDFC_ENABLE |
1960 SDR0_CUST0_NDFC_BW_8_BIT |
1961 SDR0_CUST0_NDFC_ARE_MASK |
1962 SDR0_CUST0_CHIPSELGAT_EN0 |
1963 SDR0_CUST0_CHIPSELGAT_EN2);
1966 ndfc_selection_in_fpga();
1970 /* Set Mux on EMAC */
1971 mtsdr(SDR0_CUST0, SDR0_CUST0_MUX_EMAC_SEL);
1975 if (ppc440ep_core_selection[MII_SEL] == CORE_SELECTED)
1977 update_zii_ios(gpio_tab);
1978 mfsdr(SDR0_MFR, sdr0_mfr);
1979 sdr0_mfr = (sdr0_mfr & ~SDR0_MFR_ZMII_MODE_MASK) | SDR0_MFR_ZMII_MODE_MII;
1980 mtsdr(SDR0_MFR, sdr0_mfr);
1982 set_phy_configuration_through_fpga(ZMII_CONFIGURATION_IS_MII);
1985 /* RMII Selection */
1986 if (ppc440ep_core_selection[RMII_SEL] == CORE_SELECTED)
1988 update_zii_ios(gpio_tab);
1989 mfsdr(SDR0_MFR, sdr0_mfr);
1990 sdr0_mfr = (sdr0_mfr & ~SDR0_MFR_ZMII_MODE_MASK) | SDR0_MFR_ZMII_MODE_RMII_10M;
1991 mtsdr(SDR0_MFR, sdr0_mfr);
1993 set_phy_configuration_through_fpga(ZMII_CONFIGURATION_IS_RMII);
1996 /* SMII Selection */
1997 if (ppc440ep_core_selection[SMII_SEL] == CORE_SELECTED)
1999 update_zii_ios(gpio_tab);
2000 mfsdr(SDR0_MFR, sdr0_mfr);
2001 sdr0_mfr = (sdr0_mfr & ~SDR0_MFR_ZMII_MODE_MASK) | SDR0_MFR_ZMII_MODE_SMII;
2002 mtsdr(SDR0_MFR, sdr0_mfr);
2004 set_phy_configuration_through_fpga(ZMII_CONFIGURATION_IS_SMII);
2007 /* UART Selection */
2008 uart_configuration = get_uart_configuration();
2009 switch (uart_configuration)
2011 case L1: /* L1 Selection */
2012 /* UART0 8 pins Only */
2013 /*sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0ME_MASK) | SDR0_PFC1_U0ME_DSR_DTR; */
2014 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0ME_MASK) |SDR0_PFC1_U0ME_CTS_RTS; /* Chip Pb */
2015 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0IM_MASK) | SDR0_PFC1_U0IM_8PINS;
2017 case L2: /* L2 Selection */
2018 /* UART0 and UART1 4 pins */
2019 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0ME_MASK) | SDR0_PFC1_U1ME_DSR_DTR;
2020 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0IM_MASK) | SDR0_PFC1_U0IM_4PINS;
2021 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U1ME_MASK) | SDR0_PFC1_U1ME_DSR_DTR;
2023 case L3: /* L3 Selection */
2024 /* UART0 4 pins, UART1 and UART2 2 pins */
2025 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0ME_MASK) | SDR0_PFC1_U1ME_DSR_DTR;
2026 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0IM_MASK) | SDR0_PFC1_U0IM_4PINS;
2027 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U1ME_MASK) | SDR0_PFC1_U1ME_DSR_DTR;
2029 case L4: /* L4 Selection */
2030 /* UART0, UART1, UART2 and UART3 2 pins */
2031 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0ME_MASK) | SDR0_PFC1_U0ME_DSR_DTR;
2032 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0IM_MASK) | SDR0_PFC1_U0IM_4PINS;
2033 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U1ME_MASK) | SDR0_PFC1_U1ME_DSR_DTR;
2036 update_uart_ios(uart_configuration, gpio_tab);
2038 /* UART Selection in all cases */
2039 uart_selection_in_fpga(uart_configuration);
2041 /* Packet Reject Function Available */
2042 if (ppc440ep_core_selection[PACKET_REJ_FUNC_AVAIL] == CORE_SELECTED)
2044 /* Set UPR Bit in SDR0_PFC1 Register */
2045 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_UPR_MASK) | SDR0_PFC1_UPR_ENABLE;
2048 /* Packet Reject Function Enable */
2049 if (ppc440ep_core_selection[PACKET_REJ_FUNC_EN] == CORE_SELECTED)
2051 mfsdr(SDR0_MFR, sdr0_mfr);
2052 sdr0_mfr = (sdr0_mfr & ~SDR0_MFR_PKT_REJ_MASK) | SDR0_MFR_PKT_REJ_EN;;
2053 mtsdr(SDR0_MFR, sdr0_mfr);
2056 /* Perform effective access to hardware */
2057 mtsdr(SDR0_PFC1, sdr0_pfc1);
2058 set_chip_gpio_configuration(GPIO0, gpio_tab);
2059 set_chip_gpio_configuration(GPIO1, gpio_tab);
2061 /* USB2.0 Device Reset must be done after GPIO setting */
2062 if (ppc440ep_core_selection[USB2_DEVICE] == CORE_SELECTED)
2063 usb2_device_reset_through_fpga();