2 * Copyright (C) 2002 Scott McNutt <smcnutt@artesyncp.com>
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 #include <asm/processor.h>
25 #include <spd_sdram.h>
27 #define BOOT_SMALL_FLASH 32 /* 00100000 */
28 #define FLASH_ONBD_N 2 /* 00000010 */
29 #define FLASH_SRAM_SEL 1 /* 00000001 */
31 DECLARE_GLOBAL_DATA_PTR;
33 long int fixed_sdram(void);
35 int board_early_init_f(void)
38 unsigned char *fpga_base = (unsigned char *)CFG_FPGA_BASE;
41 /*--------------------------------------------------------------------
42 * Setup the external bus controller/chip selects
43 *-------------------------------------------------------------------*/
44 mtdcr(ebccfga, xbcfg);
46 mtdcr(ebccfgd, reg | 0x04000000); /* Set ATC */
48 mtebc(pb1ap, 0x02815480); /* NVRAM/RTC */
49 mtebc(pb1cr, 0x48018000); /* BA=0x480 1MB R/W 8-bit */
50 mtebc(pb7ap, 0x01015280); /* FPGA registers */
51 mtebc(pb7cr, 0x48318000); /* BA=0x483 1MB R/W 8-bit */
53 /* read FPGA_REG0 and set the bus controller */
55 if ((status & BOOT_SMALL_FLASH) && !(status & FLASH_ONBD_N)) {
56 mtebc(pb0ap, 0x9b015480); /* FLASH/SRAM */
57 mtebc(pb0cr, 0xfff18000); /* BAS=0xfff 1MB R/W 8-bit */
58 mtebc(pb2ap, 0x9b015480); /* 4MB FLASH */
59 mtebc(pb2cr, 0xff858000); /* BAS=0xff8 4MB R/W 8-bit */
61 mtebc(pb0ap, 0x9b015480); /* 4MB FLASH */
62 mtebc(pb0cr, 0xffc58000); /* BAS=0xffc 4MB R/W 8-bit */
64 /* set CS2 if FLASH_ONBD_N == 0 */
65 if (!(status & FLASH_ONBD_N)) {
66 mtebc(pb2ap, 0x9b015480); /* FLASH/SRAM */
67 mtebc(pb2cr, 0xff818000); /* BAS=0xff8 4MB R/W 8-bit */
71 /*--------------------------------------------------------------------
72 * Setup the interrupt controller polarities, triggers, etc.
73 *-------------------------------------------------------------------*/
74 mtdcr(uic0sr, 0xffffffff); /* clear all */
75 mtdcr(uic0er, 0x00000000); /* disable all */
76 mtdcr(uic0cr, 0x00000009); /* SMI & UIC1 crit are critical */
77 mtdcr(uic0pr, 0xfffffe13); /* per ref-board manual */
78 mtdcr(uic0tr, 0x01c00008); /* per ref-board manual */
79 mtdcr(uic0vr, 0x00000001); /* int31 highest, base=0x000 */
80 mtdcr(uic0sr, 0xffffffff); /* clear all */
82 mtdcr(uic1sr, 0xffffffff); /* clear all */
83 mtdcr(uic1er, 0x00000000); /* disable all */
84 mtdcr(uic1cr, 0x00000000); /* all non-critical */
85 mtdcr(uic1pr, 0xffffe0ff); /* per ref-board manual */
86 mtdcr(uic1tr, 0x00ffc000); /* per ref-board manual */
87 mtdcr(uic1vr, 0x00000001); /* int31 highest, base=0x000 */
88 mtdcr(uic1sr, 0xffffffff); /* clear all */
95 char *s = getenv("serial#");
97 printf("Board: Ebony - AMCC PPC440GP Evaluation Board");
107 phys_size_t initdram(int board_type)
111 #if defined(CONFIG_SPD_EEPROM)
112 dram_size = spd_sdram();
114 dram_size = fixed_sdram();
119 #if !defined(CONFIG_SPD_EEPROM)
120 /*************************************************************************
121 * fixed sdram init -- doesn't use serial presence detect.
123 * Assumes: 128 MB, non-ECC, non-registered
126 ************************************************************************/
127 long int fixed_sdram(void)
131 /*--------------------------------------------------------------------
133 *------------------------------------------------------------------*/
134 mtsdram(mem_uabba, 0x00000000); /* ubba=0 (default) */
135 mtsdram(mem_slio, 0x00000000); /* rdre=0 wrre=0 rarw=0 */
136 mtsdram(mem_devopt, 0x00000000); /* dll=0 ds=0 (normal) */
137 mtsdram(mem_wddctr, 0x00000000); /* wrcp=0 dcd=0 */
138 mtsdram(mem_clktr, 0x40000000); /* clkp=1 (90 deg wr) dcdt=0 */
140 /*--------------------------------------------------------------------
141 * Setup for board-specific specific mem
142 *------------------------------------------------------------------*/
144 * Following for CAS Latency = 2.5 @ 133 MHz PLB
146 mtsdram(mem_b0cr, 0x000a4001); /* SDBA=0x000 128MB, Mode 3, enabled */
147 mtsdram(mem_tr0, 0x410a4012); /* WR=2 WD=1 CL=2.5 PA=3 CP=4 LD=2 */
149 mtsdram(mem_tr1, 0x8080082f); /* SS=T2 SL=STAGE 3 CD=1 CT=0x02f */
150 mtsdram(mem_rtr, 0x08200000); /* Rate 15.625 ns @ 133 MHz PLB */
151 mtsdram(mem_cfg1, 0x00000000); /* Self-refresh exit, disable PM */
152 udelay(400); /* Delay 200 usecs (min) */
154 /*--------------------------------------------------------------------
155 * Enable the controller, then wait for DCEN to complete
156 *------------------------------------------------------------------*/
157 mtsdram(mem_cfg0, 0x86000000); /* DCEN=1, PMUD=1, 64-bit */
159 mfsdram(mem_mcsts, reg);
160 if (reg & 0x80000000)
164 return (128 * 1024 * 1024); /* 128 MB */
166 #endif /* !defined(CONFIG_SPD_EEPROM) */
168 /*************************************************************************
171 * This routine is called just prior to registering the hose and gives
172 * the board the opportunity to check things. Returning a value of zero
173 * indicates that things are bad & PCI initialization should be aborted.
175 * Different boards may wish to customize the pci controller structure
176 * (add regions, override default access routines, etc) or perform
177 * certain pre-initialization actions.
179 ************************************************************************/
180 #if defined(CONFIG_PCI)
181 int pci_pre_init(struct pci_controller *hose)
185 /*--------------------------------------------------------------------------+
186 * The ebony board is always configured as the host & requires the
187 * PCI arbiter to be enabled.
188 *--------------------------------------------------------------------------*/
189 strap = mfdcr(cpc0_strp1);
190 if ((strap & 0x00100000) == 0) {
191 printf("PCI: CPC0_STRP1[PAE] not set.\n");
197 #endif /* defined(CONFIG_PCI) */
199 /*************************************************************************
202 * The bootstrap configuration provides default settings for the pci
203 * inbound map (PIM). But the bootstrap config choices are limited and
204 * may not be sufficient for a given board.
206 ************************************************************************/
207 #if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
208 void pci_target_init(struct pci_controller *hose)
210 /*--------------------------------------------------------------------------+
212 *--------------------------------------------------------------------------*/
213 out32r(PCIX0_PIM0SA, 0); /* disable */
214 out32r(PCIX0_PIM1SA, 0); /* disable */
215 out32r(PCIX0_PIM2SA, 0); /* disable */
216 out32r(PCIX0_EROMBA, 0); /* disable expansion rom */
218 /*--------------------------------------------------------------------------+
219 * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 strapping
220 * options to not support sizes such as 128/256 MB.
221 *--------------------------------------------------------------------------*/
222 out32r(PCIX0_PIM0LAL, CFG_SDRAM_BASE);
223 out32r(PCIX0_PIM0LAH, 0);
224 out32r(PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1);
226 out32r(PCIX0_BAR0, 0);
228 /*--------------------------------------------------------------------------+
229 * Program the board's subsystem id/vendor id
230 *--------------------------------------------------------------------------*/
231 out16r(PCIX0_SBSYSVID, CFG_PCI_SUBSYS_VENDORID);
232 out16r(PCIX0_SBSYSID, CFG_PCI_SUBSYS_DEVICEID);
234 out16r(PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY);
236 #endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */
238 /*************************************************************************
241 * This routine is called to determine if a pci scan should be
242 * performed. With various hardware environments (especially cPCI and
243 * PPMC) it's insufficient to depend on the state of the arbiter enable
244 * bit in the strap register, or generic host/adapter assumptions.
246 * Rather than hard-code a bad assumption in the general 440 code, the
247 * 440 pci code requires the board to decide at runtime.
249 * Return 0 for adapter mode, non-zero for host (monarch) mode.
252 ************************************************************************/
253 #if defined(CONFIG_PCI)
254 int is_pci_host(struct pci_controller *hose)
256 /* The ebony board is always configured as host. */
259 #endif /* defined(CONFIG_PCI) */