2 * Copyright (C) 2002 Scott McNutt <smcnutt@artesyncp.com>
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 #include <ppc_asm.tmpl>
27 #define TLB_VALID 0x00000200
28 #define _256M 0x10000000
30 /* Supported page sizes */
32 #define SZ_1K 0x00000000
33 #define SZ_4K 0x00000010
34 #define SZ_16K 0x00000020
35 #define SZ_64K 0x00000030
36 #define SZ_256K 0x00000040
37 #define SZ_1M 0x00000050
38 #define SZ_8M 0x00000060
39 #define SZ_16M 0x00000070
40 #define SZ_256M 0x00000090
42 /* Storage attributes */
43 #define SA_W 0x00000800 /* Write-through */
44 #define SA_I 0x00000400 /* Caching inhibited */
45 #define SA_M 0x00000200 /* Memory coherence */
46 #define SA_G 0x00000100 /* Guarded */
47 #define SA_E 0x00000080 /* Endian */
50 #define AC_X 0x00000024 /* Execute */
51 #define AC_W 0x00000012 /* Write */
52 #define AC_R 0x00000009 /* Read */
54 /* Some handy macros */
56 #define EPN(e) ((e) & 0xfffffc00)
57 #define TLB0(epn,sz) ( (EPN((epn)) | (sz) | TLB_VALID ) )
58 #define TLB1(rpn,erpn) ( ((rpn)&0xfffffc00) | (erpn) )
59 #define TLB2(a) ( (a)&0x00000fbf )
71 #define tlbentry(epn,sz,rpn,erpn,attr)\
72 .long TLB0(epn,sz),TLB1(rpn,erpn),TLB2(attr)
75 /**************************************************************************
78 * This table is used by the cpu boot code to setup the initial tlb
79 * entries. Rather than make broad assumptions in the cpu source tree,
80 * this table lets each board set things up however they like.
82 * Pointer to the table is returned in r1
84 *************************************************************************/
91 tlbentry( 0xf0000000, SZ_256M, 0xf0000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I )
92 tlbentry( CFG_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1, AC_R|AC_W|SA_G|SA_I )
93 tlbentry( CFG_ISRAM_BASE, SZ_4K, 0x80000000, 0, AC_R|AC_W|AC_X )
94 tlbentry( CFG_ISRAM_BASE + 0x1000, SZ_4K, 0x80001000, 0, AC_R|AC_W|AC_X )
95 tlbentry( CFG_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
96 tlbentry( CFG_SDRAM_BASE + 0x10000000, SZ_256M, 0x10000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
97 tlbentry( CFG_SDRAM_BASE + 0x20000000, SZ_256M, 0x20000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
98 tlbentry( CFG_SDRAM_BASE + 0x30000000, SZ_256M, 0x30000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
99 tlbentry( CFG_PCI_BASE, SZ_256M, 0x00000000, 2, AC_R|AC_W|SA_G|SA_I )
100 tlbentry( CFG_PCI_MEMBASE, SZ_256M, 0x00000000, 3, AC_R|AC_W|SA_G|SA_I )