git.sur5r.net Git - u-boot/blob - board/amcc/sequoia/sequoia.c

   1 /*
   2  * (C) Copyright 2006
   3  * Stefan Roese, DENX Software Engineering, sr@denx.de.
   4  *
   5  * (C) Copyright 2006
   6  * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com
   7  * Alain Saurel,            AMCC/IBM, alain.saurel@fr.ibm.com
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License as
  11  * published by the Free Software Foundation; either version 2 of
  12  * the License, or (at your option) any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22  * MA 02111-1307 USA
  23  */
  24
  25 #include <common.h>
  26 #include <asm/processor.h>
  27 #include <ppc440.h>
  28 #include "sequoia.h"
  29
  30 DECLARE_GLOBAL_DATA_PTR;
  31
  32 extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips    */
  33
  34 ulong flash_get_size (ulong base, int banknum);
  35
  36 int board_early_init_f(void)
  37 {
  38         u32 sdr0_cust0;
  39         u32 sdr0_pfc1, sdr0_pfc2;
  40         u32 reg;
  41
  42         mtdcr(ebccfga, xbcfg);
  43         mtdcr(ebccfgd, 0xb8400000);
  44
  45         /*--------------------------------------------------------------------
  46          * Setup the GPIO pins
  47          *-------------------------------------------------------------------*/
  48         /* test-only: take GPIO init from pcs440ep ???? in config file */
  49         out32(GPIO0_OR, 0x00000000);
  50         out32(GPIO0_TCR, 0x0000000f);
  51         out32(GPIO0_OSRL, 0x50015400);
  52         out32(GPIO0_OSRH, 0x550050aa);
  53         out32(GPIO0_TSRL, 0x50015400);
  54         out32(GPIO0_TSRH, 0x55005000);
  55         out32(GPIO0_ISR1L, 0x50000000);
  56         out32(GPIO0_ISR1H, 0x00000000);
  57         out32(GPIO0_ISR2L, 0x00000000);
  58         out32(GPIO0_ISR2H, 0x00000100);
  59         out32(GPIO0_ISR3L, 0x00000000);
  60         out32(GPIO0_ISR3H, 0x00000000);
  61
  62         out32(GPIO1_OR, 0x00000000);
  63         out32(GPIO1_TCR, 0xc2000000);
  64         out32(GPIO1_OSRL, 0x5c280000);
  65         out32(GPIO1_OSRH, 0x00000000);
  66         out32(GPIO1_TSRL, 0x0c000000);
  67         out32(GPIO1_TSRH, 0x00000000);
  68         out32(GPIO1_ISR1L, 0x00005550);
  69         out32(GPIO1_ISR1H, 0x00000000);
  70         out32(GPIO1_ISR2L, 0x00050000);
  71         out32(GPIO1_ISR2H, 0x00000000);
  72         out32(GPIO1_ISR3L, 0x01400000);
  73         out32(GPIO1_ISR3H, 0x00000000);
  74
  75         /*--------------------------------------------------------------------
  76          * Setup the interrupt controller polarities, triggers, etc.
  77          *-------------------------------------------------------------------*/
  78         mtdcr(uic0sr, 0xffffffff);      /* clear all */
  79         mtdcr(uic0er, 0x00000000);      /* disable all */
  80         mtdcr(uic0cr, 0x00000005);      /* ATI & UIC1 crit are critical */
  81         mtdcr(uic0pr, 0xfffff7ff);      /* per ref-board manual */
  82         mtdcr(uic0tr, 0x00000000);      /* per ref-board manual */
  83         mtdcr(uic0vr, 0x00000000);      /* int31 highest, base=0x000 */
  84         mtdcr(uic0sr, 0xffffffff);      /* clear all */
  85
  86         mtdcr(uic1sr, 0xffffffff);      /* clear all */
  87         mtdcr(uic1er, 0x00000000);      /* disable all */
  88         mtdcr(uic1cr, 0x00000000);      /* all non-critical */
  89         mtdcr(uic1pr, 0xffffffff);      /* per ref-board manual */
  90         mtdcr(uic1tr, 0x00000000);      /* per ref-board manual */
  91         mtdcr(uic1vr, 0x00000000);      /* int31 highest, base=0x000 */
  92         mtdcr(uic1sr, 0xffffffff);      /* clear all */
  93
  94         mtdcr(uic2sr, 0xffffffff);      /* clear all */
  95         mtdcr(uic2er, 0x00000000);      /* disable all */
  96         mtdcr(uic2cr, 0x00000000);      /* all non-critical */
  97         mtdcr(uic2pr, 0xffffffff);      /* per ref-board manual */
  98         mtdcr(uic2tr, 0x00000000);      /* per ref-board manual */
  99         mtdcr(uic2vr, 0x00000000);      /* int31 highest, base=0x000 */
 100         mtdcr(uic2sr, 0xffffffff);      /* clear all */
 101
 102         /* 50MHz tmrclk */
 103         *(unsigned char *)(CFG_BCSR_BASE | 0x04) = 0x00;
 104
 105         /* clear write protects */
 106         *(unsigned char *)(CFG_BCSR_BASE | 0x07) = 0x00;
 107
 108         /* enable Ethernet */
 109         *(unsigned char *)(CFG_BCSR_BASE | 0x08) = 0x00;
 110
 111         /* enable USB device */
 112         *(unsigned char *)(CFG_BCSR_BASE | 0x09) = 0x20;
 113
 114         /* select Ethernet pins */
 115         mfsdr(SDR0_PFC1, sdr0_pfc1);
 116         sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SELECT_MASK) | SDR0_PFC1_SELECT_CONFIG_4;
 117         mfsdr(SDR0_PFC2, sdr0_pfc2);
 118         sdr0_pfc2 = (sdr0_pfc2 & ~SDR0_PFC2_SELECT_MASK) | SDR0_PFC2_SELECT_CONFIG_4;
 119         mtsdr(SDR0_PFC2, sdr0_pfc2);
 120         mtsdr(SDR0_PFC1, sdr0_pfc1);
 121
 122         /* PCI arbiter enabled */
 123         mfsdr(sdr_pci0, reg);
 124         mtsdr(sdr_pci0, 0x80000000 | reg);
 125
 126         /* setup NAND FLASH */
 127         mfsdr(SDR0_CUST0, sdr0_cust0);
 128         sdr0_cust0 = SDR0_CUST0_MUX_NDFC_SEL    |
 129                 SDR0_CUST0_NDFC_ENABLE          |
 130                 SDR0_CUST0_NDFC_BW_8_BIT        |
 131                 SDR0_CUST0_NDFC_ARE_MASK        |
 132                 (0x80000000 >> (28 + CFG_NAND_CS));
 133         mtsdr(SDR0_CUST0, sdr0_cust0);
 134
 135         /* Update EBC speed after booting from i2c bootstrap settings
 136          * on newer boards with 33.333 MHZ Clocks
 137          */
 138         if (in8(CFG_BCSR_BASE + 3) & 0x80)
 139                 mtcpr(0xe0, 0x02000000);
 140
 141         return 0;
 142 }
 143
 144 /*---------------------------------------------------------------------------+
 145   | misc_init_r.
 146   +---------------------------------------------------------------------------*/
 147 int misc_init_r(void)
 148 {
 149         uint pbcr;
 150         int size_val = 0;
 151         u32 reg;
 152 #ifdef CONFIG_440EPX
 153         unsigned long usb2d0cr = 0;
 154         unsigned long usb2phy0cr, usb2h0cr = 0;
 155         unsigned long sdr0_pfc1;
 156         char *act = getenv("usbact");
 157 #endif
 158
 159         /*
 160          * FLASH stuff...
 161          */
 162
 163         /* Re-do sizing to get full correct info */
 164
 165         /* adjust flash start and offset */
 166         gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
 167         gd->bd->bi_flashoffset = 0;
 168
 169 #if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
 170         mtdcr(ebccfga, pb3cr);
 171 #else
 172         mtdcr(ebccfga, pb0cr);
 173 #endif
 174         pbcr = mfdcr(ebccfgd);
 175         switch (gd->bd->bi_flashsize) {
 176         case 1 << 20:
 177                 size_val = 0;
 178                 break;
 179         case 2 << 20:
 180                 size_val = 1;
 181                 break;
 182         case 4 << 20:
 183                 size_val = 2;
 184                 break;
 185         case 8 << 20:
 186                 size_val = 3;
 187                 break;
 188         case 16 << 20:
 189                 size_val = 4;
 190                 break;
 191         case 32 << 20:
 192                 size_val = 5;
 193                 break;
 194         case 64 << 20:
 195                 size_val = 6;
 196                 break;
 197         case 128 << 20:
 198                 size_val = 7;
 199                 break;
 200         }
 201         pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17);
 202 #if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
 203         mtdcr(ebccfga, pb3cr);
 204 #else
 205         mtdcr(ebccfga, pb0cr);
 206 #endif
 207         mtdcr(ebccfgd, pbcr);
 208
 209         /*
 210          * Re-check to get correct base address
 211          */
 212         flash_get_size(gd->bd->bi_flashstart, 0);
 213
 214 #ifdef CFG_ENV_IS_IN_FLASH
 215         /* Monitor protection ON by default */
 216         (void)flash_protect(FLAG_PROTECT_SET,
 217                             -CFG_MONITOR_LEN,
 218                             0xffffffff,
 219                             &flash_info[0]);
 220
 221         /* Env protection ON by default */
 222         (void)flash_protect(FLAG_PROTECT_SET,
 223                             CFG_ENV_ADDR_REDUND,
 224                             CFG_ENV_ADDR_REDUND + 2*CFG_ENV_SECT_SIZE - 1,
 225                             &flash_info[0]);
 226 #endif
 227
 228         /*
 229          * USB suff...
 230          */
 231 #ifdef CONFIG_440EPX
 232         if (act == NULL || strcmp(act, "hostdev") == 0) {
 233                 /* SDR Setting */
 234                 mfsdr(SDR0_PFC1, sdr0_pfc1);
 235                 mfsdr(SDR0_USB0, usb2d0cr);
 236                 mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
 237                 mfsdr(SDR0_USB2H0CR, usb2h0cr);
 238
 239                 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK;
 240                 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL;       /*0*/
 241                 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_WDINT_MASK;
 242                 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_16BIT_30MHZ;    /*1*/
 243                 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK;
 244                 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS;         /*0*/
 245                 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK;
 246                 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST;          /*1*/
 247                 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK;
 248                 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST;          /*1*/
 249
 250                 /* An 8-bit/60MHz interface is the only possible alternative
 251                    when connecting the Device to the PHY */
 252                 usb2h0cr   = usb2h0cr &~SDR0_USB2H0CR_WDINT_MASK;
 253                 usb2h0cr   = usb2h0cr | SDR0_USB2H0CR_WDINT_16BIT_30MHZ;        /*1*/
 254
 255                 /* To enable the USB 2.0 Device function through the UTMI interface */
 256                 usb2d0cr = usb2d0cr &~SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK;
 257                 usb2d0cr = usb2d0cr | SDR0_USB2D0CR_USB2DEV_SELECTION;          /*1*/
 258
 259                 sdr0_pfc1 = sdr0_pfc1 &~SDR0_PFC1_UES_MASK;
 260                 sdr0_pfc1 = sdr0_pfc1 | SDR0_PFC1_UES_USB2D_SEL;                /*0*/
 261
 262                 mtsdr(SDR0_PFC1, sdr0_pfc1);
 263                 mtsdr(SDR0_USB0, usb2d0cr);
 264                 mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
 265                 mtsdr(SDR0_USB2H0CR, usb2h0cr);
 266
 267                 /*clear resets*/
 268                 udelay (1000);
 269                 mtsdr(SDR0_SRST1, 0x00000000);
 270                 udelay (1000);
 271                 mtsdr(SDR0_SRST0, 0x00000000);
 272
 273                 printf("USB:   Host(int phy) Device(ext phy)\n");
 274
 275         } else if (strcmp(act, "dev") == 0) {
 276                 /*-------------------PATCH-------------------------------*/
 277                 mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
 278
 279                 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK;
 280                 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL;       /*0*/
 281                 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK;
 282                 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS;         /*0*/
 283                 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK;
 284                 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST;          /*1*/
 285                 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK;
 286                 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST;          /*1*/
 287                 mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
 288
 289                 udelay (1000);
 290                 mtsdr(SDR0_SRST1, 0x672c6000);
 291
 292                 udelay (1000);
 293                 mtsdr(SDR0_SRST0, 0x00000080);
 294
 295                 udelay (1000);
 296                 mtsdr(SDR0_SRST1, 0x60206000);
 297
 298                 *(unsigned int *)(0xe0000350) = 0x00000001;
 299
 300                 udelay (1000);
 301                 mtsdr(SDR0_SRST1, 0x60306000);
 302                 /*-------------------PATCH-------------------------------*/
 303
 304                 /* SDR Setting */
 305                 mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
 306                 mfsdr(SDR0_USB2H0CR, usb2h0cr);
 307                 mfsdr(SDR0_USB0, usb2d0cr);
 308                 mfsdr(SDR0_PFC1, sdr0_pfc1);
 309
 310                 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK;
 311                 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL;       /*0*/
 312                 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_WDINT_MASK;
 313                 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_8BIT_60MHZ;     /*0*/
 314                 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK;
 315                 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PUREN;          /*1*/
 316                 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK;
 317                 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_DEV;           /*0*/
 318                 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK;
 319                 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_DEV;           /*0*/
 320
 321                 usb2h0cr   = usb2h0cr &~SDR0_USB2H0CR_WDINT_MASK;
 322                 usb2h0cr   = usb2h0cr | SDR0_USB2H0CR_WDINT_8BIT_60MHZ;         /*0*/
 323
 324                 usb2d0cr = usb2d0cr &~SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK;
 325                 usb2d0cr = usb2d0cr | SDR0_USB2D0CR_EBC_SELECTION;              /*0*/
 326
 327                 sdr0_pfc1 = sdr0_pfc1 &~SDR0_PFC1_UES_MASK;
 328                 sdr0_pfc1 = sdr0_pfc1 | SDR0_PFC1_UES_EBCHR_SEL;                /*1*/
 329
 330                 mtsdr(SDR0_USB2H0CR, usb2h0cr);
 331                 mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
 332                 mtsdr(SDR0_USB0, usb2d0cr);
 333                 mtsdr(SDR0_PFC1, sdr0_pfc1);
 334
 335                 /*clear resets*/
 336                 udelay (1000);
 337                 mtsdr(SDR0_SRST1, 0x00000000);
 338                 udelay (1000);
 339                 mtsdr(SDR0_SRST0, 0x00000000);
 340
 341                 printf("USB:   Device(int phy)\n");
 342         }
 343 #endif /* CONFIG_440EPX */
 344
 345         mfsdr(SDR0_SRST1, reg);         /* enable security/kasumi engines */
 346         reg &= ~(SDR0_SRST1_CRYP0 | SDR0_SRST1_KASU0);
 347         mtsdr(SDR0_SRST1, reg);
 348
 349         /*
 350          * Clear PLB4A0_ACR[WRP]
 351          * This fix will make the MAL burst disabling patch for the Linux
 352          * EMAC driver obsolete.
 353          */
 354         reg = mfdcr(plb4_acr) & ~PLB4_ACR_WRP;
 355         mtdcr(plb4_acr, reg);
 356
 357         return 0;
 358 }
 359
 360 int checkboard(void)
 361 {
 362         char *s = getenv("serial#");
 363         u8 rev;
 364         u8 val;
 365
 366 #ifdef CONFIG_440EPX
 367         printf("Board: Sequoia - AMCC PPC440EPx Evaluation Board");
 368 #else
 369         printf("Board: Rainier - AMCC PPC440GRx Evaluation Board");
 370 #endif
 371
 372         rev = in8(CFG_BCSR_BASE + 0);
 373         val = in8(CFG_BCSR_BASE + 5) & 0x01;
 374         printf(", Rev. %X, PCI=%d MHz", rev, val ? 66 : 33);
 375
 376         if (s != NULL) {
 377                 puts(", serial# ");
 378                 puts(s);
 379         }
 380         putc('\n');
 381
 382         return (0);
 383 }
 384
 385 #if defined(CFG_DRAM_TEST)
 386 int testdram(void)
 387 {
 388         unsigned long *mem = (unsigned long *)0;
 389         const unsigned long kend = (1024 / sizeof(unsigned long));
 390         unsigned long k, n;
 391
 392         mtmsr(0);
 393
 394         for (k = 0; k < CFG_MBYTES_SDRAM;
 395              ++k, mem += (1024 / sizeof(unsigned long))) {
 396                 if ((k & 1023) == 0) {
 397                         printf("%3d MB\r", k / 1024);
 398                 }
 399
 400                 memset(mem, 0xaaaaaaaa, 1024);
 401                 for (n = 0; n < kend; ++n) {
 402                         if (mem[n] != 0xaaaaaaaa) {
 403                                 printf("SDRAM test fails at: %08x\n",
 404                                        (uint) & mem[n]);
 405                                 return 1;
 406                         }
 407                 }
 408
 409                 memset(mem, 0x55555555, 1024);
 410                 for (n = 0; n < kend; ++n) {
 411                         if (mem[n] != 0x55555555) {
 412                                 printf("SDRAM test fails at: %08x\n",
 413                                        (uint) & mem[n]);
 414                                 return 1;
 415                         }
 416                 }
 417         }
 418         printf("SDRAM test passes\n");
 419         return 0;
 420 }
 421 #endif
 422
 423 /*************************************************************************
 424  *  pci_pre_init
 425  *
 426  *  This routine is called just prior to registering the hose and gives
 427  *  the board the opportunity to check things. Returning a value of zero
 428  *  indicates that things are bad & PCI initialization should be aborted.
 429  *
 430  *      Different boards may wish to customize the pci controller structure
 431  *      (add regions, override default access routines, etc) or perform
 432  *      certain pre-initialization actions.
 433  *
 434  ************************************************************************/
 435 #if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT)
 436 int pci_pre_init(struct pci_controller *hose)
 437 {
 438         unsigned long addr;
 439 #if 0
 440         /*--------------------------------------------------------------------------+
 441          *      Cactus is always configured as the host & requires the
 442          *      PCI arbiter to be enabled ???
 443          *--------------------------------------------------------------------------*/
 444         unsigned long strap;
 445         mfsdr(sdr_sdstp1, strap);
 446         if ((strap & SDR0_SDSTP1_PAE_MASK) == 0) {
 447                 printf("PCI: SDR0_STRP1[PAE] not set.\n");
 448                 printf("PCI: Configuration aborted.\n");
 449                 return 0;
 450         }
 451 #endif
 452
 453         /*-------------------------------------------------------------------------+
 454           | Set priority for all PLB3 devices to 0.
 455           | Set PLB3 arbiter to fair mode.
 456           +-------------------------------------------------------------------------*/
 457         mfsdr(sdr_amp1, addr);
 458         mtsdr(sdr_amp1, (addr & 0x000000FF) | 0x0000FF00);
 459         addr = mfdcr(plb3_acr);
 460         mtdcr(plb3_acr, addr | 0x80000000);
 461
 462         /*-------------------------------------------------------------------------+
 463           | Set priority for all PLB4 devices to 0.
 464           +-------------------------------------------------------------------------*/
 465         mfsdr(sdr_amp0, addr);
 466         mtsdr(sdr_amp0, (addr & 0x000000FF) | 0x0000FF00);
 467         addr = mfdcr(plb4_acr) | 0xa0000000;    /* Was 0x8---- */
 468         mtdcr(plb4_acr, addr);
 469
 470         /*-------------------------------------------------------------------------+
 471           | Set Nebula PLB4 arbiter to fair mode.
 472           +-------------------------------------------------------------------------*/
 473         /* Segment0 */
 474         addr = (mfdcr(plb0_acr) & ~plb0_acr_ppm_mask) | plb0_acr_ppm_fair;
 475         addr = (addr & ~plb0_acr_hbu_mask) | plb0_acr_hbu_enabled;
 476         addr = (addr & ~plb0_acr_rdp_mask) | plb0_acr_rdp_4deep;
 477         addr = (addr & ~plb0_acr_wrp_mask) | plb0_acr_wrp_2deep;
 478         mtdcr(plb0_acr, addr);
 479
 480         /* Segment1 */
 481         addr = (mfdcr(plb1_acr) & ~plb1_acr_ppm_mask) | plb1_acr_ppm_fair;
 482         addr = (addr & ~plb1_acr_hbu_mask) | plb1_acr_hbu_enabled;
 483         addr = (addr & ~plb1_acr_rdp_mask) | plb1_acr_rdp_4deep;
 484         addr = (addr & ~plb1_acr_wrp_mask) | plb1_acr_wrp_2deep;
 485         mtdcr(plb1_acr, addr);
 486
 487         return 1;
 488 }
 489 #endif                          /* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */
 490
 491 /*************************************************************************
 492  *  pci_target_init
 493  *
 494  *      The bootstrap configuration provides default settings for the pci
 495  *      inbound map (PIM). But the bootstrap config choices are limited and
 496  *      may not be sufficient for a given board.
 497  *
 498  ************************************************************************/
 499 #if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
 500 void pci_target_init(struct pci_controller *hose)
 501 {
 502         /*--------------------------------------------------------------------------+
 503          * Set up Direct MMIO registers
 504          *--------------------------------------------------------------------------*/
 505         /*--------------------------------------------------------------------------+
 506           | PowerPC440EPX PCI Master configuration.
 507           | Map one 1Gig range of PLB/processor addresses to PCI memory space.
 508           |   PLB address 0xA0000000-0xDFFFFFFF ==> PCI address 0xA0000000-0xDFFFFFFF
 509           |   Use byte reversed out routines to handle endianess.
 510           | Make this region non-prefetchable.
 511           +--------------------------------------------------------------------------*/
 512         out32r(PCIX0_PMM0MA, 0x00000000);       /* PMM0 Mask/Attribute - disabled b4 setting */
 513         out32r(PCIX0_PMM0LA, CFG_PCI_MEMBASE);  /* PMM0 Local Address */
 514         out32r(PCIX0_PMM0PCILA, CFG_PCI_MEMBASE);       /* PMM0 PCI Low Address */
 515         out32r(PCIX0_PMM0PCIHA, 0x00000000);    /* PMM0 PCI High Address */
 516         out32r(PCIX0_PMM0MA, 0xE0000001);       /* 512M + No prefetching, and enable region */
 517
 518         out32r(PCIX0_PMM1MA, 0x00000000);       /* PMM0 Mask/Attribute - disabled b4 setting */
 519         out32r(PCIX0_PMM1LA, CFG_PCI_MEMBASE2); /* PMM0 Local Address */
 520         out32r(PCIX0_PMM1PCILA, CFG_PCI_MEMBASE2);      /* PMM0 PCI Low Address */
 521         out32r(PCIX0_PMM1PCIHA, 0x00000000);    /* PMM0 PCI High Address */
 522         out32r(PCIX0_PMM1MA, 0xE0000001);       /* 512M + No prefetching, and enable region */
 523
 524         out32r(PCIX0_PTM1MS, 0x00000001);       /* Memory Size/Attribute */
 525         out32r(PCIX0_PTM1LA, 0);        /* Local Addr. Reg */
 526         out32r(PCIX0_PTM2MS, 0);        /* Memory Size/Attribute */
 527         out32r(PCIX0_PTM2LA, 0);        /* Local Addr. Reg */
 528
 529         /*--------------------------------------------------------------------------+
 530          * Set up Configuration registers
 531          *--------------------------------------------------------------------------*/
 532
 533         /* Program the board's subsystem id/vendor id */
 534         pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID,
 535                               CFG_PCI_SUBSYS_VENDORID);
 536         pci_write_config_word(0, PCI_SUBSYSTEM_ID, CFG_PCI_SUBSYS_ID);
 537
 538         /* Configure command register as bus master */
 539         pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER);
 540
 541         /* 240nS PCI clock */
 542         pci_write_config_word(0, PCI_LATENCY_TIMER, 1);
 543
 544         /* No error reporting */
 545         pci_write_config_word(0, PCI_ERREN, 0);
 546
 547         pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101);
 548
 549 }
 550 #endif                          /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */
 551
 552 /*************************************************************************
 553  *  pci_master_init
 554  *
 555  ************************************************************************/
 556 #if defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT)
 557 void pci_master_init(struct pci_controller *hose)
 558 {
 559         unsigned short temp_short;
 560
 561         /*--------------------------------------------------------------------------+
 562           | Write the PowerPC440 EP PCI Configuration regs.
 563           |   Enable PowerPC440 EP to be a master on the PCI bus (PMM).
 564           |   Enable PowerPC440 EP to act as a PCI memory target (PTM).
 565           +--------------------------------------------------------------------------*/
 566         pci_read_config_word(0, PCI_COMMAND, &temp_short);
 567         pci_write_config_word(0, PCI_COMMAND,
 568                               temp_short | PCI_COMMAND_MASTER |
 569                               PCI_COMMAND_MEMORY);
 570 }
 571 #endif                          /* defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT) */
 572
 573 /*************************************************************************
 574  *  is_pci_host
 575  *
 576  *      This routine is called to determine if a pci scan should be
 577  *      performed. With various hardware environments (especially cPCI and
 578  *      PPMC) it's insufficient to depend on the state of the arbiter enable
 579  *      bit in the strap register, or generic host/adapter assumptions.
 580  *
 581  *      Rather than hard-code a bad assumption in the general 440 code, the
 582  *      440 pci code requires the board to decide at runtime.
 583  *
 584  *      Return 0 for adapter mode, non-zero for host (monarch) mode.
 585  *
 586  *
 587  ************************************************************************/
 588 #if defined(CONFIG_PCI)
 589 int is_pci_host(struct pci_controller *hose)
 590 {
 591         /* Cactus is always configured as host. */
 592         return (1);
 593 }
 594 #endif                          /* defined(CONFIG_PCI) */