2 * (C) Copyright 2006-2007
3 * Stefan Roese, DENX Software Engineering, sr@denx.de.
6 * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com
7 * Alain Saurel, AMCC/IBM, alain.saurel@fr.ibm.com
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 #include <fdt_support.h>
30 #include <asm/processor.h>
32 #include <asm/bitops.h>
34 DECLARE_GLOBAL_DATA_PTR;
36 extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
38 ulong flash_get_size (ulong base, int banknum);
40 int board_early_init_f(void)
43 u32 sdr0_pfc1, sdr0_pfc2;
46 mtdcr(ebccfga, xbcfg);
47 mtdcr(ebccfgd, 0xb8400000);
50 * Setup the interrupt controller polarities, triggers, etc.
52 mtdcr(uic0sr, 0xffffffff); /* clear all */
53 mtdcr(uic0er, 0x00000000); /* disable all */
54 mtdcr(uic0cr, 0x00000005); /* ATI & UIC1 crit are critical */
55 mtdcr(uic0pr, 0xfffff7ff); /* per ref-board manual */
56 mtdcr(uic0tr, 0x00000000); /* per ref-board manual */
57 mtdcr(uic0vr, 0x00000000); /* int31 highest, base=0x000 */
58 mtdcr(uic0sr, 0xffffffff); /* clear all */
60 mtdcr(uic1sr, 0xffffffff); /* clear all */
61 mtdcr(uic1er, 0x00000000); /* disable all */
62 mtdcr(uic1cr, 0x00000000); /* all non-critical */
63 mtdcr(uic1pr, 0xffffffff); /* per ref-board manual */
64 mtdcr(uic1tr, 0x00000000); /* per ref-board manual */
65 mtdcr(uic1vr, 0x00000000); /* int31 highest, base=0x000 */
66 mtdcr(uic1sr, 0xffffffff); /* clear all */
68 mtdcr(uic2sr, 0xffffffff); /* clear all */
69 mtdcr(uic2er, 0x00000000); /* disable all */
70 mtdcr(uic2cr, 0x00000000); /* all non-critical */
71 mtdcr(uic2pr, 0xffffffff); /* per ref-board manual */
72 mtdcr(uic2tr, 0x00000000); /* per ref-board manual */
73 mtdcr(uic2vr, 0x00000000); /* int31 highest, base=0x000 */
74 mtdcr(uic2sr, 0xffffffff); /* clear all */
77 out_8((u8 *) CFG_BCSR_BASE + 0x04, 0x00);
79 /* clear write protects */
80 out_8((u8 *) CFG_BCSR_BASE + 0x07, 0x00);
83 out_8((u8 *) CFG_BCSR_BASE + 0x08, 0x00);
85 /* enable USB device */
86 out_8((u8 *) CFG_BCSR_BASE + 0x09, 0x20);
88 /* select Ethernet (and optionally IIC1) pins */
89 mfsdr(SDR0_PFC1, sdr0_pfc1);
90 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SELECT_MASK) |
91 SDR0_PFC1_SELECT_CONFIG_4;
92 #ifdef CONFIG_I2C_MULTI_BUS
93 sdr0_pfc1 |= ((sdr0_pfc1 & ~SDR0_PFC1_SIS_MASK) | SDR0_PFC1_SIS_IIC1_SEL);
95 mfsdr(SDR0_PFC2, sdr0_pfc2);
96 sdr0_pfc2 = (sdr0_pfc2 & ~SDR0_PFC2_SELECT_MASK) |
97 SDR0_PFC2_SELECT_CONFIG_4;
98 mtsdr(SDR0_PFC2, sdr0_pfc2);
99 mtsdr(SDR0_PFC1, sdr0_pfc1);
101 /* PCI arbiter enabled */
102 mfsdr(sdr_pci0, reg);
103 mtsdr(sdr_pci0, 0x80000000 | reg);
105 /* setup NAND FLASH */
106 mfsdr(SDR0_CUST0, sdr0_cust0);
107 sdr0_cust0 = SDR0_CUST0_MUX_NDFC_SEL |
108 SDR0_CUST0_NDFC_ENABLE |
109 SDR0_CUST0_NDFC_BW_8_BIT |
110 SDR0_CUST0_NDFC_ARE_MASK |
111 (0x80000000 >> (28 + CFG_NAND_CS));
112 mtsdr(SDR0_CUST0, sdr0_cust0);
117 int misc_init_r(void)
123 unsigned long usb2d0cr = 0;
124 unsigned long usb2phy0cr, usb2h0cr = 0;
125 unsigned long sdr0_pfc1;
126 char *act = getenv("usbact");
129 /* Re-do flash sizing to get full correct info */
131 /* adjust flash start and offset */
132 gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
133 gd->bd->bi_flashoffset = 0;
135 #if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
136 mtdcr(ebccfga, pb3cr);
138 mtdcr(ebccfga, pb0cr);
140 pbcr = mfdcr(ebccfgd);
141 size_val = ffs(gd->bd->bi_flashsize) - 21;
142 pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17);
143 #if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
144 mtdcr(ebccfga, pb3cr);
146 mtdcr(ebccfga, pb0cr);
148 mtdcr(ebccfgd, pbcr);
151 * Re-check to get correct base address
153 flash_get_size(gd->bd->bi_flashstart, 0);
155 #ifdef CFG_ENV_IS_IN_FLASH
156 /* Monitor protection ON by default */
157 (void)flash_protect(FLAG_PROTECT_SET,
162 /* Env protection ON by default */
163 (void)flash_protect(FLAG_PROTECT_SET,
165 CFG_ENV_ADDR_REDUND + 2*CFG_ENV_SECT_SIZE - 1,
173 if (act == NULL || strcmp(act, "hostdev") == 0) {
175 mfsdr(SDR0_PFC1, sdr0_pfc1);
176 mfsdr(SDR0_USB2D0CR, usb2d0cr);
177 mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
178 mfsdr(SDR0_USB2H0CR, usb2h0cr);
180 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK;
181 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL;
182 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_WDINT_MASK;
183 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_16BIT_30MHZ;
184 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK;
185 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS;
186 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK;
187 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST;
188 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK;
189 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST;
192 * An 8-bit/60MHz interface is the only possible alternative
193 * when connecting the Device to the PHY
195 usb2h0cr = usb2h0cr &~SDR0_USB2H0CR_WDINT_MASK;
196 usb2h0cr = usb2h0cr | SDR0_USB2H0CR_WDINT_16BIT_30MHZ;
199 * To enable the USB 2.0 Device function
200 * through the UTMI interface
202 usb2d0cr = usb2d0cr &~SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK;
203 usb2d0cr = usb2d0cr | SDR0_USB2D0CR_USB2DEV_SELECTION;
205 sdr0_pfc1 = sdr0_pfc1 &~SDR0_PFC1_UES_MASK;
206 sdr0_pfc1 = sdr0_pfc1 | SDR0_PFC1_UES_USB2D_SEL;
208 mtsdr(SDR0_PFC1, sdr0_pfc1);
209 mtsdr(SDR0_USB2D0CR, usb2d0cr);
210 mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
211 mtsdr(SDR0_USB2H0CR, usb2h0cr);
215 mtsdr(SDR0_SRST1, 0x00000000);
217 mtsdr(SDR0_SRST0, 0x00000000);
219 printf("USB: Host(int phy) Device(ext phy)\n");
221 } else if (strcmp(act, "dev") == 0) {
222 /*-------------------PATCH-------------------------------*/
223 mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
225 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK;
226 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL;
227 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK;
228 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS;
229 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK;
230 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST;
231 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK;
232 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST;
233 mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
236 mtsdr(SDR0_SRST1, 0x672c6000);
239 mtsdr(SDR0_SRST0, 0x00000080);
242 mtsdr(SDR0_SRST1, 0x60206000);
244 *(unsigned int *)(0xe0000350) = 0x00000001;
247 mtsdr(SDR0_SRST1, 0x60306000);
248 /*-------------------PATCH-------------------------------*/
251 mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
252 mfsdr(SDR0_USB2H0CR, usb2h0cr);
253 mfsdr(SDR0_USB2D0CR, usb2d0cr);
254 mfsdr(SDR0_PFC1, sdr0_pfc1);
256 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK;
257 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL;
258 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_WDINT_MASK;
259 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_8BIT_60MHZ;
260 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK;
261 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PUREN;
262 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK;
263 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_DEV;
264 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK;
265 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_DEV;
267 usb2h0cr = usb2h0cr &~SDR0_USB2H0CR_WDINT_MASK;
268 usb2h0cr = usb2h0cr | SDR0_USB2H0CR_WDINT_8BIT_60MHZ;
270 usb2d0cr = usb2d0cr &~SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK;
271 usb2d0cr = usb2d0cr | SDR0_USB2D0CR_EBC_SELECTION;
273 sdr0_pfc1 = sdr0_pfc1 &~SDR0_PFC1_UES_MASK;
274 sdr0_pfc1 = sdr0_pfc1 | SDR0_PFC1_UES_EBCHR_SEL;
276 mtsdr(SDR0_USB2H0CR, usb2h0cr);
277 mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
278 mtsdr(SDR0_USB2D0CR, usb2d0cr);
279 mtsdr(SDR0_PFC1, sdr0_pfc1);
283 mtsdr(SDR0_SRST1, 0x00000000);
285 mtsdr(SDR0_SRST0, 0x00000000);
287 printf("USB: Device(int phy)\n");
289 #endif /* CONFIG_440EPX */
291 mfsdr(SDR0_SRST1, reg); /* enable security/kasumi engines */
292 reg &= ~(SDR0_SRST1_CRYP0 | SDR0_SRST1_KASU0);
293 mtsdr(SDR0_SRST1, reg);
296 * Clear PLB4A0_ACR[WRP]
297 * This fix will make the MAL burst disabling patch for the Linux
298 * EMAC driver obsolete.
300 reg = mfdcr(plb4_acr) & ~PLB4_ACR_WRP;
301 mtdcr(plb4_acr, reg);
308 char *s = getenv("serial#");
313 printf("Board: Sequoia - AMCC PPC440EPx Evaluation Board");
315 printf("Board: Rainier - AMCC PPC440GRx Evaluation Board");
318 rev = in_8((void *)(CFG_BCSR_BASE + 0));
319 val = in_8((void *)(CFG_BCSR_BASE + 5)) & CFG_BCSR5_PCI66EN;
320 printf(", Rev. %X, PCI=%d MHz", rev, val ? 66 : 33);
331 #if defined(CONFIG_PCI) && defined(CONFIG_PCI_PNP)
333 * Assign interrupts to PCI devices.
335 void sequoia_pci_fixup_irq(struct pci_controller *hose, pci_dev_t dev)
337 pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, VECNUM_EIRQ2);
344 * This routine is called just prior to registering the hose and gives
345 * the board the opportunity to check things. Returning a value of zero
346 * indicates that things are bad & PCI initialization should be aborted.
348 * Different boards may wish to customize the pci controller structure
349 * (add regions, override default access routines, etc) or perform
350 * certain pre-initialization actions.
352 #if defined(CONFIG_PCI)
353 int pci_pre_init(struct pci_controller *hose)
358 * Set priority for all PLB3 devices to 0.
359 * Set PLB3 arbiter to fair mode.
361 mfsdr(sdr_amp1, addr);
362 mtsdr(sdr_amp1, (addr & 0x000000FF) | 0x0000FF00);
363 addr = mfdcr(plb3_acr);
364 mtdcr(plb3_acr, addr | 0x80000000);
367 * Set priority for all PLB4 devices to 0.
369 mfsdr(sdr_amp0, addr);
370 mtsdr(sdr_amp0, (addr & 0x000000FF) | 0x0000FF00);
371 addr = mfdcr(plb4_acr) | 0xa0000000; /* Was 0x8---- */
372 mtdcr(plb4_acr, addr);
375 * Set Nebula PLB4 arbiter to fair mode.
378 addr = (mfdcr(plb0_acr) & ~plb0_acr_ppm_mask) | plb0_acr_ppm_fair;
379 addr = (addr & ~plb0_acr_hbu_mask) | plb0_acr_hbu_enabled;
380 addr = (addr & ~plb0_acr_rdp_mask) | plb0_acr_rdp_4deep;
381 addr = (addr & ~plb0_acr_wrp_mask) | plb0_acr_wrp_2deep;
382 mtdcr(plb0_acr, addr);
385 addr = (mfdcr(plb1_acr) & ~plb1_acr_ppm_mask) | plb1_acr_ppm_fair;
386 addr = (addr & ~plb1_acr_hbu_mask) | plb1_acr_hbu_enabled;
387 addr = (addr & ~plb1_acr_rdp_mask) | plb1_acr_rdp_4deep;
388 addr = (addr & ~plb1_acr_wrp_mask) | plb1_acr_wrp_2deep;
389 mtdcr(plb1_acr, addr);
391 #ifdef CONFIG_PCI_PNP
392 hose->fixup_irq = sequoia_pci_fixup_irq;
396 #endif /* defined(CONFIG_PCI) */
401 * The bootstrap configuration provides default settings for the pci
402 * inbound map (PIM). But the bootstrap config choices are limited and
403 * may not be sufficient for a given board.
405 #if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
406 void pci_target_init(struct pci_controller *hose)
409 * Set up Direct MMIO registers
412 * PowerPC440EPX PCI Master configuration.
413 * Map one 1Gig range of PLB/processor addresses to PCI memory space.
414 * PLB address 0xA0000000-0xDFFFFFFF
415 * ==> PCI address 0xA0000000-0xDFFFFFFF
416 * Use byte reversed out routines to handle endianess.
417 * Make this region non-prefetchable.
419 out32r(PCIX0_PMM0MA, 0x00000000); /* PMM0 Mask/Attribute */
420 /* - disabled b4 setting */
421 out32r(PCIX0_PMM0LA, CFG_PCI_MEMBASE); /* PMM0 Local Address */
422 out32r(PCIX0_PMM0PCILA, CFG_PCI_MEMBASE); /* PMM0 PCI Low Address */
423 out32r(PCIX0_PMM0PCIHA, 0x00000000); /* PMM0 PCI High Address */
424 out32r(PCIX0_PMM0MA, 0xE0000001); /* 512M + No prefetching, */
425 /* and enable region */
427 out32r(PCIX0_PMM1MA, 0x00000000); /* PMM0 Mask/Attribute */
428 /* - disabled b4 setting */
429 out32r(PCIX0_PMM1LA, CFG_PCI_MEMBASE2); /* PMM0 Local Address */
430 out32r(PCIX0_PMM1PCILA, CFG_PCI_MEMBASE2); /* PMM0 PCI Low Address */
431 out32r(PCIX0_PMM1PCIHA, 0x00000000); /* PMM0 PCI High Address */
432 out32r(PCIX0_PMM1MA, 0xE0000001); /* 512M + No prefetching, */
433 /* and enable region */
435 out32r(PCIX0_PTM1MS, 0x00000001); /* Memory Size/Attribute */
436 out32r(PCIX0_PTM1LA, 0); /* Local Addr. Reg */
437 out32r(PCIX0_PTM2MS, 0); /* Memory Size/Attribute */
438 out32r(PCIX0_PTM2LA, 0); /* Local Addr. Reg */
441 * Set up Configuration registers
444 /* Program the board's subsystem id/vendor id */
445 pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID,
446 CFG_PCI_SUBSYS_VENDORID);
447 pci_write_config_word(0, PCI_SUBSYSTEM_ID, CFG_PCI_SUBSYS_ID);
449 /* Configure command register as bus master */
450 pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER);
452 /* 240nS PCI clock */
453 pci_write_config_word(0, PCI_LATENCY_TIMER, 1);
455 /* No error reporting */
456 pci_write_config_word(0, PCI_ERREN, 0);
458 pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101);
461 #endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */
463 #if defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT)
464 void pci_master_init(struct pci_controller *hose)
466 unsigned short temp_short;
469 * Write the PowerPC440 EP PCI Configuration regs.
470 * Enable PowerPC440 EP to be a master on the PCI bus (PMM).
471 * Enable PowerPC440 EP to act as a PCI memory target (PTM).
473 pci_read_config_word(0, PCI_COMMAND, &temp_short);
474 pci_write_config_word(0, PCI_COMMAND,
475 temp_short | PCI_COMMAND_MASTER |
478 #endif /* defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT) */
483 * This routine is called to determine if a pci scan should be
484 * performed. With various hardware environments (especially cPCI and
485 * PPMC) it's insufficient to depend on the state of the arbiter enable
486 * bit in the strap register, or generic host/adapter assumptions.
488 * Rather than hard-code a bad assumption in the general 440 code, the
489 * 440 pci code requires the board to decide at runtime.
491 * Return 0 for adapter mode, non-zero for host (monarch) mode.
493 #if defined(CONFIG_PCI)
494 int is_pci_host(struct pci_controller *hose)
496 /* Cactus is always configured as host. */
499 #endif /* defined(CONFIG_PCI) */
501 #if defined(CONFIG_POST)
503 * Returns 1 if keys pressed to start the power-on long-running tests
504 * Called from board_init_f().
506 int post_hotkeys_pressed(void)
508 return 0; /* No hotkeys supported */
510 #endif /* CONFIG_POST */