3 * See file CREDITS for list of people who contributed to this
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; either version 2 of
9 * the License, or (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 #include <asm/processor.h>
25 #include <spd_sdram.h>
27 extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
29 int board_early_init_f(void)
33 /*--------------------------------------------------------------------
34 * Setup the external bus controller/chip selects
35 *-------------------------------------------------------------------*/
36 mtdcr(ebccfga, xbcfg);
38 mtdcr(ebccfgd, reg | 0x04000000); /* Set ATC */
40 mtebc(pb0ap, 0x03017300); /* FLASH/SRAM */
41 mtebc(pb0cr, 0xfc0da000); /* BAS=0xfc0 64MB r/w 16-bit */
43 mtebc(pb1ap, 0x00000000);
44 mtebc(pb1cr, 0x00000000);
46 mtebc(pb2ap, 0x04814500);
47 /*CPLD*/ mtebc(pb2cr, 0x80018000); /*BAS=0x800 1MB r/w 8-bit */
49 mtebc(pb3ap, 0x00000000);
50 mtebc(pb3cr, 0x00000000);
52 mtebc(pb4ap, 0x00000000);
53 mtebc(pb4cr, 0x00000000);
55 mtebc(pb5ap, 0x00000000);
56 mtebc(pb5cr, 0x00000000);
58 /*--------------------------------------------------------------------
59 * Setup the interrupt controller polarities, triggers, etc.
60 *-------------------------------------------------------------------*/
61 mtdcr(uic0sr, 0xffffffff); /* clear all */
62 mtdcr(uic0er, 0x00000000); /* disable all */
63 mtdcr(uic0cr, 0x00000009); /* ATI & UIC1 crit are critical */
64 mtdcr(uic0pr, 0xfffffe13); /* per ref-board manual */
65 mtdcr(uic0tr, 0x01c00008); /* per ref-board manual */
66 mtdcr(uic0vr, 0x00000001); /* int31 highest, base=0x000 */
67 mtdcr(uic0sr, 0xffffffff); /* clear all */
69 mtdcr(uic1sr, 0xffffffff); /* clear all */
70 mtdcr(uic1er, 0x00000000); /* disable all */
71 mtdcr(uic1cr, 0x00000000); /* all non-critical */
72 mtdcr(uic1pr, 0xffffe0ff); /* per ref-board manual */
73 mtdcr(uic1tr, 0x00ffc000); /* per ref-board manual */
74 mtdcr(uic1vr, 0x00000001); /* int31 highest, base=0x000 */
75 mtdcr(uic1sr, 0xffffffff); /* clear all */
77 /*--------------------------------------------------------------------
79 *-------------------------------------------------------------------*/
81 /*setup Address lines for flash sizes larger than 16Meg. */
82 out32(GPIO0_OSRL, in32(GPIO0_OSRL) | 0x40010000);
83 out32(GPIO0_TSRL, in32(GPIO0_TSRL) | 0x40010000);
84 out32(GPIO0_ISR1L, in32(GPIO0_ISR1L) | 0x40000000);
87 out32(GPIO0_TCR, in32(GPIO0_TCR) | 0xC080);
88 out32(GPIO0_TSRL, in32(GPIO0_TSRL) | 0x40);
89 out32(GPIO0_ISR1L, in32(GPIO0_ISR1L) | 0x55);
90 out32(GPIO0_OSRH, in32(GPIO0_OSRH) | 0x50004000);
91 out32(GPIO0_ISR1H, in32(GPIO0_ISR1H) | 0x00440000);
94 out32(GPIO1_TCR, in32(GPIO1_TCR) | 0x02000000);
95 out32(GPIO1_OSRL, in32(GPIO1_OSRL) | 0x00080000);
96 out32(GPIO1_ISR2L, in32(GPIO1_ISR2L) | 0x00010000);
98 /* external interrupts IRQ0...3 */
99 out32(GPIO1_TCR, in32(GPIO1_TCR) & ~0x0f000000);
100 out32(GPIO1_TSRL, in32(GPIO1_TSRL) & ~0x00005500);
101 out32(GPIO1_ISR1L, in32(GPIO1_ISR1L) | 0x00005500);
103 #if 0 /* test-only */
105 out32(GPIO1_TCR, in32(GPIO1_TCR) | 0xc0000000);
106 out32(GPIO1_OSRL, in32(GPIO1_OSRL) | 0x50000000);
107 out32(GPIO0_TCR, in32(GPIO0_TCR) | 0xf);
108 out32(GPIO0_OSRH, in32(GPIO0_OSRH) | 0xaa);
109 out32(GPIO0_ISR2H, in32(GPIO0_ISR2H) | 0x00000500);
112 /*--------------------------------------------------------------------
113 * Setup other serial configuration
114 *-------------------------------------------------------------------*/
115 mfsdr(sdr_pci0, reg);
116 mtsdr(sdr_pci0, 0x80000000 | reg); /* PCI arbiter enabled */
117 mtsdr(sdr_pfc0, 0x00003e00); /* Pin function */
118 mtsdr(sdr_pfc1, 0x00048000); /* Pin function: UART0 has 4 pins */
120 /*clear tmrclk divisor */
121 *(unsigned char *)(CFG_BCSR_BASE | 0x04) = 0x00;
124 *(unsigned char *)(CFG_BCSR_BASE | 0x08) = 0xf0;
126 #if 0 /* test-only */
127 /*enable usb 1.1 fs device and remove usb 2.0 reset */
128 *(unsigned char *)(CFG_BCSR_BASE | 0x09) = 0x00;
131 /*get rid of flash write protect */
132 *(unsigned char *)(CFG_BCSR_BASE | 0x07) = 0x40;
137 int misc_init_r (void)
139 DECLARE_GLOBAL_DATA_PTR;
143 /* Re-do sizing to get full correct info */
144 mtdcr(ebccfga, pb0cr);
145 pbcr = mfdcr(ebccfgd);
146 switch (gd->bd->bi_flashsize) {
172 pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17);
173 mtdcr(ebccfga, pb0cr);
174 mtdcr(ebccfgd, pbcr);
176 /* Monitor protection ON by default */
177 (void)flash_protect(FLAG_PROTECT_SET,
188 unsigned char *s = getenv("serial#");
190 get_sys_info(&sysinfo);
192 printf("Board: Yellowstone - AMCC PPC440GR Evaluation Board");
199 printf("\tVCO: %lu MHz\n", sysinfo.freqVCOMhz / 1000000);
200 printf("\tCPU: %lu MHz\n", sysinfo.freqProcessor / 1000000);
201 printf("\tPLB: %lu MHz\n", sysinfo.freqPLB / 1000000);
202 printf("\tOPB: %lu MHz\n", sysinfo.freqOPB / 1000000);
203 printf("\tEPB: %lu MHz\n", sysinfo.freqEPB / 1000000);
204 printf("\tPCI: %lu MHz\n", sysinfo.freqPCI / 1000000);
209 /*************************************************************************
210 * sdram_init -- doesn't use serial presence detect.
212 * Assumes: 256 MB, ECC, non-registered
215 ************************************************************************/
216 void sdram_init(void)
220 /*--------------------------------------------------------------------
222 *------------------------------------------------------------------*/
223 mtsdram(mem_uabba, 0x00000000); /* ubba=0 (default) */
224 mtsdram(mem_slio, 0x00000000); /* rdre=0 wrre=0 rarw=0 */
225 mtsdram(mem_devopt, 0x00000000); /* dll=0 ds=0 (normal) */
226 mtsdram(mem_clktr, 0x40000000); /* ?? */
227 mtsdram(mem_wddctr, 0x40000000); /* ?? */
229 /*clear this first, if the DDR is enabled by a debugger
230 then you can not make changes. */
231 mtsdram(mem_cfg0, 0x00000000); /* Disable EEC */
233 /*--------------------------------------------------------------------
234 * Setup for board-specific specific mem
235 *------------------------------------------------------------------*/
237 * Following for CAS Latency = 2.5 @ 133 MHz PLB
239 mtsdram(mem_b0cr, 0x000a4001); /* SDBA=0x000 128MB, Mode 3, enabled */
240 mtsdram(mem_b1cr, 0x080a4001); /* SDBA=0x080 128MB, Mode 3, enabled */
242 mtsdram(mem_tr0, 0x410a4012); /* ?? */
243 mtsdram(mem_tr1, 0x8080080b); /* ?? */
244 mtsdram(mem_rtr, 0x04080000); /* ?? */
245 mtsdram(mem_cfg1, 0x00000000); /* Self-refresh exit, disable PM */
246 mtsdram(mem_cfg0, 0x34000000); /* Disable EEC */
247 udelay(400); /* Delay 200 usecs (min) */
249 /*--------------------------------------------------------------------
250 * Enable the controller, then wait for DCEN to complete
251 *------------------------------------------------------------------*/
252 mtsdram(mem_cfg0, 0x84000000); /* Enable */
255 mfsdram(mem_mcsts, reg);
256 if (reg & 0x80000000)
261 /*************************************************************************
264 ************************************************************************/
265 long int initdram(int board)
268 return CFG_SDRAM_BANKS * (CFG_KBYTES_SDRAM * 1024); /* return bytes */
271 #if defined(CFG_DRAM_TEST)
274 unsigned long *mem = (unsigned long *)0;
275 const unsigned long kend = (1024 / sizeof(unsigned long));
280 for (k = 0; k < CFG_KBYTES_SDRAM;
281 ++k, mem += (1024 / sizeof(unsigned long))) {
282 if ((k & 1023) == 0) {
283 printf("%3d MB\r", k / 1024);
286 memset(mem, 0xaaaaaaaa, 1024);
287 for (n = 0; n < kend; ++n) {
288 if (mem[n] != 0xaaaaaaaa) {
289 printf("SDRAM test fails at: %08x\n",
295 memset(mem, 0x55555555, 1024);
296 for (n = 0; n < kend; ++n) {
297 if (mem[n] != 0x55555555) {
298 printf("SDRAM test fails at: %08x\n",
304 printf("SDRAM test passes\n");
309 /*************************************************************************
312 * This routine is called just prior to registering the hose and gives
313 * the board the opportunity to check things. Returning a value of zero
314 * indicates that things are bad & PCI initialization should be aborted.
316 * Different boards may wish to customize the pci controller structure
317 * (add regions, override default access routines, etc) or perform
318 * certain pre-initialization actions.
320 ************************************************************************/
321 #if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT)
322 int pci_pre_init(struct pci_controller *hose)
327 /*--------------------------------------------------------------------------+
328 * Bamboo is always configured as the host & requires the
329 * PCI arbiter to be enabled.
330 *--------------------------------------------------------------------------*/
331 mfsdr(sdr_sdstp1, strap);
332 if ((strap & SDR0_SDSTP1_PAE_MASK) == 0) {
333 printf("PCI: SDR0_STRP1[PAE] not set.\n");
334 printf("PCI: Configuration aborted.\n");
338 /*-------------------------------------------------------------------------+
339 | Set priority for all PLB3 devices to 0.
340 | Set PLB3 arbiter to fair mode.
341 +-------------------------------------------------------------------------*/
342 mfsdr(sdr_amp1, addr);
343 mtsdr(sdr_amp1, (addr & 0x000000FF) | 0x0000FF00);
344 addr = mfdcr(plb3_acr);
345 mtdcr(plb3_acr, addr | 0x80000000);
347 /*-------------------------------------------------------------------------+
348 | Set priority for all PLB4 devices to 0.
349 +-------------------------------------------------------------------------*/
350 mfsdr(sdr_amp0, addr);
351 mtsdr(sdr_amp0, (addr & 0x000000FF) | 0x0000FF00);
352 addr = mfdcr(plb4_acr) | 0xa0000000; /* Was 0x8---- */
353 mtdcr(plb4_acr, addr);
355 /*-------------------------------------------------------------------------+
356 | Set Nebula PLB4 arbiter to fair mode.
357 +-------------------------------------------------------------------------*/
359 addr = (mfdcr(plb0_acr) & ~plb0_acr_ppm_mask) | plb0_acr_ppm_fair;
360 addr = (addr & ~plb0_acr_hbu_mask) | plb0_acr_hbu_enabled;
361 addr = (addr & ~plb0_acr_rdp_mask) | plb0_acr_rdp_4deep;
362 addr = (addr & ~plb0_acr_wrp_mask) | plb0_acr_wrp_2deep;
363 mtdcr(plb0_acr, addr);
366 addr = (mfdcr(plb1_acr) & ~plb1_acr_ppm_mask) | plb1_acr_ppm_fair;
367 addr = (addr & ~plb1_acr_hbu_mask) | plb1_acr_hbu_enabled;
368 addr = (addr & ~plb1_acr_rdp_mask) | plb1_acr_rdp_4deep;
369 addr = (addr & ~plb1_acr_wrp_mask) | plb1_acr_wrp_2deep;
370 mtdcr(plb1_acr, addr);
374 #endif /* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */
376 /*************************************************************************
379 * The bootstrap configuration provides default settings for the pci
380 * inbound map (PIM). But the bootstrap config choices are limited and
381 * may not be sufficient for a given board.
383 ************************************************************************/
384 #if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
385 void pci_target_init(struct pci_controller *hose)
387 /*--------------------------------------------------------------------------+
388 * Set up Direct MMIO registers
389 *--------------------------------------------------------------------------*/
390 /*--------------------------------------------------------------------------+
391 | PowerPC440 EP PCI Master configuration.
392 | Map one 1Gig range of PLB/processor addresses to PCI memory space.
393 | PLB address 0xA0000000-0xDFFFFFFF ==> PCI address 0xA0000000-0xDFFFFFFF
394 | Use byte reversed out routines to handle endianess.
395 | Make this region non-prefetchable.
396 +--------------------------------------------------------------------------*/
397 out32r(PCIX0_PMM0MA, 0x00000000); /* PMM0 Mask/Attribute - disabled b4 setting */
398 out32r(PCIX0_PMM0LA, CFG_PCI_MEMBASE); /* PMM0 Local Address */
399 out32r(PCIX0_PMM0PCILA, CFG_PCI_MEMBASE); /* PMM0 PCI Low Address */
400 out32r(PCIX0_PMM0PCIHA, 0x00000000); /* PMM0 PCI High Address */
401 out32r(PCIX0_PMM0MA, 0xE0000001); /* 512M + No prefetching, and enable region */
403 out32r(PCIX0_PMM1MA, 0x00000000); /* PMM0 Mask/Attribute - disabled b4 setting */
404 out32r(PCIX0_PMM1LA, CFG_PCI_MEMBASE2); /* PMM0 Local Address */
405 out32r(PCIX0_PMM1PCILA, CFG_PCI_MEMBASE2); /* PMM0 PCI Low Address */
406 out32r(PCIX0_PMM1PCIHA, 0x00000000); /* PMM0 PCI High Address */
407 out32r(PCIX0_PMM1MA, 0xE0000001); /* 512M + No prefetching, and enable region */
409 out32r(PCIX0_PTM1MS, 0x00000001); /* Memory Size/Attribute */
410 out32r(PCIX0_PTM1LA, 0); /* Local Addr. Reg */
411 out32r(PCIX0_PTM2MS, 0); /* Memory Size/Attribute */
412 out32r(PCIX0_PTM2LA, 0); /* Local Addr. Reg */
414 /*--------------------------------------------------------------------------+
415 * Set up Configuration registers
416 *--------------------------------------------------------------------------*/
418 /* Program the board's subsystem id/vendor id */
419 pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID,
420 CFG_PCI_SUBSYS_VENDORID);
421 pci_write_config_word(0, PCI_SUBSYSTEM_ID, CFG_PCI_SUBSYS_ID);
423 /* Configure command register as bus master */
424 pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER);
426 /* 240nS PCI clock */
427 pci_write_config_word(0, PCI_LATENCY_TIMER, 1);
429 /* No error reporting */
430 pci_write_config_word(0, PCI_ERREN, 0);
432 pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101);
435 #endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */
437 /*************************************************************************
440 ************************************************************************/
441 #if defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT)
442 void pci_master_init(struct pci_controller *hose)
444 unsigned short temp_short;
446 /*--------------------------------------------------------------------------+
447 | Write the PowerPC440 EP PCI Configuration regs.
448 | Enable PowerPC440 EP to be a master on the PCI bus (PMM).
449 | Enable PowerPC440 EP to act as a PCI memory target (PTM).
450 +--------------------------------------------------------------------------*/
451 pci_read_config_word(0, PCI_COMMAND, &temp_short);
452 pci_write_config_word(0, PCI_COMMAND,
453 temp_short | PCI_COMMAND_MASTER |
456 #endif /* defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT) */
458 /*************************************************************************
461 * This routine is called to determine if a pci scan should be
462 * performed. With various hardware environments (especially cPCI and
463 * PPMC) it's insufficient to depend on the state of the arbiter enable
464 * bit in the strap register, or generic host/adapter assumptions.
466 * Rather than hard-code a bad assumption in the general 440 code, the
467 * 440 pci code requires the board to decide at runtime.
469 * Return 0 for adapter mode, non-zero for host (monarch) mode.
472 ************************************************************************/
473 #if defined(CONFIG_PCI)
474 int is_pci_host(struct pci_controller *hose)
476 /* Bamboo is always configured as host. */
479 #endif /* defined(CONFIG_PCI) */
481 /*************************************************************************
484 * This routine is called to reset (keep alive) the watchdog timer
486 ************************************************************************/
487 #if defined(CONFIG_HW_WATCHDOG)
488 void hw_watchdog_reset(void)