2 * (C) Copyright 2006-2007
3 * Stefan Roese, DENX Software Engineering, sr@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 #include <asm/processor.h>
28 #include <spd_sdram.h>
30 #include <fdt_support.h>
32 DECLARE_GLOBAL_DATA_PTR;
34 extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
36 int board_early_init_f(void)
40 /*--------------------------------------------------------------------
41 * Setup the external bus controller/chip selects
42 *-------------------------------------------------------------------*/
43 mtdcr(ebccfga, xbcfg);
45 mtdcr(ebccfgd, reg | 0x04000000); /* Set ATC */
47 /*--------------------------------------------------------------------
49 *-------------------------------------------------------------------*/
51 /*setup Address lines for flash size 64Meg. */
52 out32(GPIO0_OSRL, in32(GPIO0_OSRL) | 0x50010000);
53 out32(GPIO0_TSRL, in32(GPIO0_TSRL) | 0x50010000);
54 out32(GPIO0_ISR1L, in32(GPIO0_ISR1L) | 0x50000000);
57 out32(GPIO0_TCR, in32(GPIO0_TCR) | 0xC080);
58 out32(GPIO0_TSRL, in32(GPIO0_TSRL) | 0x40);
59 out32(GPIO0_ISR1L, in32(GPIO0_ISR1L) | 0x55);
60 out32(GPIO0_OSRH, in32(GPIO0_OSRH) | 0x50004000);
61 out32(GPIO0_ISR1H, in32(GPIO0_ISR1H) | 0x00440000);
64 out32(GPIO1_TCR, in32(GPIO1_TCR) | 0x02000000);
65 out32(GPIO1_OSRL, in32(GPIO1_OSRL) | 0x00080000);
66 out32(GPIO1_ISR2L, in32(GPIO1_ISR2L) | 0x00010000);
68 /* external interrupts IRQ0...3 */
69 out32(GPIO1_TCR, in32(GPIO1_TCR) & ~0x00f00000);
70 out32(GPIO1_TSRL, in32(GPIO1_TSRL) & ~0x0000ff00);
71 out32(GPIO1_ISR1L, in32(GPIO1_ISR1L) | 0x00005500);
75 out32(GPIO1_TCR, in32(GPIO1_TCR) | 0xc0000000);
76 out32(GPIO1_OSRL, in32(GPIO1_OSRL) | 0x50000000);
77 out32(GPIO0_TCR, in32(GPIO0_TCR) | 0xf);
78 out32(GPIO0_OSRH, in32(GPIO0_OSRH) | 0xaa);
79 out32(GPIO0_ISR2H, in32(GPIO0_ISR2H) | 0x00000500);
82 /*--------------------------------------------------------------------
83 * Setup the interrupt controller polarities, triggers, etc.
84 *-------------------------------------------------------------------*/
85 mtdcr(uic0sr, 0xffffffff); /* clear all */
86 mtdcr(uic0er, 0x00000000); /* disable all */
87 mtdcr(uic0cr, 0x00000009); /* ATI & UIC1 crit are critical */
88 mtdcr(uic0pr, 0xfffffe13); /* per ref-board manual */
89 mtdcr(uic0tr, 0x01c00008); /* per ref-board manual */
90 mtdcr(uic0vr, 0x00000001); /* int31 highest, base=0x000 */
91 mtdcr(uic0sr, 0xffffffff); /* clear all */
93 mtdcr(uic1sr, 0xffffffff); /* clear all */
94 mtdcr(uic1er, 0x00000000); /* disable all */
95 mtdcr(uic1cr, 0x00000000); /* all non-critical */
96 mtdcr(uic1pr, 0xffffe0ff); /* per ref-board manual */
97 mtdcr(uic1tr, 0x00ffc000); /* per ref-board manual */
98 mtdcr(uic1vr, 0x00000001); /* int31 highest, base=0x000 */
99 mtdcr(uic1sr, 0xffffffff); /* clear all */
101 /*--------------------------------------------------------------------
102 * Setup other serial configuration
103 *-------------------------------------------------------------------*/
104 mfsdr(sdr_pci0, reg);
105 mtsdr(sdr_pci0, 0x80000000 | reg); /* PCI arbiter enabled */
106 mtsdr(sdr_pfc0, 0x00003e00); /* Pin function */
107 mtsdr(sdr_pfc1, 0x00048000); /* Pin function: UART0 has 4 pins */
109 /*clear tmrclk divisor */
110 *(unsigned char *)(CFG_BCSR_BASE | 0x04) = 0x00;
113 *(unsigned char *)(CFG_BCSR_BASE | 0x08) = 0xf0;
116 /*enable usb 1.1 fs device and remove usb 2.0 reset */
117 *(unsigned char *)(CFG_BCSR_BASE | 0x09) = 0x00;
120 /*get rid of flash write protect */
121 *(unsigned char *)(CFG_BCSR_BASE | 0x07) = 0x00;
126 int misc_init_r (void)
131 /* Re-do sizing to get full correct info */
132 mtdcr(ebccfga, pb0cr);
133 pbcr = mfdcr(ebccfgd);
134 switch (gd->bd->bi_flashsize) {
160 pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17);
161 mtdcr(ebccfga, pb0cr);
162 mtdcr(ebccfgd, pbcr);
164 /* adjust flash start and offset */
165 gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
166 gd->bd->bi_flashoffset = 0;
168 /* Monitor protection ON by default */
169 (void)flash_protect(FLAG_PROTECT_SET,
179 char *s = getenv("serial#");
184 printf("Board: Yosemite - AMCC PPC440EP Evaluation Board");
186 printf("Board: Yellowstone - AMCC PPC440GR Evaluation Board");
189 rev = in_8((void *)(CFG_BCSR_BASE + 0));
190 val = in_8((void *)(CFG_BCSR_BASE + 5)) & CFG_BCSR5_PCI66EN;
191 printf(", Rev. %X, PCI=%d MHz", rev, val ? 66 : 33);
202 /*************************************************************************
203 * initdram -- doesn't use serial presence detect.
205 * Assumes: 256 MB, ECC, non-registered
208 ************************************************************************/
212 void sdram_tr1_set(int ram_address, int* tr1_value)
216 volatile unsigned int* ram_pointer = (unsigned int*)ram_address;
217 int first_good = -1, last_bad = 0x1ff;
219 unsigned long test[NUM_TRIES] = {
220 0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
221 0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
222 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
223 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
224 0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,
225 0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,
226 0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,
227 0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,
228 0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A,
229 0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A,
230 0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5,
231 0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5,
232 0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA,
233 0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA,
234 0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55,
235 0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55 };
237 /* go through all possible SDRAM0_TR1[RDCT] values */
238 for (i=0; i<=0x1ff; i++) {
239 /* set the current value for TR1 */
240 mtsdram(mem_tr1, (0x80800800 | i));
243 for (j=0; j<NUM_TRIES; j++) {
244 ram_pointer[j] = test[j];
246 /* clear any cache at ram location */
247 __asm__("dcbf 0,%0": :"r" (&ram_pointer[j]));
250 /* read values back */
251 for (j=0; j<NUM_TRIES; j++) {
252 for (k=0; k<NUM_READS; k++) {
253 /* clear any cache at ram location */
254 __asm__("dcbf 0,%0": :"r" (&ram_pointer[j]));
256 if (ram_pointer[j] != test[j])
261 if (k != NUM_READS) {
266 /* we have a SDRAM0_TR1[RDCT] that is part of the window */
267 if (j == NUM_TRIES) {
268 if (first_good == -1)
269 first_good = i; /* found beginning of window */
270 } else { /* bad read */
271 /* if we have not had a good read then don't care */
272 if(first_good != -1) {
273 /* first failure after a good read */
280 /* return the current value for TR1 */
281 *tr1_value = (first_good + last_bad) / 2;
284 phys_size_t initdram(int board)
287 int tr1_bank1, tr1_bank2;
289 /*--------------------------------------------------------------------
291 *------------------------------------------------------------------*/
292 mtsdram(mem_uabba, 0x00000000); /* ubba=0 (default) */
293 mtsdram(mem_slio, 0x00000000); /* rdre=0 wrre=0 rarw=0 */
294 mtsdram(mem_devopt, 0x00000000); /* dll=0 ds=0 (normal) */
295 mtsdram(mem_clktr, 0x40000000); /* ?? */
296 mtsdram(mem_wddctr, 0x40000000); /* ?? */
298 /*clear this first, if the DDR is enabled by a debugger
299 then you can not make changes. */
300 mtsdram(mem_cfg0, 0x00000000); /* Disable EEC */
302 /*--------------------------------------------------------------------
303 * Setup for board-specific specific mem
304 *------------------------------------------------------------------*/
306 * Following for CAS Latency = 2.5 @ 133 MHz PLB
308 mtsdram(mem_b0cr, 0x000a4001); /* SDBA=0x000 128MB, Mode 3, enabled */
309 mtsdram(mem_b1cr, 0x080a4001); /* SDBA=0x080 128MB, Mode 3, enabled */
311 mtsdram(mem_tr0, 0x410a4012); /* ?? */
312 mtsdram(mem_rtr, 0x04080000); /* ?? */
313 mtsdram(mem_cfg1, 0x00000000); /* Self-refresh exit, disable PM */
314 mtsdram(mem_cfg0, 0x30000000); /* Disable EEC */
315 udelay(400); /* Delay 200 usecs (min) */
317 /*--------------------------------------------------------------------
318 * Enable the controller, then wait for DCEN to complete
319 *------------------------------------------------------------------*/
320 mtsdram(mem_cfg0, 0x80000000); /* Enable */
323 mfsdram(mem_mcsts, reg);
324 if (reg & 0x80000000)
328 sdram_tr1_set(0x00000000, &tr1_bank1);
329 sdram_tr1_set(0x08000000, &tr1_bank2);
330 mtsdram(mem_tr1, (((tr1_bank1+tr1_bank2)/2) | 0x80800800));
332 return CFG_SDRAM_BANKS * (CFG_KBYTES_SDRAM * 1024); /* return bytes */
335 /*************************************************************************
338 * This routine is called just prior to registering the hose and gives
339 * the board the opportunity to check things. Returning a value of zero
340 * indicates that things are bad & PCI initialization should be aborted.
342 * Different boards may wish to customize the pci controller structure
343 * (add regions, override default access routines, etc) or perform
344 * certain pre-initialization actions.
346 ************************************************************************/
347 #if defined(CONFIG_PCI)
348 int pci_pre_init(struct pci_controller *hose)
352 /*-------------------------------------------------------------------------+
353 | Set priority for all PLB3 devices to 0.
354 | Set PLB3 arbiter to fair mode.
355 +-------------------------------------------------------------------------*/
356 mfsdr(sdr_amp1, addr);
357 mtsdr(sdr_amp1, (addr & 0x000000FF) | 0x0000FF00);
358 addr = mfdcr(plb3_acr);
359 mtdcr(plb3_acr, addr | 0x80000000);
361 /*-------------------------------------------------------------------------+
362 | Set priority for all PLB4 devices to 0.
363 +-------------------------------------------------------------------------*/
364 mfsdr(sdr_amp0, addr);
365 mtsdr(sdr_amp0, (addr & 0x000000FF) | 0x0000FF00);
366 addr = mfdcr(plb4_acr) | 0xa0000000; /* Was 0x8---- */
367 mtdcr(plb4_acr, addr);
369 /*-------------------------------------------------------------------------+
370 | Set Nebula PLB4 arbiter to fair mode.
371 +-------------------------------------------------------------------------*/
373 addr = (mfdcr(plb0_acr) & ~plb0_acr_ppm_mask) | plb0_acr_ppm_fair;
374 addr = (addr & ~plb0_acr_hbu_mask) | plb0_acr_hbu_enabled;
375 addr = (addr & ~plb0_acr_rdp_mask) | plb0_acr_rdp_4deep;
376 addr = (addr & ~plb0_acr_wrp_mask) | plb0_acr_wrp_2deep;
377 mtdcr(plb0_acr, addr);
380 addr = (mfdcr(plb1_acr) & ~plb1_acr_ppm_mask) | plb1_acr_ppm_fair;
381 addr = (addr & ~plb1_acr_hbu_mask) | plb1_acr_hbu_enabled;
382 addr = (addr & ~plb1_acr_rdp_mask) | plb1_acr_rdp_4deep;
383 addr = (addr & ~plb1_acr_wrp_mask) | plb1_acr_wrp_2deep;
384 mtdcr(plb1_acr, addr);
388 #endif /* defined(CONFIG_PCI) */
390 /*************************************************************************
393 * The bootstrap configuration provides default settings for the pci
394 * inbound map (PIM). But the bootstrap config choices are limited and
395 * may not be sufficient for a given board.
397 ************************************************************************/
398 #if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
399 void pci_target_init(struct pci_controller *hose)
401 /*--------------------------------------------------------------------------+
402 * Set up Direct MMIO registers
403 *--------------------------------------------------------------------------*/
404 /*--------------------------------------------------------------------------+
405 | PowerPC440 EP PCI Master configuration.
406 | Map one 1Gig range of PLB/processor addresses to PCI memory space.
407 | PLB address 0xA0000000-0xDFFFFFFF ==> PCI address 0xA0000000-0xDFFFFFFF
408 | Use byte reversed out routines to handle endianess.
409 | Make this region non-prefetchable.
410 +--------------------------------------------------------------------------*/
411 out32r(PCIX0_PMM0MA, 0x00000000); /* PMM0 Mask/Attribute - disabled b4 setting */
412 out32r(PCIX0_PMM0LA, CFG_PCI_MEMBASE); /* PMM0 Local Address */
413 out32r(PCIX0_PMM0PCILA, CFG_PCI_MEMBASE); /* PMM0 PCI Low Address */
414 out32r(PCIX0_PMM0PCIHA, 0x00000000); /* PMM0 PCI High Address */
415 out32r(PCIX0_PMM0MA, 0xE0000001); /* 512M + No prefetching, and enable region */
417 out32r(PCIX0_PMM1MA, 0x00000000); /* PMM0 Mask/Attribute - disabled b4 setting */
418 out32r(PCIX0_PMM1LA, CFG_PCI_MEMBASE2); /* PMM0 Local Address */
419 out32r(PCIX0_PMM1PCILA, CFG_PCI_MEMBASE2); /* PMM0 PCI Low Address */
420 out32r(PCIX0_PMM1PCIHA, 0x00000000); /* PMM0 PCI High Address */
421 out32r(PCIX0_PMM1MA, 0xE0000001); /* 512M + No prefetching, and enable region */
423 out32r(PCIX0_PTM1MS, 0x00000001); /* Memory Size/Attribute */
424 out32r(PCIX0_PTM1LA, 0); /* Local Addr. Reg */
425 out32r(PCIX0_PTM2MS, 0); /* Memory Size/Attribute */
426 out32r(PCIX0_PTM2LA, 0); /* Local Addr. Reg */
428 /*--------------------------------------------------------------------------+
429 * Set up Configuration registers
430 *--------------------------------------------------------------------------*/
432 /* Program the board's subsystem id/vendor id */
433 pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID,
434 CFG_PCI_SUBSYS_VENDORID);
435 pci_write_config_word(0, PCI_SUBSYSTEM_ID, CFG_PCI_SUBSYS_ID);
437 /* Configure command register as bus master */
438 pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER);
440 /* 240nS PCI clock */
441 pci_write_config_word(0, PCI_LATENCY_TIMER, 1);
443 /* No error reporting */
444 pci_write_config_word(0, PCI_ERREN, 0);
446 pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101);
449 #endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */
451 /*************************************************************************
454 ************************************************************************/
455 #if defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT)
456 void pci_master_init(struct pci_controller *hose)
458 unsigned short temp_short;
460 /*--------------------------------------------------------------------------+
461 | Write the PowerPC440 EP PCI Configuration regs.
462 | Enable PowerPC440 EP to be a master on the PCI bus (PMM).
463 | Enable PowerPC440 EP to act as a PCI memory target (PTM).
464 +--------------------------------------------------------------------------*/
465 pci_read_config_word(0, PCI_COMMAND, &temp_short);
466 pci_write_config_word(0, PCI_COMMAND,
467 temp_short | PCI_COMMAND_MASTER |
470 #endif /* defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT) */
472 /*************************************************************************
475 * This routine is called to determine if a pci scan should be
476 * performed. With various hardware environments (especially cPCI and
477 * PPMC) it's insufficient to depend on the state of the arbiter enable
478 * bit in the strap register, or generic host/adapter assumptions.
480 * Rather than hard-code a bad assumption in the general 440 code, the
481 * 440 pci code requires the board to decide at runtime.
483 * Return 0 for adapter mode, non-zero for host (monarch) mode.
486 ************************************************************************/
487 #if defined(CONFIG_PCI)
488 int is_pci_host(struct pci_controller *hose)
490 /* Bamboo is always configured as host. */
493 #endif /* defined(CONFIG_PCI) */
495 /*************************************************************************
498 * This routine is called to reset (keep alive) the watchdog timer
500 ************************************************************************/
501 #if defined(CONFIG_HW_WATCHDOG)
502 void hw_watchdog_reset(void)
508 void board_reset(void)
510 /* give reset to BCSR */
511 *(unsigned char *)(CFG_BCSR_BASE | 0x06) = 0x09;
514 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
515 void ft_board_setup(void *blob, bd_t *bd)
520 ft_cpu_setup(blob, bd);
522 /* Fixup NOR mapping */
523 val[0] = 0; /* chip select number */
524 val[1] = 0; /* always 0 */
525 val[2] = gd->bd->bi_flashstart;
526 val[3] = gd->bd->bi_flashsize;
527 rc = fdt_find_and_setprop(blob, "/plb/opb/ebc", "ranges",
528 val, sizeof(val), 1);
530 printf("Unable to update property NOR mapping, err=%s\n",
533 #endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */