git.sur5r.net Git - u-boot/blob - board/atmel/at91sam9261ek/at91sam9261ek.c

   1 /*
   2  * (C) Copyright 2007-2008
   3  * Stelian Pop <stelian.pop@leadtechdesign.com>
   4  * Lead Tech Design <www.leadtechdesign.com>
   5  *
   6  * See file CREDITS for list of people who contributed to this
   7  * project.
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License as
  11  * published by the Free Software Foundation; either version 2 of
  12  * the License, or (at your option) any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22  * MA 02111-1307 USA
  23  */
  24
  25 #include <common.h>
  26 #include <asm/arch/at91sam9261.h>
  27 #include <asm/arch/at91sam9261_matrix.h>
  28 #include <asm/arch/at91sam9_smc.h>
  29 #include <asm/arch/at91_common.h>
  30 #include <asm/arch/at91_pmc.h>
  31 #include <asm/arch/at91_rstc.h>
  32 #include <asm/arch/gpio.h>
  33 #include <asm/arch/io.h>
  34 #include <lcd.h>
  35 #include <atmel_lcdc.h>
  36 #if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_DRIVER_DM9000)
  37 #include <net.h>
  38 #endif
  39
  40 DECLARE_GLOBAL_DATA_PTR;
  41
  42 /* ------------------------------------------------------------------------- */
  43 /*
  44  * Miscelaneous platform dependent initialisations
  45  */
  46
  47 #ifdef CONFIG_CMD_NAND
  48 static void at91sam9261ek_nand_hw_init(void)
  49 {
  50         unsigned long csa;
  51
  52         /* Enable CS3 */
  53         csa = at91_sys_read(AT91_MATRIX_EBICSA);
  54         at91_sys_write(AT91_MATRIX_EBICSA,
  55                        csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA);
  56
  57         /* Configure SMC CS3 for NAND/SmartMedia */
  58         at91_sys_write(AT91_SMC_SETUP(3),
  59                        AT91_SMC_NWESETUP_(1) | AT91_SMC_NCS_WRSETUP_(0) |
  60                        AT91_SMC_NRDSETUP_(1) | AT91_SMC_NCS_RDSETUP_(0));
  61         at91_sys_write(AT91_SMC_PULSE(3),
  62                        AT91_SMC_NWEPULSE_(3) | AT91_SMC_NCS_WRPULSE_(3) |
  63                        AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(3));
  64         at91_sys_write(AT91_SMC_CYCLE(3),
  65                        AT91_SMC_NWECYCLE_(5) | AT91_SMC_NRDCYCLE_(5));
  66         at91_sys_write(AT91_SMC_MODE(3),
  67                        AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
  68                        AT91_SMC_EXNWMODE_DISABLE |
  69 #ifdef CONFIG_SYS_NAND_DBW_16
  70                        AT91_SMC_DBW_16 |
  71 #else /* CONFIG_SYS_NAND_DBW_8 */
  72                        AT91_SMC_DBW_8 |
  73 #endif
  74                        AT91_SMC_TDF_(2));
  75
  76         at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9261_ID_PIOC);
  77
  78         /* Configure RDY/BSY */
  79         at91_set_gpio_input(AT91_PIN_PC15, 1);
  80
  81         /* Enable NandFlash */
  82         at91_set_gpio_output(AT91_PIN_PC14, 1);
  83
  84         at91_set_A_periph(AT91_PIN_PC0, 0);     /* NANDOE */
  85         at91_set_A_periph(AT91_PIN_PC1, 0);     /* NANDWE */
  86 }
  87 #endif
  88
  89 #ifdef CONFIG_HAS_DATAFLASH
  90 static void at91sam9261ek_spi_hw_init(void)
  91 {
  92         at91_set_A_periph(AT91_PIN_PA3, 0);     /* SPI0_NPCS0 */
  93
  94         at91_set_A_periph(AT91_PIN_PA0, 0);     /* SPI0_MISO */
  95         at91_set_A_periph(AT91_PIN_PA1, 0);     /* SPI0_MOSI */
  96         at91_set_A_periph(AT91_PIN_PA2, 0);     /* SPI0_SPCK */
  97
  98         /* Enable clock */
  99         at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9261_ID_SPI0);
 100 }
 101 #endif
 102
 103 #ifdef CONFIG_DRIVER_DM9000
 104 static void at91sam9261ek_dm9000_hw_init(void)
 105 {
 106         /* Configure SMC CS2 for DM9000 */
 107         at91_sys_write(AT91_SMC_SETUP(2),
 108                        AT91_SMC_NWESETUP_(2) | AT91_SMC_NCS_WRSETUP_(0) |
 109                        AT91_SMC_NRDSETUP_(2) | AT91_SMC_NCS_RDSETUP_(0));
 110         at91_sys_write(AT91_SMC_PULSE(2),
 111                        AT91_SMC_NWEPULSE_(4) | AT91_SMC_NCS_WRPULSE_(8) |
 112                        AT91_SMC_NRDPULSE_(4) | AT91_SMC_NCS_RDPULSE_(8));
 113         at91_sys_write(AT91_SMC_CYCLE(2),
 114                        AT91_SMC_NWECYCLE_(16) | AT91_SMC_NRDCYCLE_(16));
 115         at91_sys_write(AT91_SMC_MODE(2),
 116                        AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
 117                        AT91_SMC_EXNWMODE_DISABLE |
 118                        AT91_SMC_BAT_WRITE | AT91_SMC_DBW_16 |
 119                        AT91_SMC_TDF_(1));
 120
 121         /* Configure Reset signal as output */
 122         at91_set_gpio_output(AT91_PIN_PC10, 0);
 123
 124         /* Configure Interrupt pin as input, no pull-up */
 125         at91_set_gpio_input(AT91_PIN_PC11, 0);
 126 }
 127 #endif
 128
 129 #ifdef CONFIG_LCD
 130 vidinfo_t panel_info = {
 131         vl_col:         240,
 132         vl_row:         320,
 133         vl_clk:         4965000,
 134         vl_sync:        ATMEL_LCDC_INVLINE_INVERTED |
 135                         ATMEL_LCDC_INVFRAME_INVERTED,
 136         vl_bpix:        3,
 137         vl_tft:         1,
 138         vl_hsync_len:   5,
 139         vl_left_margin: 1,
 140         vl_right_margin:33,
 141         vl_vsync_len:   1,
 142         vl_upper_margin:1,
 143         vl_lower_margin:0,
 144         mmio:           AT91SAM9261_LCDC_BASE,
 145 };
 146
 147 void lcd_enable(void)
 148 {
 149         at91_set_gpio_value(AT91_PIN_PA12, 0);  /* power up */
 150 }
 151
 152 void lcd_disable(void)
 153 {
 154         at91_set_gpio_value(AT91_PIN_PA12, 1);  /* power down */
 155 }
 156
 157 static void at91sam9261ek_lcd_hw_init(void)
 158 {
 159         at91_set_A_periph(AT91_PIN_PB1, 0);     /* LCDHSYNC */
 160         at91_set_A_periph(AT91_PIN_PB2, 0);     /* LCDDOTCK */
 161         at91_set_A_periph(AT91_PIN_PB3, 0);     /* LCDDEN */
 162         at91_set_A_periph(AT91_PIN_PB4, 0);     /* LCDCC */
 163         at91_set_A_periph(AT91_PIN_PB7, 0);     /* LCDD2 */
 164         at91_set_A_periph(AT91_PIN_PB8, 0);     /* LCDD3 */
 165         at91_set_A_periph(AT91_PIN_PB9, 0);     /* LCDD4 */
 166         at91_set_A_periph(AT91_PIN_PB10, 0);    /* LCDD5 */
 167         at91_set_A_periph(AT91_PIN_PB11, 0);    /* LCDD6 */
 168         at91_set_A_periph(AT91_PIN_PB12, 0);    /* LCDD7 */
 169         at91_set_A_periph(AT91_PIN_PB15, 0);    /* LCDD10 */
 170         at91_set_A_periph(AT91_PIN_PB16, 0);    /* LCDD11 */
 171         at91_set_A_periph(AT91_PIN_PB17, 0);    /* LCDD12 */
 172         at91_set_A_periph(AT91_PIN_PB18, 0);    /* LCDD13 */
 173         at91_set_A_periph(AT91_PIN_PB19, 0);    /* LCDD14 */
 174         at91_set_A_periph(AT91_PIN_PB20, 0);    /* LCDD15 */
 175         at91_set_B_periph(AT91_PIN_PB23, 0);    /* LCDD18 */
 176         at91_set_B_periph(AT91_PIN_PB24, 0);    /* LCDD19 */
 177         at91_set_B_periph(AT91_PIN_PB25, 0);    /* LCDD20 */
 178         at91_set_B_periph(AT91_PIN_PB26, 0);    /* LCDD21 */
 179         at91_set_B_periph(AT91_PIN_PB27, 0);    /* LCDD22 */
 180         at91_set_B_periph(AT91_PIN_PB28, 0);    /* LCDD23 */
 181
 182         at91_sys_write(AT91_PMC_SCER, AT91_PMC_HCK1);
 183
 184         gd->fb_base = AT91SAM9261_SRAM_BASE;
 185 }
 186
 187 #ifdef CONFIG_LCD_INFO
 188 #include <nand.h>
 189 #include <version.h>
 190
 191 void lcd_show_board_info(void)
 192 {
 193         ulong dram_size, nand_size;
 194         int i;
 195         char temp[32];
 196
 197         lcd_printf ("%s\n", U_BOOT_VERSION);
 198         lcd_printf ("(C) 2008 ATMEL Corp\n");
 199         lcd_printf ("at91support@atmel.com\n");
 200         lcd_printf ("%s CPU at %s MHz\n",
 201                 AT91_CPU_NAME,
 202                 strmhz(temp, AT91_CPU_CLOCK));
 203
 204         dram_size = 0;
 205         for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
 206                 dram_size += gd->bd->bi_dram[i].size;
 207         nand_size = 0;
 208         for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
 209                 nand_size += nand_info[i].size;
 210         lcd_printf ("  %ld MB SDRAM, %ld MB NAND\n",
 211                 dram_size >> 20,
 212                 nand_size >> 20 );
 213 }
 214 #endif /* CONFIG_LCD_INFO */
 215 #endif
 216
 217 int board_init(void)
 218 {
 219         /* Enable Ctrlc */
 220         console_init_f();
 221
 222         /* arch number of AT91SAM9261EK-Board */
 223         gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9261EK;
 224         /* adress of boot parameters */
 225         gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 226
 227         at91_serial_hw_init();
 228 #ifdef CONFIG_CMD_NAND
 229         at91sam9261ek_nand_hw_init();
 230 #endif
 231 #ifdef CONFIG_HAS_DATAFLASH
 232         at91sam9261ek_spi_hw_init();
 233 #endif
 234 #ifdef CONFIG_DRIVER_DM9000
 235         at91sam9261ek_dm9000_hw_init();
 236 #endif
 237 #ifdef CONFIG_LCD
 238         at91sam9261ek_lcd_hw_init();
 239 #endif
 240         return 0;
 241 }
 242
 243 int dram_init(void)
 244 {
 245         gd->bd->bi_dram[0].start = PHYS_SDRAM;
 246         gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
 247         return 0;
 248 }
 249
 250 #ifdef CONFIG_RESET_PHY_R
 251 void reset_phy(void)
 252 {
 253 #ifdef CONFIG_DRIVER_DM9000
 254         /*
 255          * Initialize ethernet HW addr prior to starting Linux,
 256          * needed for nfsroot
 257          */
 258         eth_init(gd->bd);
 259 #endif
 260 }
 261 #endif