]> git.sur5r.net Git - u-boot/blob - board/atmel/at91sam9261ek/at91sam9261ek.c
6f15bc677671a3b9d80321c6f0a2206573d87219
[u-boot] / board / atmel / at91sam9261ek / at91sam9261ek.c
1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * (C) Copyright 2007-2008
4  * Stelian Pop <stelian@popies.net>
5  * Lead Tech Design <www.leadtechdesign.com>
6  */
7
8 #include <common.h>
9 #include <debug_uart.h>
10 #include <asm/io.h>
11 #include <asm/arch/at91sam9261.h>
12 #include <asm/arch/at91sam9261_matrix.h>
13 #include <asm/arch/at91sam9_smc.h>
14 #include <asm/arch/at91_common.h>
15 #include <asm/arch/at91_rstc.h>
16 #include <asm/arch/clk.h>
17 #include <asm/arch/gpio.h>
18 #include <lcd.h>
19 #include <atmel_lcdc.h>
20 #if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_DRIVER_DM9000)
21 #include <net.h>
22 #include <netdev.h>
23 #endif
24 #include <asm/mach-types.h>
25
26 DECLARE_GLOBAL_DATA_PTR;
27
28 /* ------------------------------------------------------------------------- */
29 /*
30  * Miscelaneous platform dependent initialisations
31  */
32
33 #ifdef CONFIG_CMD_NAND
34 static void at91sam9261ek_nand_hw_init(void)
35 {
36         struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
37         struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
38         unsigned long csa;
39
40         /* Enable CS3 */
41         csa = readl(&matrix->ebicsa);
42         csa |= AT91_MATRIX_CS3A_SMC_SMARTMEDIA;
43
44         writel(csa, &matrix->ebicsa);
45
46         /* Configure SMC CS3 for NAND/SmartMedia */
47 #ifdef CONFIG_AT91SAM9G10EK
48         writel(AT91_SMC_SETUP_NWE(2) | AT91_SMC_SETUP_NCS_WR(0) |
49                 AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(0),
50                 &smc->cs[3].setup);
51         writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(7) |
52                 AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(7),
53                 &smc->cs[3].pulse);
54         writel(AT91_SMC_CYCLE_NWE(7) | AT91_SMC_CYCLE_NRD(7),
55                 &smc->cs[3].cycle);
56 #else
57         writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
58                 AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
59                 &smc->cs[3].setup);
60         writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) |
61                 AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3),
62                 &smc->cs[3].pulse);
63         writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5),
64                 &smc->cs[3].cycle);
65 #endif
66         writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
67                        AT91_SMC_MODE_EXNW_DISABLE |
68 #ifdef CONFIG_SYS_NAND_DBW_16
69                        AT91_SMC_MODE_DBW_16 |
70 #else /* CONFIG_SYS_NAND_DBW_8 */
71                        AT91_SMC_MODE_DBW_8 |
72 #endif
73                        AT91_SMC_MODE_TDF_CYCLE(2),
74                        &smc->cs[3].mode);
75
76         at91_periph_clk_enable(ATMEL_ID_PIOC);
77
78         /* Configure RDY/BSY */
79         at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
80
81         /* Enable NandFlash */
82         at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
83
84         at91_set_A_periph(AT91_PIN_PC0, 0);     /* NANDOE */
85         at91_set_A_periph(AT91_PIN_PC1, 0);     /* NANDWE */
86 }
87 #endif
88
89 #ifdef CONFIG_DRIVER_DM9000
90 static void at91sam9261ek_dm9000_hw_init(void)
91 {
92         struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
93
94         /* Configure SMC CS2 for DM9000 */
95 #ifdef CONFIG_AT91SAM9G10EK
96         writel(AT91_SMC_SETUP_NWE(3) | AT91_SMC_SETUP_NCS_WR(0) |
97                 AT91_SMC_SETUP_NRD(3) | AT91_SMC_SETUP_NCS_RD(0),
98                 &smc->cs[2].setup);
99         writel(AT91_SMC_PULSE_NWE(6) | AT91_SMC_PULSE_NCS_WR(8) |
100                 AT91_SMC_PULSE_NRD(6) | AT91_SMC_PULSE_NCS_RD(8),
101                 &smc->cs[2].pulse);
102         writel(AT91_SMC_CYCLE_NWE(20) | AT91_SMC_CYCLE_NRD(20),
103                 &smc->cs[2].cycle);
104         writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
105                        AT91_SMC_MODE_EXNW_DISABLE |
106                        AT91_SMC_MODE_BAT | AT91_SMC_MODE_DBW_16 |
107                        AT91_SMC_MODE_TDF_CYCLE(1),
108                        &smc->cs[2].mode);
109 #else
110         writel(AT91_SMC_SETUP_NWE(3) | AT91_SMC_SETUP_NCS_WR(0) |
111                 AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(0),
112                 &smc->cs[2].setup);
113         writel(AT91_SMC_PULSE_NWE(4) | AT91_SMC_PULSE_NCS_WR(8) |
114                 AT91_SMC_PULSE_NRD(4) | AT91_SMC_PULSE_NCS_RD(8),
115                 &smc->cs[2].pulse);
116         writel(AT91_SMC_CYCLE_NWE(16) | AT91_SMC_CYCLE_NRD(16),
117                 &smc->cs[2].cycle);
118         writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
119                        AT91_SMC_MODE_EXNW_DISABLE |
120                        AT91_SMC_MODE_BAT | AT91_SMC_MODE_DBW_16 |
121                        AT91_SMC_MODE_TDF_CYCLE(1),
122                        &smc->cs[2].mode);
123 #endif
124
125         /* Configure Reset signal as output */
126         at91_set_gpio_output(AT91_PIN_PC10, 0);
127
128         /* Configure Interrupt pin as input, no pull-up */
129         at91_set_gpio_input(AT91_PIN_PC11, 0);
130 }
131 #endif
132
133 #ifdef CONFIG_LCD
134 vidinfo_t panel_info = {
135         .vl_col =               240,
136         .vl_row =               320,
137         .vl_clk =               4965000,
138         .vl_sync =              ATMEL_LCDC_INVLINE_INVERTED |
139                                 ATMEL_LCDC_INVFRAME_INVERTED,
140         .vl_bpix =              3,
141         .vl_tft =               1,
142         .vl_hsync_len =         5,
143         .vl_left_margin =       1,
144         .vl_right_margin =      33,
145         .vl_vsync_len =         1,
146         .vl_upper_margin =      1,
147         .vl_lower_margin =      0,
148         .mmio =                 ATMEL_BASE_LCDC,
149 };
150
151 void lcd_enable(void)
152 {
153         at91_set_gpio_value(AT91_PIN_PA12, 0);  /* power up */
154 }
155
156 void lcd_disable(void)
157 {
158         at91_set_gpio_value(AT91_PIN_PA12, 1);  /* power down */
159 }
160
161 static void at91sam9261ek_lcd_hw_init(void)
162 {
163         at91_set_A_periph(AT91_PIN_PB1, 0);     /* LCDHSYNC */
164         at91_set_A_periph(AT91_PIN_PB2, 0);     /* LCDDOTCK */
165         at91_set_A_periph(AT91_PIN_PB3, 0);     /* LCDDEN */
166         at91_set_A_periph(AT91_PIN_PB4, 0);     /* LCDCC */
167         at91_set_A_periph(AT91_PIN_PB7, 0);     /* LCDD2 */
168         at91_set_A_periph(AT91_PIN_PB8, 0);     /* LCDD3 */
169         at91_set_A_periph(AT91_PIN_PB9, 0);     /* LCDD4 */
170         at91_set_A_periph(AT91_PIN_PB10, 0);    /* LCDD5 */
171         at91_set_A_periph(AT91_PIN_PB11, 0);    /* LCDD6 */
172         at91_set_A_periph(AT91_PIN_PB12, 0);    /* LCDD7 */
173         at91_set_A_periph(AT91_PIN_PB15, 0);    /* LCDD10 */
174         at91_set_A_periph(AT91_PIN_PB16, 0);    /* LCDD11 */
175         at91_set_A_periph(AT91_PIN_PB17, 0);    /* LCDD12 */
176         at91_set_A_periph(AT91_PIN_PB18, 0);    /* LCDD13 */
177         at91_set_A_periph(AT91_PIN_PB19, 0);    /* LCDD14 */
178         at91_set_A_periph(AT91_PIN_PB20, 0);    /* LCDD15 */
179         at91_set_B_periph(AT91_PIN_PB23, 0);    /* LCDD18 */
180         at91_set_B_periph(AT91_PIN_PB24, 0);    /* LCDD19 */
181         at91_set_B_periph(AT91_PIN_PB25, 0);    /* LCDD20 */
182         at91_set_B_periph(AT91_PIN_PB26, 0);    /* LCDD21 */
183         at91_set_B_periph(AT91_PIN_PB27, 0);    /* LCDD22 */
184         at91_set_B_periph(AT91_PIN_PB28, 0);    /* LCDD23 */
185
186         at91_system_clk_enable(AT91_PMC_HCK1);
187
188         /* For 9G10EK, let U-Boot allocate the framebuffer in SDRAM */
189 #ifdef CONFIG_AT91SAM9261EK
190         gd->fb_base = ATMEL_BASE_SRAM;
191 #endif
192 }
193
194 #ifdef CONFIG_LCD_INFO
195 #include <nand.h>
196 #include <version.h>
197
198 void lcd_show_board_info(void)
199 {
200         ulong dram_size, nand_size;
201         int i;
202         char temp[32];
203
204         lcd_printf ("%s\n", U_BOOT_VERSION);
205         lcd_printf ("(C) 2008 ATMEL Corp\n");
206         lcd_printf ("at91support@atmel.com\n");
207         lcd_printf ("%s CPU at %s MHz\n",
208                 ATMEL_CPU_NAME,
209                 strmhz(temp, get_cpu_clk_rate()));
210
211         dram_size = 0;
212         for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
213                 dram_size += gd->bd->bi_dram[i].size;
214         nand_size = 0;
215         for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
216                 nand_size += get_nand_dev_by_index(i)->size;
217         lcd_printf ("  %ld MB SDRAM, %ld MB NAND\n",
218                 dram_size >> 20,
219                 nand_size >> 20 );
220 }
221 #endif /* CONFIG_LCD_INFO */
222 #endif
223
224 #ifdef CONFIG_DEBUG_UART_BOARD_INIT
225 void board_debug_uart_init(void)
226 {
227         at91_seriald_hw_init();
228 }
229 #endif
230
231 #ifdef CONFIG_BOARD_EARLY_INIT_F
232 int board_early_init_f(void)
233 {
234 #ifdef CONFIG_DEBUG_UART
235         debug_uart_init();
236 #endif
237         return 0;
238 }
239 #endif
240
241 int board_init(void)
242 {
243 #ifdef CONFIG_AT91SAM9G10EK
244         /* arch number of AT91SAM9G10EK-Board */
245         gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9G10EK;
246 #else
247         /* arch number of AT91SAM9261EK-Board */
248         gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9261EK;
249 #endif
250         /* adress of boot parameters */
251         gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
252
253 #ifdef CONFIG_CMD_NAND
254         at91sam9261ek_nand_hw_init();
255 #endif
256 #ifdef CONFIG_DRIVER_DM9000
257         at91sam9261ek_dm9000_hw_init();
258 #endif
259 #ifdef CONFIG_LCD
260         at91sam9261ek_lcd_hw_init();
261 #endif
262         return 0;
263 }
264
265 #ifdef CONFIG_DRIVER_DM9000
266 int board_eth_init(bd_t *bis)
267 {
268         return dm9000_initialize(bis);
269 }
270 #endif
271
272 int dram_init(void)
273 {
274         gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
275                 CONFIG_SYS_SDRAM_SIZE);
276
277         return 0;
278 }
279
280 #ifdef CONFIG_RESET_PHY_R
281 void reset_phy(void)
282 {
283 #ifdef CONFIG_DRIVER_DM9000
284         /*
285          * Initialize ethernet HW addr prior to starting Linux,
286          * needed for nfsroot
287          */
288         eth_init();
289 #endif
290 }
291 #endif