2 * (C) Copyright 2007-2008
3 * Stelian Pop <stelian@popies.net>
4 * Lead Tech Design <www.leadtechdesign.com>
6 * SPDX-License-Identifier: GPL-2.0+
10 #include <linux/sizes.h>
11 #include <asm/arch/at91sam9263.h>
12 #include <asm/arch/at91sam9_smc.h>
13 #include <asm/arch/at91_common.h>
14 #include <asm/arch/at91_matrix.h>
15 #include <asm/arch/at91_pio.h>
16 #include <asm/arch/clk.h>
18 #include <asm/arch/gpio.h>
19 #include <asm/arch/hardware.h>
21 #include <atmel_lcdc.h>
23 DECLARE_GLOBAL_DATA_PTR;
25 /* ------------------------------------------------------------------------- */
27 * Miscelaneous platform dependent initialisations
30 #ifdef CONFIG_CMD_NAND
31 static void at91sam9263ek_nand_hw_init(void)
34 at91_smc_t *smc = (at91_smc_t *) ATMEL_BASE_SMC0;
35 at91_matrix_t *matrix = (at91_matrix_t *) ATMEL_BASE_MATRIX;
38 csa = readl(&matrix->csa[0]) | AT91_MATRIX_CSA_EBI_CS3A;
39 writel(csa, &matrix->csa[0]);
43 /* Configure SMC CS3 for NAND/SmartMedia */
44 writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
45 AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
48 writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) |
49 AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3),
52 writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5),
54 writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
55 AT91_SMC_MODE_EXNW_DISABLE |
56 #ifdef CONFIG_SYS_NAND_DBW_16
57 AT91_SMC_MODE_DBW_16 |
58 #else /* CONFIG_SYS_NAND_DBW_8 */
61 AT91_SMC_MODE_TDF_CYCLE(2),
64 at91_periph_clk_enable(ATMEL_ID_PIOA);
65 at91_periph_clk_enable(ATMEL_ID_PIOCDE);
67 /* Configure RDY/BSY */
68 at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
70 /* Enable NandFlash */
71 at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
76 vidinfo_t panel_info = {
80 .vl_sync = ATMEL_LCDC_INVLINE_INVERTED |
81 ATMEL_LCDC_INVFRAME_INVERTED,
86 .vl_right_margin = 33,
90 .mmio = ATMEL_BASE_LCDC,
95 at91_set_pio_value(AT91_PIO_PORTA, 30, 1); /* power up */
98 void lcd_disable(void)
100 at91_set_pio_value(AT91_PIO_PORTA, 30, 0); /* power down */
103 static void at91sam9263ek_lcd_hw_init(void)
105 at91_set_a_periph(AT91_PIO_PORTC, 1, 0); /* LCDHSYNC */
106 at91_set_a_periph(AT91_PIO_PORTC, 2, 0); /* LCDDOTCK */
107 at91_set_a_periph(AT91_PIO_PORTC, 3, 0); /* LCDDEN */
108 at91_set_b_periph(AT91_PIO_PORTB, 9, 0); /* LCDCC */
109 at91_set_a_periph(AT91_PIO_PORTC, 6, 0); /* LCDD2 */
110 at91_set_a_periph(AT91_PIO_PORTC, 7, 0); /* LCDD3 */
111 at91_set_a_periph(AT91_PIO_PORTC, 8, 0); /* LCDD4 */
112 at91_set_a_periph(AT91_PIO_PORTC, 9, 0); /* LCDD5 */
113 at91_set_a_periph(AT91_PIO_PORTC, 10, 0); /* LCDD6 */
114 at91_set_a_periph(AT91_PIO_PORTC, 11, 0); /* LCDD7 */
115 at91_set_a_periph(AT91_PIO_PORTC, 14, 0); /* LCDD10 */
116 at91_set_a_periph(AT91_PIO_PORTC, 15, 0); /* LCDD11 */
117 at91_set_a_periph(AT91_PIO_PORTC, 16, 0); /* LCDD12 */
118 at91_set_b_periph(AT91_PIO_PORTC, 12, 0); /* LCDD13 */
119 at91_set_a_periph(AT91_PIO_PORTC, 18, 0); /* LCDD14 */
120 at91_set_a_periph(AT91_PIO_PORTC, 19, 0); /* LCDD15 */
121 at91_set_a_periph(AT91_PIO_PORTC, 22, 0); /* LCDD18 */
122 at91_set_a_periph(AT91_PIO_PORTC, 23, 0); /* LCDD19 */
123 at91_set_a_periph(AT91_PIO_PORTC, 24, 0); /* LCDD20 */
124 at91_set_b_periph(AT91_PIO_PORTC, 17, 0); /* LCDD21 */
125 at91_set_a_periph(AT91_PIO_PORTC, 26, 0); /* LCDD22 */
126 at91_set_a_periph(AT91_PIO_PORTC, 27, 0); /* LCDD23 */
128 at91_periph_clk_enable(ATMEL_ID_LCDC);
129 gd->fb_base = ATMEL_BASE_SRAM0;
132 #ifdef CONFIG_LCD_INFO
136 #ifdef CONFIG_MTD_NOR_FLASH
137 extern flash_info_t flash_info[];
140 void lcd_show_board_info(void)
142 ulong dram_size, nand_size;
143 #ifdef CONFIG_MTD_NOR_FLASH
149 lcd_printf ("%s\n", U_BOOT_VERSION);
150 lcd_printf ("(C) 2008 ATMEL Corp\n");
151 lcd_printf ("at91support@atmel.com\n");
152 lcd_printf ("%s CPU at %s MHz\n",
154 strmhz(temp, get_cpu_clk_rate()));
157 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
158 dram_size += gd->bd->bi_dram[i].size;
160 for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
161 nand_size += nand_info[i]->size;
162 #ifdef CONFIG_MTD_NOR_FLASH
164 for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++)
165 flash_size += flash_info[i].size;
167 lcd_printf (" %ld MB SDRAM, %ld MB NAND",
170 #ifdef CONFIG_MTD_NOR_FLASH
171 lcd_printf (",\n %ld MB NOR",
176 #endif /* CONFIG_LCD_INFO */
179 int board_early_init_f(void)
186 /* arch number of AT91SAM9263EK-Board */
187 gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9263EK;
188 /* adress of boot parameters */
189 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
191 #ifdef CONFIG_CMD_NAND
192 at91sam9263ek_nand_hw_init();
194 #ifdef CONFIG_HAS_DATAFLASH
195 at91_set_pio_output(AT91_PIO_PORTE, 20, 1); /* select spi0 clock */
196 at91_spi0_hw_init(1 << 0);
198 #ifdef CONFIG_USB_OHCI_NEW
202 at91sam9263ek_lcd_hw_init();
209 gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
210 CONFIG_SYS_SDRAM_SIZE);
215 #ifdef CONFIG_RESET_PHY_R